Stacked 3d package with improved bandwidth and power efficiency

Abstract

Stacked die packages such as PoP are used in space - constrained portable systems e,g. SmartPhones. The processor ( SoC ) and Mobile DRAM chips are stacked vertically to fit the combination within the restricted board space. The use of wire bonds in the memory chips as well as package level interconnects introduces delays into the data transmitted between the chips and limits the max. clock rate ( at present about 533 MHz for LP DDR 2 memory ) and hence the data transfer rate / bandwidth to less than 6.4 GB per sec. For Smart Phones to become capable of PC quality Games and high speed video would require a doubling of the bandwidth to over 12.8 GB per sec. To achieve that target PoP type packages were to be replaced by 3-d stacks using TSVs and wide I/Os. However recently JEDEC has postponed the introduction of Wide I/O Mobile memory stacks ( using TSVs ) to 2015. So the bandwidth of PoP packages must be improved. A physical way to increase the Bandwidth between the SoC and memory chips in a PoP is by increasing the max. no. of vertical I/Os as this allows more channels / higher parallelism in data transfer. This can be accomplished by shrinking the pitch ( from current 0.4 mm to 0.3 mm ) and doubling the number of rows of vertical I/Os ( from current 2 to 4 ) in PoP. However this requires major effort for the Packaging supply chain and would still fall well short of the future Bandwidth and interconnect Power efficiency targets. In this paper we will describe modifications and additions to the baseline PoP package so that it can be operated at clock rates up to 800 MHz and deliver bandwidth of 12.8 GB per sec or more and match the Interconnect Power efficiency of 3-d stacks with TSVs. Compensation features are introduced for ea. interconnect line between the SoC and Memory in the PoP package. The features are integrated on chips that are inserted between the two layers of the package. The vertical interconnection between the two levels of the PoP are replaced and routed through this additional chip. Only minor changes are required in the baseline PoP package thus will not require long delay to shrink current PoP interconnect pitch etc. The additional chip is built with available technologies and would increase cost by only a fraction of that needed for stacks with TSV-based wide I/O. Simulation results will be presented and compared with test results.