MNOS Memory Devices Research Articles

Charge trapping in MIOS memory structures under positive and negative biasing

Abstract Trapping phenomena which occur at the interface between the two insulating layers and in the SiO layer of the metal (Al)-insulator lpar;SiO)-oxide (SiO2)-semiconductor (Si) (MIOS) memory structures are considered. The performance of the devices is evaluated by measuring the flat-band voltage V FB as a function of different applied pulses on the gate. Pulses of 300μs duration with different amplitude (25-45 V) are sufficient for charge trapping in the MIOS structure. In order to erase the memory state a large negative pulse ( —40V amplitude and 3 ms duration) was applied leading to hole injection in the gate structure. The switching characteristics i.e. flat-band voltage variation with pulse duration is roughly logarithmic with time as has been observed in MNOS memory devices. The decay rate of the memory charge is 048V per decade of time measured in seconds for the electrons and 0-62 V per decade of time measured in seconds for the holes.

New scaling guidelines for MNOS nonvolatile memory devices

New phenomena in MNOS retention characteristics that originate from stored charge distribution are described and new scaling guidelines are indicated. The most significant phenomenon is that write-state retentivity is less dependent on the programmed depth, and is improved by reducing silicon nitride thickness. This behavior suggests that write-state charges are distributed rectangularly, while erase-state charges are distributed exponentially. The lower limit of the programming voltage is determined by write-state retentivity and not erase-state retentivity, and the write-state charge distribution depth determines the lower limit of silicon nitride thickness. The upper limit of the programming voltage is determined by erase-state retentivity after erase/write cycles. The scaling guidelines indicate that 16-Mb EEPROMs can be designed using MNOS memory devices. >

The effect of composition and exposure to external factors on the electronic structure of amorphous silicon nitride in memory devices

Silicon nitride is widely used in microelectronics as a charge storage layer in MNOS memory devices. It has been studied using soft X-ray emission spectroscopy. To understand fatigue phenomena in memory devices and the nature of localized states (LS) in the band gap, L 2,3 spectra of the valence band (VB) were obtained with attention being paid to the density of LS. a-SiN x and a-SiNx:H samples have been prepared by various methods. They were subjected to an electric field and to ultraviolet irradiation to model the degradation of devices. The investigation of a-SiN x showed that VB and especially LS spectra are very sensitive to composition changes. Increasing the nitrogen content of a-SiN x and a-SiN x:H causes a shift in the LS-spectrum to E c and separation of the maximum into two, as well as changes in the shape of the VB spectrum. It has been found that E field exposure and UV irradiation irradiation the formation of some new SiO bonds in the VB spectrum of SiN x with a shift of the main maximum of the LS spectrum to E c.

Yield and reliability of MNOS EEPROM products

MNOS electrically erasable and programmable read-only memory (EEPROM) products have been manufactured using 2- mu m CMOS fabrication technology, in which MNOS memory devices are composed of a 1.6-nm tunnel SiO/sub 2/ layer and a 28-nm Si/sub 3/N/sub 4/ layer. The Hitachi MNOS EEPROM family consists of a 64-kb EEPROM with static random access memory (SRAM) timing and three EEPROM on-chip microcomputers. Electrical and quality tests establish two basic reliability features: ten-year data retention and 10/sup 5/ erase/write cycle endurance. The MNOS EEPROM family yield has reached the same high level as that of SRAM products fabricated with the same 2- mu m CMOS technology. In addition, high-density low-cost MNOS EEPROM products are possible because of the high scalability and high yield attributable to their simple cell structure. >

A new model for the discharge behaviour of metal-nitride-oxide-silicon (MNOS) non-volatile memory devices

A new model is presented for the discharge mechanism of MNOS memory devices. For moderate and large charge contents the discharging effect can actually be ascribed to the compensation of the stored charge by the injection from the silicon into the nitride of carriers of the opposite type.

Carrier conduction characteristics of si gate mnos memory device

AbstractThe carrier conduction characteristics during erase and write in Si‐gate‐type MNOS memory devices with thin oxide (∼2 nm) have been investigated by comparison with the conventional Al‐gate type. As a result, it has been confirmed that as in Al‐gate type, the carrier injection between the substrate and the gate insulator is dominated by electron injection from the substrate into the gate insulator under positive gate bias, and by hole injection from the substrate into the gate insulator under negative gate bias. However, unlike in the conventional Al‐gate type, the carrier conduction mechanism in nitride for Si‐gate MNOS memory is determined by different mechanisms under positive and negative gate biases, attributed mainly to the difference in carrier injection from the gate electrode.

Scaling Down MNOS Nonvolatile Memory Devices

Scaling down of MNOS nonvolatile memory devices are presented. Knowledge of operating mechanisms of the electrically alterable nonvolatile memory provides guidelines for choosing the proper thickness of the gate insulating films (Si3N4 and SiO2). It is found that writing time of an MNOS device depends on the nitride thickness alone but not on the oxide thickness, while erasing time depends on the thicknesses of both films. A 10-V programmable scaled down MNOS memory device is realized by decreasing nitride thickness from 50 nm to 19.5 nm and keeping oxide thickness almost constant at about 2.1 nm. Experimental devices are shown to be highly reliable, if the Si3N4 is slightly oxidized, resulting in an MONOS structure.

Electron injection parameters and memory characteristics of MNOS devices

AbstractThe charge injection mechanism of MNOS memory devices is analyzed in terms of the effective electron occupation function fT(t) of N‐O interface traps, and the flat‐band voltage (VFB) shift is derived as a function of pulse voltage and pulsewidth. The N‐O interface trap density NT is determined from the charge injection parameters (vO, r, n). According to the measurement using an automatic VFB measurement device, NT is 1 ‐ 3.6 × 1016 m−2. The parameter vO relating to tunneling in the absence of the applied voltage is dependent on Nss; 3 × 10−9 s−1 for samples with large Nss and 1.4 × 10−12‐1 × 10−18 s−1 for samples with small Nss. The calculated results of the pulse voltage and pulsewidth characteristics using these values agree with the measured results. The present analysis method is applicable for samples with different permittivity, film thickness and fabricating conditions as long as the nitrided film current can be ignored.

The mechanism of N-H bond decomposition in silicon nitride films

Thin dielectric films produced by the ammonolysis of monosilane in the temperature range 750–900 °C have 5–30% of their nitrogen atoms and 0.5–5% of their silicon atoms chemically bonded with hydrogen. We investigated the process of N-H bond decomposition under heat treatment at 900–1100 °C in vacuum and in different ambient gases by means of multiple internal reflection spectroscopy in the IR. It was found that in vacuum or in an inert gas ambient the activation energy of the process is 65 ± 2 kcal mol −1, which is close to the N-H bond dissociation energy. When hydrogen or ammonia are added to the inert gas the activation energy of the process increases; pureammonia ( P NH 3 = 1.01 × 10 3 hPa) or hydrogen ( P h 2 = 1.01 × 10 3 hPa) suppress the decomposition entirely. The mechanism of the process and some features of the degradation of MNOS memory devices are discussed.

Dynamic Injection MNOS Memory Devices

Dynamic Injection MNOS (DIMNOS) memory devices are proposed which feature high speed writing, 5 V drain voltage and a dynamic RAM with MNOS backup. These devices have one or two control gates and one MNOS memory between the control gates and field SiO2 layer. In the above structures, the inversion layer under the MNOS gate is filled with charges transferred from the source through the control gates while writing voltage is being applied to MNOS gate. Then, the control gates are electrically closed and the stored charge in the inversion layer is injected into the interface between the thin SiO2 and Si3N4 layers in the MNOS. In the experimental results, N-channel Si-gate DIMNOS memory devices are written as fully as conventional MNOS memories in less than 50 nanoseconds. Furthermore, in the dynamic inhibited writing mode, writing is indeed inhibited with pulse widths shorter than 1.0 msec if the number of inhibited writing attempts is kept to less than 103 by writing pulse shape improvement.

Valence alternation pair model of charge storage in MNOS memory devices

Certain point defects in amorphous silicon nitride called valence alternation pairs (VAP) appear to be able to account not only for the charge storage and decay characteristics of MNOS memory devices but also for the fatigue phenomena that occur in these devices after undergoing a sufficiently large number of write-erase operations. The theory and properties of VAP defects in the nitride are described. A model for the MNOS memory device based on the existence of VAP defects in the nitride is proposed. Charge storage, decay, and fatigue characteristics of MNOS devices are explained in terms of the model.

Characteristics of interface-doped MNOS memory devices

The results of an investigation of the characteristics of MNOS memory devices are given in which the interface between the oxide and nitride was doped with a few monolayers of various refractory metals. In particular, write speeds of the order of microseconds could be obtained along with retention times which could be extrapolated to many decades. No temperature dependence could be found for the decay of stored charge between 77 K and 300°C, indicating that retention is normally dominated by Fowler-Nordheim back tunneling from the interface. Long time exposure to high gate voltages and write/erase cycling in excess of 1000 cycles sharply reduces the achievable memory window, and is accompanied by the copious generation of fast surface states, at least in p-channel devices.

Cross-gate MNOS memory device

A novel MNOS device structure is described. It solves the parasitic leakage problem, sometimes also known as the sidewalk effect.

The effect of electrical conduction of Si3N4on the discharge of MNOS memory transistors

It is proposed that the discharge of MNOS memory devices proceeds through a combination of direct tunneling from charge traps in the silicon nitride into the silicon, and charge migration through the nitride by a series of Poole-Frenkel emission-drift-capture events. The discharge of MNOS transistors calculated from this model by computer agrees well with experimental data taken at elevated temperatures on SOS/MNOS devices with LPCVD nitrides. Parameter values used indicate a very low value of electron mobility. The discharge rate at elevated temperatures is predicted to be sensitive to whether the silicon under the gate is in accumulation or depletion during the discharge.

Writing of gold-doped MNOS memory devices

Gold diffusions at 900°C were carded out for diffusion times of 10, 20, and 40 min, on the MNOS devices with chemically oxidized n-type substrates. It was found that the switching speed with negative write pulses was improved 15-40 times over the control devices by 20-min gold diffusion. The writing speed is degraded with longer diffusion time because the increased accumulation of gold at the Si-SiO 2 interface serves effectively to increase the minority carrier relaxation time and scattering effects. It was also found that the presence of the acceptor traps and accumulation near and at the Si-SiO 2 interface in the MNOS system degrade the writing speed for positive pulses.

Charge distribution in the nitride of MNOS memory devices

The steady state charge distribution for weakly occupied traps is a universal function of position over most of the nitride, with dielectric constant and Frenkel-Poole coefficient α being the only material parameters. The transient charge distribution for constant current pulses is approximated by truncating the steady state distribution and the resulting relation between charge content and its centroid is used to fit experimental data which provides α-values of a reasonable magnitude. A diffusive component of charge motion during application of alternating polarity voltage pulses is identified, and its diffusion coefficient is related to the Frenkel-Poole emission rate from traps.

The Effects of High Temperature Annealing on MNOS Devices

The effects of high temperature annealing on the conduction and memory properties of MNOS memory devices was studied. The results showed that the conductivity of the nitride increased with annealing time and temperature and that the memory retention qualities of the device were degraded. These results can be explained by the hypothesis that the heat‐treatment has increased the number of traps in the silicon nitride. The correlation of the theoretical and experimental results indicates that the traps are uniformly distributed through the silicon nitride layer and are not localized at the oxide nitride interface.

Radiation-Induced Memory Loss in Thin-Oxide MNOS Devices

A theoretical model is proposed for the radiation-induced memory loss effect in thin-oxide MNOS memory devices. The model treats the stored charge as being located in the nitride, at an average distance from the silicon much larger than the oxide thickness. Under these conditions the radiation-induced conductivity in the nitride determines the decay of stored charge. It is proposed that the radiation-induced conductivity in the nitride is due to radiation-induced carriers drifting in the electric field during the slowing down process, and that the carriers become trapped before reaching thermal equilibrium. In calculating the radiation-induced nitride conductivity, a continuous slowing-down process is assumed. In addition, it is assumed that the radiation-induced carriers are generated according to a 1/(Energy) law. Although values for some of the parameters in the model are not known, it is shown that experimental values of the radiation-induced memory loss rate are consistent with physically reasonable values of the unknown parameters.

Nonsteady-state techniques for determining the energy distribution of interface traps in MNOS (memory) devices

New techniques are used to obtain the energy distribution of interface traps throughout the band gap of MNOS devices. The techniques are based on thermal and isothermal dielectric relaxation current techniques. It is demonstrated that the techniques are capable of detecting small changes in the trap distribution, such as might occur due to ageing or termperature cycling.

The implanted stepped-oxide MNOSFET

A novel MNOSFET device structure has been demonstrated to solve a serious problem with MNOS memory devices. The new structure eliminates the parasitic FET devices which are formed in parallel with the variable threshold MNOSFET when the conventional device structure is used.