Charge trapping in MIOS memory structures under positive and negative biasing

Abstract

Abstract Trapping phenomena which occur at the interface between the two insulating layers and in the SiO layer of the metal (Al)-insulator lpar;SiO)-oxide (SiO2)-semiconductor (Si) (MIOS) memory structures are considered. The performance of the devices is evaluated by measuring the flat-band voltage V FB as a function of different applied pulses on the gate. Pulses of 300μs duration with different amplitude (25-45 V) are sufficient for charge trapping in the MIOS structure. In order to erase the memory state a large negative pulse ( —40V amplitude and 3 ms duration) was applied leading to hole injection in the gate structure. The switching characteristics i.e. flat-band voltage variation with pulse duration is roughly logarithmic with time as has been observed in MNOS memory devices. The decay rate of the memory charge is 048V per decade of time measured in seconds for the electrons and 0-62 V per decade of time measured in seconds for the holes.