Μm SiGe Research Articles

Dispersion study of DC and Low Frequency Noise in SiGe:C Heterojunction Bipolar Transistors used for mm-Wave to Terahertz applications

This work presents an investigation of DC and Low Frequency Noise dispersion in 0.13μm SiGe:C BiCMOS Heterojunction Bipolar Transistors (HBTs) used for mm-Wave to Terahertz applications. Therefore, DC and Low Frequency Noise measurements have been performed over a half wafer on a large number of transistors. A statistical 1/f noise compact model is presented as well as a study of the repartition of generation-recombination components. The main Low Frequency Noise sources are found to be homogenously distributed in the intrinsic base-emitter junction. The mean 1/f noise level, evaluated by the figure of merit KBmean, is equal to 6 10−10μm2.

Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming

We introduce a ladder filter-based programmable time-delay element for beamforming in ultra-wideband (UWB) systems. Such a lumped-element realization becomes possible by approximating e -std as a ratio of polynomials (based on Taylor and Pade expansions). When compared with conventional methods based on the tapped delay-line architecture, the proposed technique achieves lower power dissipation, higher delay range and resolution, and better area efficiency. A prototype delay line designed for the 3.1-10.6 GHz UWB range achieves a delay range of 140 ps and a gain range of -30 dB to +10 dB. Fabricated in a 0.25 μm SiGe BiCMOS process, the delay element occupies an active area of 1 mm 2 and consumes 53 mW from a 2.5 V supply. A four-antenna beamforming system using the delay element can achieve a scanning range of ±61 ° with 0.86 ° resolution for an antenna spacing of 15 mm.

100MHz to 2.5GHz RF Detector Based on SiGe HBT

A RF received signal strength indication (RSSI) circuit with 100MHz to 2.5GHz frequency bandwidth was designed based on Jazz 0.18 μm SiGe HBT process. The RSSI was composed of 4 cascaded limiting amplifier and full wave current rectifier. A novel DC offset compensation circuit was adopted to achieve stable operating point. The circuit was simulated with Cadence design kit. Results showed that the RSSI had a wide dynamic range from 45dBm to 0dBm, operated at a 3.3V single supply. The power consumption is 18.8mW.

0.3–4.3 GHz Frequency-Accurate Fractional-$N$ Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital $\Delta$-$\Sigma$ Modulator-Based Divider Controller

If the modulus of the digital delta-sigma modulator (DΔΣM) in a fractional- N frequency synthesizer is a power of two, then the output frequency is constrained to be a rational multiple of the phase detector frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PD</sub> ), where the denominator of the rational multiplier is a power of two. If the required output frequency is not related to f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PD</sub> in this way, one is forced to approximate the ratio by using a small programmable modulus DΔΣM or a very large power-of-two modulus. Both of these solutions involve additional hardware. Furthermore, the programmable modulus solution can suffer from spurs, while the large power of two lacks accuracy. This paper presents a new solution, based on mixed-radix algebra, where the required ratio is formed by combining two different moduli. The programmable modulus solves the accuracy problem, while the large power-of-two modulus minimizes the spur content. In addition, the phase detector can be clocked at high speed. This paper explains the theoretical foundations of the method, elaborates a design methodology, and presents measured results for an 0.18 μm SiGe BiCMOS prototype.

Encrypted communications: towards very low consumption frequency-hopping active filters

The principal techniques of coding used for secure encrypted communications are first indicated. Then, after a brief recall of the essential points of frequency-agile filters, a second order frequency-hopping bandpass filter operating in current mode and implemented with CCCII is introduced. It necessitates six CCCII only and uses an improved multiple feedback loop connected in such a way that all of its frequency-agile filters of classes 0, 1, 2 and 3 are available. This very low consumption active filter so offers the advantage to have four central frequencies selected digitally for each value of its bias current. Validation results in 0.25 μm SiGe BiCMOS technology are given. They highlight the new perspectives for encrypted communications to be expected from this approach.

Analysis of scalable two-π equivalent-circuit model for on-chip spiral inductors

High-accuracy inductor model is vital for the success of RF/mm-wave circuit design. In this article, the development of two-π scalable model with four ladder skin effect structure has been described in detail. For the scalable compact circuit modeling, a set of formulas by which all of the compact circuit elements can be calculated according to the components geometric dimensions and process parameters will be given. The proposed modeling method is regarded as full scalable as all the component parameters are calculated by physical equations or revise equations. A series of spiral inductors with various geometries have been fabricated with 0.13 µm SiGe BiCMOS aluminum process to verify the model. Excellent agreements are obtained between the measured data and calculation form the proposed model up to frequencies above self-resonant. This scalable 28-element two-π model enables to accurately characterize RF behaviors of on-chip spiral inductors and optimize the inductor performance. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:93-100, 2015.

A Low-Loss and High Isolation D-Band SPDT Switch Utilizing Deep-Saturated SiGe HBTs

A single-pole double-throw switch, utilizing double-shunt, deep-saturated HBTs is implemented in a 0.13 μm SiGe BiCMOS technology, occupying 0.36 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of IC area. A superior switch performance is identified when HBTs are operated in saturation regime, and state of the art performance is achieved at D-band frequencies from 96 to 163 GHz. Measurements show a minimum insertion loss of 2.6 dB at 120 and 150 GHz, a highest isolation of 29 dB at 120 GHz and an input 1 dB compression point of 17 dBm at 94 GHz, outperforming similar implementations in deep-scaled CMOS technologies.

Tunable 245 GHz transmitter and receiver in SiGe technology for gas spectroscopy

A 245 GHz sensor system for gas spectroscopy is presented, which includes an integrated SiGe transmitter (TX) and receiver (RX), and a 0.6 m-long gas absorption cell between the TX and RX modules. The integrated local oscillators (LOs) of TX and RX chips are controlled by two external phase-locked loops (PLLs), whose reference frequencies are swept with constant frequency offset for a low intermediate frequency of the RX. The RX consists of a differential low-noise amplifier, an integrated 122 GHz LO with a 1/64 divider, a 90° differential hybrid and an active subharmonic mixer. The TX consists of an integrated 122 GHz LO with a 1/64 divider, and a frequency doubler. The TX and RX chips are fabricated in 0.13 µm SiGe BiCMOS technology with f T/f max of 300 GHz/500 GHz. Using external dielectric lenses for the TX and RX modules, the gas absorption spectra were measured for acetonitrile and methanol.

A SiGe LC-ladder low noise amplifier with base resistance match, gain and noise flatness for UWB applications

This study presents a 3.1–10.6GHz ultra-wideband low noise amplifier (UWB LNA) in 0.18µm SiGe HBT technology. To achieve a good input match, parasitic base resistance in a bipolar transistor and an LC-ladder filter are included into calculations with the common-emitter topology using shunt–shunt capacitive feedback. Both high and flat power gain (S21) and low and flat noise figure (NF) are achieved by adjusting the pole and zero in amplifying stage and quality factors of the fourth-order input network. Design equations for performances such as gain, noise figure and linearity IIP3 are derived especially on gain flatness and noise flatness. LNA dissipates 33mW power and achieves S21 of 20.65+0.7dB, NF of 2.79+0.2dB over the band of 3.1–10.6GHz. The simulated input third-order intermodulation point (IIP3) is −17dBm at 10GHz.

High-speed continuous-time band pass ΔΣ modulator for class-S systems

A fully integrated continuous-time bandpass delta-sigma modulator (BPDSM) fabricated in a 0.25μm SiGe BiCMOS is presented. It consists of a two-stage second-order resonator, high-speed comparator, multi-feedback current digital-to-analog converter, and an output buffer. The input frequency can be tuned from 3.55 to 3.9GHz at a 9.5GHz fixed sampling clock frequency. This modulator dissipates 109mA from a 3.3V power supply. The peak signal-to-noise ratio (SNR) of the sine-wave input is 37.3dB in a 20MHz channel bandwidth, and the error vector magnitude (EVM) of a 64QAM long-term evolution (LTE) downlink signal is 5.94% with a 10.5dB peak-to-average-power ratio (PAPR).

A high linearity SiGe HBT LNA for GPS receiver

A high linearity 1.575 GHz SiGe:HBT low noise amplifier (LNA) for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process. A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1.11 dB, a power gain of 18 dB, an output 1 dB compression point of +7.8 dBm and an input third-order intercept point of +1.8 dBm. The chip occupies a 500 × 560 μm2 area and consumes 3.6 mA from a 2.85 V power supply.

Integrated Multichannel Electronics for High Performance Time Correlated Single Photon Counting

The analysis of extremely weak, ultrafast and periodical light signals is increasingly widespread in a large number of fields, from chemistry and biology to telemetry and communication, and in a great variety of applications, from quantum cryptography to fluorescence imaging.Speaking of fluorescent lifetime analysis, for example, the detection of very faint and fast optical signals is fundamental to investigate the complex interactions between molecules that play a key role in many crucial issues such as the origin and growth mechanisms of tumors. In this domain the Time-Correlated Single Photon Counting (TCSPC) technique is very effective to reconstruct the light waveform when both extremely high time resolution and linearity are required.TCSPC is based on the detection of single photons and on the record of their arrival times: if the probability of detecting a photon during one excitation cycle is far less than one, the histogram of photon arrivals per time bin exactly corresponds to the temporal trend of the light signal. In order to properly reconstruct the light waveform a time measurement block featuring very high performance is necessary: this circuit has to be able to measure time intervals of few hundreds of nanoseconds with picosecond time resolution and a differential non-linearity much lower than few percents of the time bin width.Moreover a growing number of techniques do now require to collect data from multiple channels at the same time. Förster Resonance Energy Transfer (FRET), Fluorescence Diffuse Optical Tomography (FDOT) and single-molecule spectroscopy, for example, can benefit a lot of a system capable of providing simultaneous analysis in temporal or spectral range. Indeed, concurrency not only reduces the measurement time, revealing dynamic phenomena even on very short timescales but it also opens the way to spectrally resolved measurements that analyze different events occurring simultaneously, like Fluorescence Cross-Correlation Spectroscopy (FCCS).Nevertheless the development of a truly parallel acquisition system featuring both high performance and a high number of independent channels is still an open challenge: to achieve this goal the design of a time measurement circuit capable of acquiring data from several channels in parallel while providing high performance on each channel is of the utmost importance. In this work a fully integrated array of 16 time to amplitude converters (TAC) designed in 0.35µm SiGe technology is presented.The first simulations show very high performance on each channel with a FWHM time resolution lower than 19ps and a differential non linearity lower than 0.4% peak-to-peak of the LSB. In order to reduce the overall area of the chip, pairs of converter stages share all the conversion chain through a 2 input multiplexer. The simulated dead time on the entire full scale range is 191ns, corresponding to a maximum conversion frequency of 5.24MHz per channel. The obtained results on the designed 16 channel TAC array are extremely good and, if the performance are verified by experimental measurements, this array will be one of the fundamental blocks of a fully parallel high-performance TCSPC acquisition system. Based on high efficiency fully custom single photon detectors (SPAD) and on a front-end electronics specifically designed to properly work with these sensors, the final system will be the upgrade of a few channels high performance acquisition chain already developed in the same technology.

Phase-synchroniser based on gm-C all-pass filter chain with sliding mode control

Phase-synchronisers have many applications in VLSI circuit designs. They are used in CMOS RF circuits including phase (de)modulators, phase recovery circuits, multiphase synthesis, etc. In this article, a phase-synchroniser based on gm-C all-pass filter chain with sliding mode control is presented. The filter chain provides good controllable delay characteristics over the full range of phase and frequency regulation, without deterioration of input signal amplitude and waveform, while the sliding mode control enables us to achieve fast and predetermined finite locking time. IHP 0.25 µm SiGe BiCMOS technology has been used in design and verification processes. The circuit operates in the frequency range from 33 MHz up to 150 MHz. Simulation results indicate that it is possible to achieve very fast synchronisation time period, which is approximately four time intervals of the input signal during normal operation, and 20 time intervals during power-on.

Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer

A millimeter wave frequency mixed-signal design of a 1-tap half-rate look-ahead decision feedback equalizer for 80 Gb/s short-reach optical communication systems is presented. On-wafer tests are developed to determine the maximum operating bit rate of the equalizer. Results are also presented for intersymbol interference mitigation at 80 Gb/s for a 20 GHz bandwidth-limited channel. Further improvements on the architecture of the 80 Gb/s equalizer are discussed and used in the design and on-wafer measurement of a 110 Gb/s equalizer. The equalizers are designed in a 0.13 μm SiGe:C BiCMOS technology. The 80 and 110 Gb/s versions dissipate 4 and 5.75 W, respectively and occupy 2 and 2.56 mm2, respectively.

A 16.5–28 GHz 0.18-$\mu$m BiCMOS Power Amplifier With Flat $19.4 \pm 1.2$ dBm Output Power

A broadband fully integrated power amplifier (PA) with 3 dB bandwidth from 16.5 to 28 GHz was designed using a 0.18 μm SiGe BiCMOS process. The PA consists of a drive amplifier and two parallel main amplifiers. Lumped-element Wilkinson power divider and combiner are especially used to combine the main amplifiers as well as to provide suppression for the harmonics through their inherent low-pass filtering characteristic. The PA exhibits measured gain of more than 34.5 dB and very flat output power of 19.4±1.2 dBm across 16.5-28 GHz, and power added efficiency (PAE) higher than 20% and 17% between 16-24.5 GHz and up to 28 GHz, respectively. Specifically at 24 GHz, it achieves 19.4 dBm output power, 22.3% PAE, and 37.6 dB gain.

KLauS: an ASIC for silicon photomultiplier readout and its application in a setup for production testing of scintillating tiles

KLauS is an ASIC produced in the AMS 0.35 μm SiGe process to read out the charge signals from silicon photomultipliers.Developed as an analog front-end for future calorimeters with highgranularity as pursued by the AHCAL concept in the CALICEcollaboration, the ASIC is designed to measure the charge signal ofthe sensors in a large dynamic range and with low electronic noisecontributions. In order to tune the operation voltage of each sensorindividually, an 8-bit DAC to tune the voltage at the input terminalwithin a range of 2V is implemented. Using an integrated fastcomparator with low jitter, the time information can be measured withsub-nanosecond resolution. The low power consumption of the ASIC canbe further decreased using power gating techniques. Future versionsof KLauS are under development and will incorporate an ADC with aresolution of up to 12-bits and blocks for digital data transmission.The chip is used in a setup for mass testing and characterization ofscintillator tiles for the AHCAL test beam program.

Indirect Back-Gate Coupling Quadrature LC-VCO

This letter presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two p-core cross-coupled voltage-controlled oscillators (VCOs) using indirect back-gate coupling. In conventional direct-back coupling the resonator's voltage swing, tuning range, and quality factor are respectively limited by the forward-conducting back-gate junction cut-in voltage, diffusion capacitance and small dynamic resistance. To generate quadrature phase signals with strong coupling strength and large output swing, the proposed design uses pMOSFETs as buffers between the back-gate diode and LC tank to eliminate the drawback in existing back gate coupling QVCOs. The proposed CMOS QVCO has been implemented with the TSMC 0.18 μm SiGe 3P6M technology. At the supply voltage of 0.8 V, the total power consumption is 4.4 mW. The free-running frequency of the QVCO is tuneable from 5.96 GHz to 6.60 GHz as the tuning voltage is varied from 0.0 V to 0.8 V. The measured phase noise at 1 MHz frequency offset is -120.5 dBc/Hz at the oscillation frequency of 6.59 GHz and the figure of merit (FOM) of the proposed QVCO is -190.4 dBc/Hz.

Coupled Dual LC Tanks Based ILFD With Low Injection Power and Compact Size

This letter presents a fully differential injection locked frequency divider using coupled dual LC tanks. The proposed injection locked frequency divide-by-2 divider achieves a wide locking range with low injected power levels. The divider, fabricated in 0.18 μm SiGe BiCMOS process achieves a locking range of 3.77 GHz with an injected power as low as -16 dBm, a phase noise of -116 dBc/Hz at 10 kHz offset with an input referred phase noise of -109.7 dBc/Hz at 10 kHz offset at 25 GHz, maximum output power of -2.44 dBm, efficiency of 18.5% and the dc power consumption is 4.8 mW.

An X-Band Slow-Wave T/R Switch in 0.25-$\mu\hbox{m}$ SiGe BiCMOS

This brief presents a fully integrated X-band transmit/receive (T/R) switch using slow-wave transmission lines for X-band phased-array radar applications. The T/R switch was fabricated in a 0.25- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu\hbox{m}$</tex></formula> SiGe bipolar CMOS (BiCMOS) process and occupies 0.73- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{mm}^{2}$</tex></formula> chip area, excluding pads. The switch is based on shunt–shunt topology and employs isolated n-channel (NMOS) transistors and slow-wave microstrip lines. Additionally, resistive body floating and dc biasing are employed to improve the power-handling capability <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$({P}_{1\, {\rm dB}})$</tex></formula> of the switch. The T/R switch resulted in a measured insertion loss of 2.1–2.9 dB and isolation of 39–42 dB from 8 to 12 GHz. The input referred <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${P}_{1\, {\rm dB}}$</tex></formula> is 27.6 dBm at 10 GHz. To our knowledge, this brief presents the utilization of slow-wave transmission lines in T/R switches for the first time. Furthermore, it can simultaneously satisfy stringent isolation, insertion loss, and power-handling capability requirements for implementing a fully integrated SiGe T/R module.

Linearity improvement analysis for power amplifiers at mm‐wave frequencies

ABSTRACTThis article presents an adaptive predistortion (APD) linearization technique to improve the linearity of millimeter‐wave power amplifiers (PAs), specifically at 60 GHz. The PA and the APD were designed using the 0.13 µm SiGe BiCMOS process. The predistortion is applied to the PA by varying the gain of the PA through its variable gain amplifier. The PA achieves a PSAT of 11.97 dBm and of −10 dBm. After linearization the PA has an improved of −6 dBm. This linearization technique results in an optimum intermodulation distortion 3rd reduction of 10 dB. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:743–748, 2014