Μm SiGe Research Articles

Design of AD Converters in 0.35 µm SiGe BiCMOS Technology for Ultra-Wideband M-Sequence Radar Sensors.

The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter's own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of -3.3 V.

A rail-to-rail high speed comparator with LVDS output in 0.18-[formula omitted]m SiGe BiCMOS Technology

Achieving low propagation delay in comparators under low input overdrive voltage is challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed comparator. By clamping the output node of the current summation circuit relative to a fixed level VC, the overdrive recovery time under large signal is successfully reduced. Moreover,by adopting a cascaded approach with multiple stages of high bandwidth and low gain,not only is the comparator’s gain enhanced,but it also acquires higher bandwidth. Ultimately, the comparator’s output is transmitted at high speed through an LVDS interface. This design is implemented using 0.18μm SiGe BiCMOS technology. Simulation results show that the comparator has a static power consumption of 26.4 mW, and for 5 mV input overdrive, the average propagation delay is about 1.09 ns.

A 26-28 GHz, Two-Stage, Low-Noise Amplifier for Fifth-Generation Radio Frequency and Millimeter-Wave Applications.

This paper presents a high-gain low-noise amplifier (LNA) operating at the 5G mm-wave band. The full design combines two conventional cascode stages: common base (CB) and common emitter (CS). The design technique reduces the miller effect and uses low-voltage supply and low-current-density transistors to simultaneously achieve high gain and low noise figures (NFs). The two-stage LNA topology is analyzed and designed using 0.25 µm SiGe BiCMOS process technology from NXP semiconductors. The measured circuit shows a small signal gain at 26 GHz of 26 dB with a gain error below 1 dB on the entire frequency band (26-28 GHz). The measured average NF is 3.84 dB, demonstrated over the full frequency band under 15 mA current consumption per stage, supplied with a voltage of 3.3 V.

Design and Realization of Ultra-Wideband Differential Amplifiers for M-Sequence Radar Applications.

Amplification of wideband high-frequency and microwave signals is a fundamental element within every high-frequency circuit and device. Ultra-wideband (UWB) sensor applications use circuits designed for their specific application. The article presents the analysis, design, and implementation of ultra-wideband differential amplifiers for M-sequence-based UWB applications. The designed differential amplifiers are based on the Cherry-Hooper structure and are implemented in a low-cost 0.35 µm SiGe BiCMOS semiconductor process. The article presents an analysis and realization of several designs focused on different modifications of the Cherry-Hooper amplifier structure. The proposed amplifier modifications are focused on achieving the best result in one main parameter's performance. Amplifier designs modified by capacitive peaking to achieve the largest bandwidth, amplifiers with the lowest possible noise figure, and designs focused on achieving the highest common mode rejection ratio (CMRR) are described. The layout of the differential amplifiers was created and the chip was manufactured and wire-bonded to the QFN package. For evaluation purposes, a high-frequency PCB board was designed. Schematic simulations, post-layout simulations, and measurements of the individual parameters of the designed amplifiers were performed. The designed and fabricated ultra-wideband differential amplifiers have the following parameters: a supply current of 100-160 mA at -3.3 V or 3.3 V, bandwidth from 6 to 12 GHz, gain (at 1 GHz) from 12 to 16 dB, noise figure from 7 to 13 dB, and a common mode rejection ratio of up to 70 dB.

A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation

This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60 GHz wireless communication systems. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operations to deliver better channel utilization and faster response times for the system. The isolation between the transmitter and receiver from the architecture design to system integration for FD operations has been fully considered. A digital self-interference cancellation (DSIC) is implemented in MATLAB to verify the FD performance. The super-heterodyne architecture with an intermediate frequency (IF) of 12 GHz is designed to suppress the image frequencies without using extra filters. A flexible phase-locked loop (PLL) synthesizer provides a local oscillator (LO) frequency with a 2 kHz resolution. Other than the time division duplex (TDD) mode used in the conventional 60 GHz system, a wide-bandwidth baseband digital variable-gain amplifier (DVGA) with a 3 dB bandwidth of more than 4 GHz also supports frequency division duplex (FDD) operations. The transceiver chip is fabricated using the Tower Jazz 0.18 µm SiGe BiCMOS process. With an on-board antenna, the transceiver covers all four channels in the 802.11ad standard, with MCS-12 (7.04 Gbps under 1.76 GSym/s and 16-QAM) under 1.5 m. In the proposed system design, the RF frontend-based self-interference (SI) suppression from the local transmitter to receiver LNA is around 54 dB. To achieve a practical FD application, the SI is further suppressed with the help of a digital SI compensation. The measured power consumption for the transmitter and receiver configurations are 194 mW and 231 mW, respectively, in HD mode and 398 mW for the FDD or FD operation mode.

A 1.25-GHz multi-amplitude modulator driver in 0.18 μm SiGe BiCOMOS technology for high speed quantum key distribution.

Quantum key distribution (QKD) research has yielded highly fruitful results and is currently undergoing an industrialization transformation. In QKD systems, electro-optic modulators are typically employed to prepare the required quantum states. While various QKD systems operating at GHz repetition frequency have demonstrated exceptional performance, they predominantly rely on instruments or printed circuit boards to fulfill the driving circuit function of the electro-optic modulator. Consequently, these systems tend to be complex with low integration levels. To address this challenge, we have introduced a modulator driver integrated circuit in 0.18 µm SiGe BiCMOS technology. The circuit can generate multiple-level driving signals with a clock frequency of 1.25GHz and a rising edge of ∼50ps. Each voltage amplitude can be independently adjusted, ensuring the precise preparation of quantum states. The measured signal-to-noise ratio was more than 17 dB, resulting in a low quantum bit error rate of 0.24% in our polarization-encoding system. This work will contribute to the advancement of QKD system integration and promote the industrialization process in this field.

Analysis and Implementation of Controlled Semiconductor Switch for Ultra-Wideband Radar Sensor Applications.

All ultra-wideband (UWB) sensor applications require hardware designed directly for their specific application. The switching of broadband radio frequency and microwave signals is an integral part of almost every piece of high-frequency equipment, whether in commercial operation or laboratory conditions. The trend of integrating various circuit structures and systems on a chip (SoC) or in a single package (SiP) is also related to the need to design these integrated switches for various measuring devices and instruments in laboratories, paradoxically for their further development. Another possible use is switching high-frequency signals in telecommunications devices, whether mobile or fixed networks, for example, for switching signals from several antennas. Based on these requirements, a high-frequency semiconductor integrated switch with NMOS transistors was designed. With these transistors, it is possible to achieve higher integration than with bipolar ones. Even though MOSFET transistors have worse frequency characteristics, we can compensate them to some extent with the precise design of the circuit and layout of the chip. This article describes the analysis and design of a high-frequency semiconductor integrated switch for UWB applications consisting of three series-parallel switches controlled by CMOS logic signals. They are primarily intended for UWB sensor systems, e.g., when switching and configuring the antenna MIMO system or when switching calibration tools. The design of the switch was implemented in low-cost 0.35 µm SiGe BiCMOS technology with an emphasis on the smallest possible attenuation and the largest possible bandwidth and isolation. The reason for choosing this technology was also that other circuit structures of UWB systems were realized in this technology. Through the simulations, individual parameters of the circuit were simulated, the layout of the chip was also created, and the parameters of the circuit were simulated with the parasitic extraction and the inclusion of parasitic elements (post-layout simulations). Subsequently, the chip was manufactured and its parameters were measured and evaluated. Based on these measurements, the designed and fabricated UWB switch was found to have the following parameters: a supply current of 2 mA at 3.3 V, a bandwidth of 6 GHz, an insertion loss (at 1 GHz) of -2.2 dB, and isolation (at 1 GHz) of -33 dB, which satisfy the requirements for our UWB sensor applications.

A 25-Gb/s dual-loop adaptive continuous-time linear equalizer based on power comparison for the optical transmitter

A new dual-loop adaptive continuous-time linear equalizer (CTLE) based on power comparison is proposed to realize a 25-Gb/s optical transmitter. The adaptive CTLE controls the high-frequency gain peaking of the loop regulation path to match the configuration of the boost factor for improved adaptive capacity and power comparison accuracy. A digital control method is used to operate two power comparison loops with different running cycles for increased power comparison accuracy and reduced power consumption of the adaptive control process. Measurements of an adaptive CTLE fabricated by the 0.18 μm SiGe BiCMOS process showed that it was able to compensate for the coaxial cables with an attenuation of at least −11.4 dB @12.5 GHz. The adaptive CTLE only consumed 22.8 mW from a 1.8-V power supply, resulting in energy efficiency at 0.91 pJ/b.

4 × 25 Gb/s PAM4 optical transmitter for micro‐ring modulator with thermal control

AbstractThe explosive growth of bandwidth demands of data center and super‐computing systems spur the appliance and development of optoelectronic‐based solutions such as micro‐ring modulator (MRM) transmitters, and advanced modulation schemes such as four‐level pulse‐amplitude modulation (PAM4). In this paper, a 4 × 25 Gb/s PAM4 MRM transmitter fabricated in 0.13 μm SiGe BiCMOS technology is presented. It consists of four‐channel MRM driver and thermal control loop. Capacitor and resistor degeneration techniques and inductor peaking techniques are adopted to expand channel bandwidth. Meanwhile, the predistortion technique is utilized to compensate for MRM nonlinearity, and auto gain control (AGC) circuits to enable the MRM driver to realize a fixed differential output swing of 3.5 Vpp. Furthermore, a thermal control method based on analog to digital converter, digital to analog converter, and logic control circuits is proposed to compensate for the temperature sensitivity of MRM. The measurement results show that the 25 Gb/s nonreturn‐to‐zero optical eye achieves an extinction ratio of 5.63 dB, and the PAM4 eye can be observed up to 40 Gb/s.

A laser source driver in 0.18 μm SiGe BiCMOS technology for high speed quantum key distribution

Quantum key distribution (QKD) has rapidly developed recently. The repetition frequency of the QKD system increases from tens or hundreds of MHz to GHz. A laser diode (LD) operating in gain-switched mode is widely used as a weak coherent light source in a QKD system. We present an LD driver circuit fabricated in 0.18 μm SiGe heterojunction bipolar transistor bipolar complementary metal oxide semiconductor technology. The circuit can operate at frequencies up to 2.5 GHz, satisfying the requirements of high-speed laser drives in practical QKD systems. The output current of the driver circuit can reach 100 mA when driving an LD whose input equivalent resistance is ∼21 Ω. The extinction ratio of the 1550-nm distributed feedback LD light source driven by our driver circuit reaches 23 dB at the operating frequency of 2.5 GHz, meeting the requirements of QKD systems. This circuit will be used in miniaturized QKD systems.

Transmitter and Receiver in 0.13 μm SiGe for Gas Spectroscopy at 222–270/444–540 GHz

This paper presents a transmitter (TX) and a receiver (RX) with a cross-polarized bowtie-antenna on a silicon lens for gas spectroscopy at 222–270 GHz and the doubled frequency at 444–540 GHz. TX and RX are fabricated in 0.13 μm SiGe BiCMOS technology. Both use two integrated local oscillators for frequency subbands 222–256 GHz and 250–270 GHz, which allow operating in one branch of the TX and RX at 222–270 GHz and in a second branch of the TX and RX at 444–540 GHz by frequency doubling. The directivity of the cross-polarized bowtie-antenna of the TX and RX is optimized for these two frequency bands with an estimated value of 24.4 dBi at 260 GHz, and 29.5 dBi at 520 GHz. Absorption spectroscopy of gaseous methanol is used as a measure for the performance of the TX and RX in the lower and upper frequency bands.

A D‐band quadrature‐hybrids‐based 5‐bit vector‐modulated phase shifter with low RMS phase error

This letter presents a D-band 5-bit vector-modulated phase shifter based on quadrature hybrids for D-band phased arrays. The proposed vector-modulated phase shifter employs two stages of quadrature hybrid followed with a single-pole double-throw switch for I/Q phase splitting and vector-summing. To improve the isolation performance, traveling-wave single-pole double-throw switches together with transistor parallel inductors are adopted. A marchand balun followed with two variable gain amplifiers is placed between the two quadrature hybrids for I/Q amplitude weighting. A proof-of-concept vector-modulated phase shifter is designed and fabricated in 0.13 μm SiGe BiCMOS technology and occupies a core chip area of 0.45 mm2. Measurement results show that the RMS phase error is 1.6° at 149 GHz and the RMS gain error is below 2.8 dB over 146–156 GHz. The DC power consumption is 148 mW.

A Low Phase Noise Dual-Loop Dual-Output Frequency Synthesizer in SiGe BiCMOS

In this article, a dual-loop dual-output frequency synthesizer designed for IEEE802.11aj (45 GHz) standard is presented. In order to support the super-heterodyne transceiver, the Loop1 output frequency is fixed for easy design of high-performance IF transceiver and filter, and the Loop2 output frequency varies for the channel selection according to the IEEE802.11aj (45 GHz) standard. The power hungry high-speed prescaler (or multi-modulus-divider) is replaced with a mixer in Loop2, thus the in-band phase noise and DC power consumption can be improved. The dual-loop dual-output synthesizer is fabricated in 0.13 µm SiGe BiCMOS technology, occupies an area of 2.7 mm × 2.4 mm, and consumes 610 mW DC power. Measured results show the phase noise of the frequency synthesizer are −79.3 dBc/Hz@10 kHz and −129.1 dBc/Hz@10 MHz at 12.96 GHz for Output1 and −76.6 dBc/Hz@10 kHz and −117.2 dBc/Hz@10 MHz at 32.535 GHz for Output2. The low-reference spur of −69.2 dBc and low-power level spurious tones at the outputs are observed during the measurement. To the best of our knowledge, this work is the first reported dual-loop dual-output synthesizer designed for IEEE802.11aj (45 GHz) standard.

Numerical study of nSi and nSiGe solar cells: Emerging microstructure nSiGe cell achieved the highest 8.55% efficiency

This paper reports about the comparative study of nSi and nSiGe microstructure materials opto-electrical energy conversion prospect. The significance of nSiGe thin active laye in organic-inorganic heterojunction (HJ) solar cell efficiency progression is illustrated. Transparent and carrier selective top contact purposes p-type un-doped organic materials are promising for low processing cost n-Si HJ solar cell. Near infrared band absorption enrichment by Ge inclusion in n-Si thin active layer is a new design approach. p-PTAA/n-Si PV device modelling and it electrical properties are investigated by using SCAPS simulator. Thin Si active layer solar cell is commercially important. However, thin layer absorption related technological shortcoming overcoming approaches 10% Ge content impact is studied in this work. Moreover, SiO2 nanomaterial passivated p-PTAA/SiO2/n-SiGe and p-PTAA/SiO2/n-Si models active layer thickness and operating temperature effects have also been studied. The current-voltage (J-V) characteristics analysis is realized that nSiGe cell is potential for the progression of current density and efficiency. SiO2 nanomaterial passivated 3 μm SiGe microstructure cell is realized promising to increase 48.1 mA/cm2 of current density. The highest 8.55% efficiency is achieved for 2 nm SiO2 passivation and 20 nm of PTAA emitter.

The Analysis of the Polysilicon base Position of the Thermal Resistance and the Self Heating Effects of 0.13 µm SiGe Heterojunction Bipolar Transistors

The Analysis of the Polysilicon base Position of the Thermal Resistance and the Self Heating Effects of 0.13 µm SiGe Heterojunction Bipolar Transistors

A Closed-Loop Reconfigurable Analog Baseband Circuitry With Open-Loop Tunable Notch Filters to Improve Receiver Tx Leakage and Close-in Blocker Tolerance

This paper presents an analog baseband (ABB) circuit in a 0.13 μm SiGe technology for transmitter leakage cancellation and close-in blocker suppressions in fully duplex (FD) frequency-modulated continuous-wave (FMCW) radar. This ABB comprises a programmable gain amplifier (PGA) and a cascaded LPF/Notch hybrid, which incorporates a closed-loop (CL) reconfigurable low-pass filter (LPF) and an open-loop (OL) tunable notch filter. The adopted key topologies include active-RC bi-quads and Gm-C ones. In an FD FMCW transceiver, Tx leakage and close-in blockers are difficult to be eliminated in the RF domain, especially when leakage/blockers are very close to desired signals or even in-band in the frequency domain. This LPF/notch hybrid is proposed to solve this issue. The LPF and PGA provide bandwidth (BW)/gain programmability, while the Gm-C bi-quad provides adaptable center frequency for a notch filter. With this adaption, the notch filter could be adjusted to match the leakage/blocker offset frequency. Thus, digitally discrete programmability and analog continuous tuning capability are combined in this solution for improving the overall front-end interference robustness without de-sensitizing the Rx. Furthermore, the order of LPF/notch hybrid is programmable from 2 to 10 with a step of 2 for different rejection levels of interferences. The measured chip achieves a -3dB bandwidth of 6 21 MHz with 4-bit digital control and 1 MHz/step programmability, and a voltage gain of 0 70 dB with 9-bit digital control (3-bit from pre-amplifier, and 6-bit from PGA with 1 dB/step). With the condition of 15 dB gain, output P-1dB is 11.8 dBm@3MHz, and the output IP3 is 20.8 dBm@3MHz.

Reliable metal-graphene contact formation process flows in a CMOS-compatible environment.

The possibility of exploiting the enormous potential of graphene for microelectronics and photonics must go through the optimization of the graphene-metal contact. Achieving low contact resistance is essential for the consideration of graphene as a candidate material for electronic and photonic devices. This work has been carried out in an 8'' wafer pilot-line for the integration of graphene into a CMOS environment. The main focus is to study the impact of the patterning of graphene and passivation on metal-graphene contact resistance. The latter is measured by means of transmission line measurement (TLM) with several contact designs. The presented approaches enable reproducible formation of contact resistivity as low as 660 Ω μm with a sheet resistance of 1.8 kΩ/□ by proper graphene patterning, passivation of the channel and a post-processing treatment such as annealing.

A BiCMOS frontend electronics chipset for the readout of the INO-ICAL RPC detector

This paper presents a BiCMOS voltage amplifier-based high-speed frontend electronics (FEE) chipset, designed in 0.35μm SiGe BiCMOS technology. This chipset comprises two ASICs, namely a quad voltage amplifier ASIC and an octal comparator ASIC. The two-chip FEE is designed for the readout of large area, single-gap, avalanche mode Resistive Plate Chamber (RPC) detectors of the Iron Calorimeter (ICAL) experiment of the India based Neutrino Observatory (INO). The use of a voltage amplifier-based FEE topology along with a separate comparator ASIC resulted in a stable high gain and high-speed FEE operation in the presence of a large number of detector channels. This FEE solution has a total amplifier gain of 74, overall timing precision of 140 ps (RMS), and power consumption of 25 mW/channel. It exhibits pixel-wise detector efficiency larger than 90% along with position- and time-resolution of 1 cm RMS, and 1 ns RMS, respectively, when used with a prototype INO-ICAL RPC detector of size 1.85 m × 1.75 m. Furthermore, the performance of the FEE is not affected by the presence of the magnetic field (1.3 T) used in the experiment.

A 6–18 GHz high dB‐linear attenuator based on variable gain amplifier for ultra‐wideband phased array systems

AbstractThe letter presents a high dB‐linear attenuator based on variable gain amplifier (VGA) for ultra‐wideband phased array systems. An effective dB‐linear compensation structure is proposed to improve the gain range and accuracy. The bandwidth and gain flatness of the proposed VGA are increased by the emitter resistor–capacitor negative feedback and transistor segmentation technique. The proposed VGA is implemented with the 0.18 μm SiGe bipolar complementary metal oxide semiconductor (BiCMOS) process. The measured results show that the VGA can operate from 6 to 18 GHz with a controlled variable gain range of 20 dB, the root‐mean‐square gain error is less than 0.55 dB. The input 1 dB compression point (IP1dB) of the fabricated VGA is more than −5 dBm. The proposed VGA consumes 71 mW and occupies a chip area of 0.98 mm × 0.98 mm.

Radiation response of SiGe low noise amplifier irradiated with different energy protons

This research, for the first time, uses different energy protons of 5 MeV and 10 MeV to irradiate low noise amplifiers (LNAs) with a frequency band ranging from 1.4GHz to 1.8 GHz designed with 0.25 μm SiGe BiCMOS technology. It studies the resulting radiation effects and also compares the RF responses of the LNAs under different energy proton irradiations. The irradiation fluences of the two different protons are up to 1 × 1015 protons/cm2. The response characteristics of input reflection coefficient S11, transmission gain S21 and noise figure (NF) of the device RF performance before and after the 5 MeV and 10 MeV proton irradiations are compared and discussed. The results show that the input reflection coefficient decreases after the proton irradiations, and at 5 MeV, the transmission gain decreases by 1.8 dB at most, and the NF increases by 1.5 dB at most. Moreover, the degradation of LNA characteristic parameters under 5 MeV proton irradiation is much more than under 10 MeV proton irradiation, with the irradiation dose of 1 × 1015 protons/cm2.