Μm Process Research Articles

A unified black‐box macro model for analog circuit based on artificial neural network

SummaryA novel unified black‐box macro model for analog circuits is presented. This black‐box macro model enables the creation of a high‐accuracy DC and AC macro model by modeling the port voltages and currents of analog circuits using an artificial neural network (ANN). The modeling process for different analog circuit blocks is the same, as the model can be modeled by extracting only the port values. The operational amplifier (OPAMP), which is an important module of the analog circuit, is taken as an example for the verification of the model proposed in this work. The black‐box macro model of OPAMP is used for DC, AC, and transient simulations. The simulation speed of the black‐box macro model is much better than that of the transistor‐level model, and the trade‐off between accuracy and speed can be freely adjusted. The black‐box macro model of OPAMP is also validated by bandgap and low dropout regulators (LDO). To verify the accuracy of the model, the experimental measurement results of the LDO circuit fabricated in the 0.18 μm process have been obtained. Compared with the measurement results, the simulation results of both transistor and black‐box macro models have high accuracy. Those results demonstrate the great potential of the black‐box macro model in analog circuit design and simulation.

A Wirelessly Powered System of Coherent Sensing Nodes for Fracture Mapping Applications at Temperatures up to 250 °C and Pressures up to 24 MPa

Fracture mapping is essential in hydraulic fracturing and finds applications in the oil and gas industry. Mapping of fractures using traditional radioactive or microseismic methods involves contamination and is prone to being inaccurate, thereby reducing the yield in fracturing applications. Therefore, wireless sensor networks (WSNs) with each sensing node having a small form factor and low power consumption are currently being investigated for use in such applications. This paper presents a fully battery-less system of coherent sensing nodes using wireless energy harvesting. These nodes are capable of mapping fractures reliably at temperatures up to 250 °C and pressures up to 24 MPa. Each node comprises a microchip having dimensions of 1.1 mm X 0.56 mm, two coils of 8 mm diameter each, and resonating capacitors. The microchip was fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm process. The node receives a 40.68 MHz radio frequency (RF) signal in the industrial, scientific, and medical applications (ISM) band and transmits back a locked sub-harmonic 13.56 MHz ISM band RF signal. The sub-harmonic signal is generated on-chip using a digital divide-by-3 circuit, drastically reducing the microchip power consumption compared to injection-locked oscillators or phase-locked loops (PLLs). The sensor nodes used in the system have a form factor of 17 mm X 12 mm X 0.2 mm and a minimum average power consumption of 1.5 μW.

Integrated Filter Design for Analog Field Mill Sensor Interface

The design process of an integrated bandpass filter targeted for the noise filtering stage of the synchronous demodulation unit of an electric field mill sensor interface is presented. The purpose of this study of filter integration techniques is to avoid the challenging and, in some cases, impossible passive element integration process and to incorporate the final filter design in an entirely integrated field mill sensing system with superior performance and an optimized silicon-to-cost ratio. Four different CMOS filter implementations in the 0.18 μm process of XFAB, using OTA (Operational Transconductance Amplifier)-based configurations for passive element replacement in cascaded filter topologies and leapfrog techniques, are compared in terms of noise performance, total harmonic distortion, dynamic range, and power consumption, as well as in terms of integrability, silicon area, and performance degradation at process corners/mismatches. The optimum filter design performance-wise and process-wise is included in the final design of the integrated analog readout of a field mill sensor, and post-layout simulation results of the total circuit are presented.

High voltage low quiescent current LDO with self-regulation impedance buffer

Abstract To improve the whole characteristic of the LDO, a low quiescent current structure of high voltage LDO with self-regulation impedance buffer and bandgap amplifier is presented in this paper. With the bandgap amplifier proposed, the function of voltage reference and error amplifier can be achieved simultaneously, which can efficiently reduce the consumption. The load capacitor can be as small as 0.47µF by using the self-regulation impedance buffer and current buffer compensation scheme. The LDO has been implemented in a 0.18 µm process with die size 0.03 mm2 . Without the load, the consumption quiescent current of the LDO is 1 µA. Experimental result shows that the overshoot and undershoot of line transient response are less than 30 mV/V. The load regulation is about 0.1A, and line regulation is about 0.07 mV/V at no load condition.

Fully Integrated 1.8 V Output 300 mA Load LDO with Fast Transient Response

Based on an 0.18 μm process, this paper proposes a fully integrated 1.8 V output 300 mA load low-dropout linear regulator (LDO) with a fast transient response. By inserting a transient-enhanced biased Class AB super source follower at the gate of the output power transistor, this LDO can quickly adjust the gate voltage of the power transistor without additional power consumption. By adding an active capacitor circuit composed of a fast comparator with offset voltage at the output point, this LDO can quickly charge/discharge the transient current and accelerate the transient response without reducing the circuit stability. Simulation results show that the proposed LDO has an output voltage of 1.8 V, when the input voltage is 2 V to 5 V while consuming 66.4 μA of quiescent current. The proposed capless LDO has a 1.94 µV/mA load regulation, a 0.55 mV/V linear regulation, and a −60 dB@1 kHz power supply rejection. When the load current steps from 3 mA to 300 mA in 300 ns, the LDO settles in 400 ns with an overshoot and undershoot of 67 mV and 86 mV, respectively.

Novel FDNR, FDNC and lossy inductor simulators employing second generation voltage conveyor (VCII)

AbstractIn this research the second‐generation voltage conveyor (VCII) is employed in the design of grounded frequency dependent negative resistor (FDNR) and Frequency dependent negative conductance (FDNC). Additionally, two lossy parallel and series R‐L inductor simulators are also designed. To the best knowledge of the authors above mentioned immittance simulators are first time implemented using VCII. The FDNR requires two VCII, two capacitors and one grounded resistor. FDNC is implemented using three VCII, three resistors and two grounded capacitors. The R‐L inductor emulators requires two VCII, two resistors and one grounded capacitor. All the presented immittance simulators do not require any kind of passive component matching. The non‐ideal gain and sensitivity analysis is conducted to study their performance under circuit parameter variations. Parasitic analysis is also done for the FDNR, FDNC and R‐L inductance simulators to study the effect of parasitic impedance on the circuit operation. To validate the designs, they are simulated in Cadence design environment using 0.18 μm process design kit (PDK) at ±0.9 V supply. Additionally, the circuits are also validated using the macro model of commercially available integrated circuit (IC) AD844. The theoretical and simulation results are found to be in close agreement.

Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis

This work presents the comparison between Nanowire Tunnel Field-Effect Transistor (NW-TFET) and Line-TFET applied on the design of Low-Dropout Voltage Regulator (LDO). Both devices have a SiGe source composition in order to enhance the current drive. The transistors were modeled using lookup tables (LUTs) approach based on experimental data using Verilog-A language. The LDOs were designed for two conditions, considering different gm/ID, load currents and load capacitances. In order to compare the TFET LDOs with an established technology, a MOSFET LDO was designed with TSMC 0.18 µm process design kit. Both TFET LDOs reach stability without the presence of a compensation capacitor. For gm/ID = 10.5 V−1 the current consumption of NW-TFET LDO (1.5nA) is near two orders of magnitude lower than Line-TFET LDO (68nA) and three orders of magnitude lower than MOSFET LDO (9 µA). The Line-TFET LDO exhibits better results in almost all parameters despite of the gain-bandwidth product (GBW) that is in the same order of magnitude of the MOSFET LDO, 171 kHz compared to 250 kHz for gm/ID = 10.5 V−1. The comparison between TFET LDOs for gm/ID = 7 V−1 was also performed regarding the transient and process variability analysis. The transient response revealed that the Line-TFET LDO has a pronounced lower settling time, 71 µs compared to 5 ms for a load step, but with a damped oscillatory response, the NW-TFET LDO presented lower undershoot for the load step. The process variability analysis was performed for devices within the wafer and was observed that the Line-TFET LDO suffers a higher impact with a 20 dB variation on the loop gain in comparison to 10 dB in the NW-TFET LDO.

Low-Power and High-Precision Readout Circuit Design for Micro-Electromechanical Systems (MEMS) Acceleration Sensors

MEMS acceleration sensors are widely used in Internet of Things, electronic machinery, aerospace and other fields with outstanding advantages such as small size, high reliability, intelligence and high integration. Traditional MEMS acceleration sensors limit their applications due to high-power consumption and low-precision; the standby time and service life are being increased in order to study the low-power and high-precision MEMS acceleration sensor readout, this paper adopts the Fully Differential Switched Capacitor-Variable Gain Amplifier (FDSC-VGA) instead of the traditional high-power Capacitance-to-Voltage Converter (CVC-VGA), Sample-and-Hold Circuit (S&H) and Anti-Aliasing Filter (AAF) as front-end modules. At the same time, a high-precision four-phase non-crossover clock is designed to precisely control the timing switch, thus effectively reducing the power consumption of the MEMS acceleration sensor readout circuit; then, the overall readout circuit is simulated and verified by Dong Bu HiTek 0.18 μm process. The results show that the error rate of the output voltage of FDSC-VGA is reduced from 8.03% to 0.88% compared with the conventional readout circuit, and the noise power consumption of MEMS acceleration sensor readout circuit can be reduced by 65%.

A complementary high linearity bootstrap switch based on negative voltage bootstrap capacitor

The sample-and-hold (S/H) circuit is an important part of the analog-to-digital converter (ADC). A bootstrap switch with capacitive load can form a basic S/H circuit. A complementary high linearity gate voltage bootstrap switch based on bootstrap capacitor is proposed in this paper. By reducing the size of the key node transistors, the parasitic capacitance is reduced. The sampling metal-oxide-semiconductor field-effect transistor (MOSFET) in this structure is composed of complementary NMOS and PMOS, which reduces the channel charge injection effect and variations in on-resistance (Ron). The simulation results show that the effective number of bits (ENOB), signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the structure are 16.5 bits, 101.11 dB and 101.83 dB respectively at the sampling frequency of 50 MHz and full swing voltage input of 1.8 V based on SMIC 0.18 μm process. Compared with the conventional NMOS switch, ENOB, SDNR, and SFDR are increased by 2.45 bits, 14.73 dB, and 13.38 dB, respectively. In addition, Monte Carlo (MC) and corner simulations of the proposed circuit are performed, and the results show that the proposed circuit has good performance.

Integrated Low-Voltage Compliance and Wide-Dynamic Stimulator Design for Neural Implantable Devices

In this study, a pulse frequency modulation (PFM)-based stimulator is proposed for use in biomedical implantable devices. Conventionally, functional electrical stimulation (FES) techniques have been used to reinforce damaged nerves, such as retina tissue and brain tissue, by injecting a certain amount of charge into tissues. Although several design methods are present for implementing FES devices, an FES stimulator for retinal implants is difficult to realize because of the chip area, which needs to be inserted in a fovea, sized 5 mm x 5 mm, and power limitations to prevent the heat generation that causes tissue damage. In this work, we propose a novel stimulation structure to reduce the compliance voltage during stimulation, which can result in high-speed and low-voltage operation. A new stimulator that is composed of a modified high-speed PFM, a 4-bit counter, a serializer, a digital controller, and a current driver is designed and verified using a DB HiTek standard 0.18 μm process. This proposed stimulator can generate a charge up to 130 nC, consumes an average power of 375 µW during a stimulation period, and occupies a total area of 700 µm × 68 µm.

Design and Experiment of a Hybrid-Integrated Ultrahigh-g Accelerometer With Variable-Section Beam

Due to the special fields of aerospace, explosion impact, weapon penetration and other high g value acceleration test, the sensor test range and anti-overload capability have great requirements. At present, most accelerometer beams with equal section are used. The existing data prove that the beam structure with variable section can effectively solve the problem of stress concentration, improve the anti-overload capability of acceleration sensor, and increase the system stability through theoretical simulation. This study presents a hybrid-integrated high-precision MEMS ultra-high-g piezoresistive accelerometer, which is composed of a sensitive structure and an ASIC interface (application specific integrated circuit). Based on the traditional constant-section four-beam accelerometer, a variable-section beam is proposed, and the section size increases linearly with the length of beam. Through finite element simulation analysis, it is verified that the variable section beam has the characteristics of reducing stress concentration and can improve the anti-overload ability of the accelerometer. The simulation results show that the maximum stress of the structure under 200,000 g is 28.34 MPa, and its resonance frequency is 548 kHz. Finally, the processing flow is designed, and the fabrication of MEMS chip is completed. Based on the TSMC 0.35 μm process, the ASIC interface is designed and fabricated to process the signal from the sensing element and realize the functions of amplification and filtering. The MEMS chip and ASIC chip are integrated by gold wire bonding, packaged in a stainless-steel shell, and tested by Hopkinson bar. The test results show that the sensitivity of the accelerometer is 0.2747 μV/g, the non-linearity is 2.79%, and the full range is 200,000 g, and the anti-overload capacity is 250,000 g.

2D Winograd CNN Chip for COVID-19 and Pneumonia Detection

In this paper, a two-dimensional Winograd CNN (Convolutional Neural Network) chip for COVID-19 and pneumonia detection is proposed. In light of the COVID-19 pandemic, many studies have led to a dramatic increase in the effects of the virus on the lungs. Some studies have also pointed out that the clinical application of deep learning in the medical field is also increasing, and it is also pointed out that the radiation impact of CT exposure is more serious than that of X-ray films and that CT exposure is not suitable for viral pneumonia. This study will analyze the results of X-rays trained using CNN architecture and convolutional using Winograd. This research will also set up a popular model architecture to realize four kinds of grayscale image prediction to verify the actual prediction effect on this data. The experimental data is mainly composed of chest X-rays of four different types of grayscales as input material. Among them, the research method of this experiment is to design the basic CNN operation structure of the chip and apply the Winograd calculus method to the convolutional operation. Finally, according to the TSMC 0.18 μm process, the actual chip is produced, and each step is verified to ensure the correctness of the circuit. The experimental results prove that the accuracy of our proposed method reaches 87.87%, and the precision reaches 88.48%. This proves that our proposed method has an excellent recognition rate.

A high performance RC-INV triggering SCR under 0.25 µm process

PurposeAs it is known, the electrostatic discharge (ESD) protection design of integrated circuit is very important, among which the silicon controlled rectifier (SCR) is one of the most commonly used ESD protection devices. However, the traditional SCR has the disadvantages of too high trigger voltage, too low holding voltage after the snapback and longer turn-on time. The purpose of this paper is to design a high-performance SCR in accordance with the design window under 0.25 µm process, and provide a new scheme for SCR design to reduce the trigger voltage, improve the holding voltage and reduce the turn-on time.Design/methodology/approachBased on the traditional SCR, an RC-INV trigger circuit is introduced. Through theoretical analysis, TCAD simulation and tape-out verification, it is shown that RC-INV triggering SCR can reduce the trigger voltage, increase the holding voltage and reduce the turn-on time of the device on the premise of maintaining good robustness.FindingsThe RC-INV triggering SCR has great performance, and the test shows that the transmission line pulse curve with almost no snapback can be obtained. Compared with the traditional SCR, the trigger voltage decreased from 32.39 to 16.24 V, the holding voltage increased from 3.12 to 14.18 V and the turn-on time decreased from 29.6 to 16.6 ns, decreasing by 43.9% the level of human body model reached 18 kV+.Originality/valueUnder 0.25 µm BCD process, this study propose a high-performance RC-INV triggering SCR ESD protection device. The work presented in this paper has a certain guiding significance for the design of SCR ESD protection devices.

Metamutator based universal, single input multi output current mode filter

AbstractThe introduction of Add ‐ Differentiate IC, AD‐IC, a new integrated circuit, into schemes for realizing single input multiple output current mode filters is the motivation behind this paper. In the circuit structure of this filter with only one active device with a minimal number of transistors and five passive components are being used. Non ideal effects of the design are investigated and simulation results of the application, using TSMC 0.25 μm process parameters with ±1.25 V power supply voltage and the bias as 0.8 V resulting in 0.99 mW power dissipation for the entire filter, are also presented to confirm the theoretical analysis. With this new design technique, the tunabilities of the angular frequency ( ) and quality factor ( ) can be performed independently.

A Novel Architecture of Asynchronous Sorting Engine Module for ASIC Design

A novel sorting engine called Sorting Grid (SG) is presented in this paper. SG is intended to be used as a hardware module for ASIC design which can be employed for any ASIC chip requiring fast sorting operation. The SG is implemented by simple modular architecture so that it is easily synthesized with conventional ASIC tools. SG allows inputs with the same key and provides stable sorting for those inputs. SG sorts m-bit N binary inputs in (m+1) cycles with variable cycle time. SG employs a self-timed asynchronous clock of which the period changes according to the operation time of each cycle. The clock period greatly decreases along the cycle. With this clock and a multi-level bypassing scheme, SG has O(N+m) time-complexity for pseudo-random binary inputs. By the simulations with 1.2V-0.13 μm process technology, the sorting rate of the SG is about 1 ns per input for 16-bit inputs.

Motion-Based Object Location on a Smart Image Sensor Using On-Pixel Memory.

Object location is a crucial computer vision method often used as a previous stage to object classification. Object-location algorithms require high computational and memory resources, which poses a difficult challenge for portable and low-power devices, even when the algorithm is implemented using dedicated digital hardware. Moving part of the computation to the imager may reduce the memory requirements of the digital post-processor and exploit the parallelism available in the algorithm. This paper presents the architecture of a Smart Imaging Sensor (SIS) that performs object location using pixel-level parallelism. The SIS is based on a custom smart pixel, capable of computing frame differences in the analog domain, and a digital coprocessor that performs morphological operations and connected components to determine the bounding boxes of the detected objects. The smart-pixel array implements on-pixel temporal difference computation using analog memories to detect motion between consecutive frames. Our SIS can operate in two modes: (1) as a conventional image sensor and (2) as a smart sensor which delivers a binary image that highlights the pixels in which movement is detected between consecutive frames and the object bounding boxes. In this paper, we present the design of the smart pixel and evaluate its performance using post-parasitic extraction on a 0.35 µm mixed-signal CMOS process. With a pixel-pitch of 32 µm × 32 µm, we achieved a fill factor of 28%. To evaluate the scalability of the design, we ported the layout to a 0.18 µm process, achieving a fill factor of 74%. On an array of smart pixels, the circuit operates at a maximum frame rate of 3846 frames per second. The digital coprocessor was implemented and validated on a Xilinx Artix-7 XC7A35T field-programmable gate array that runs at 125 MHz, locates objects in a video frame in 0.614 µs, and has a power consumption of 58 mW.

(Digital Presentation) Performance Improvement of Nickel-Rich Layered Cathodes for Li Batteries Based on Modified Solid State Reaction

Lithiated metal oxides with layered structure used as the cathode may provide a high capacity and stable cycle retention, which is a desired property for lithium-ion batteries. Among them, NMC composed of Ni, Mn and Co as transition metal ions is considered a promising positive electrode. Due to high cost and toxicity of Co, Ni-rich layered oxide with substitution of Ni for Co content shows high capacity and adequate cycling performance. Recently, the fabrication of NMC adopting single-crystal (grain size: 1~6 μm) process tends to give better long-term performance than ones with particles in nanometer range.In this study, LiNi0.8Mn0.1Co0.1O2 (NMC811) with substitution of Ni/Mn for Co were selected as the Ni-rich layered cathode investigated. Due to the low melting point of Li2CO3, the heating temperature/time of powder mixture become crucial to control the adequate grain size of to achieve better retention. The value of the I(003) /I(104) ratio in XRD pattern represent cation mixing in layered structure. And this parameter is closely related to its electrochemical properties. Discussion will be carried out based on the results of XRD analysis and the charge–discharge profiles and cycling performance.

Modeling of CMOS transistors from 0.18 μm process by artificial neural network

In this work, we developed a new transistor model that can be used to simulate analog circuits. Our model uses artificial neural network to capture the electrical characteristics of transistors instead of the traditional physics-driven model. By preprocessing the transistor data, high-precision modeling is achieved. N-type and p-type transistors with various widths and lengths are fabricated with the 0.18 μm analog process in the foundry. ANN modeling on these transistors shows high precision compared with the BSIM3 transistor model. The results show that the DC characteristics of the ANN model are more accurate than the BSIM3 transistor model, and have better capture on the output-resistance of the MOSFET.

A Low-Computing-Complexity Touch Signal Detection Method and Analog Front-End Circuits Based on Cross-Correlation Technology for Large-Size Touch Panel.

This paper proposes a low-computing-complexity touch signal detection method and analog front-end (AFE) circuits based on cross-correlation technology for large mutual capacitance touch screen panels (TSPs). To solve the traditional touch signal detection method problem of lots of invalid data being sampled and processed in a large-size TSP, the proposed method only samples and processes the signals around the touch points rather than full-screen data to decrease the computing complexity and analog–digital convertor (ADC) acquisition number. Compared with the traditional method, the proposed touch points search algorithm complexity decreases from MN to M + nN where M, N, and n are the number of RX channels, TX channels, and touch points, respectively. The maximum ADC acquisition number of the proposed method decreases from MN to 18n. Based on the proposed touch signal detection method, the AFE circuits are designed by a 0.11 μm process. The proposed dual cross-correlation AFE achieves detection of the weak touch signal submerged in the large display panel noise. The average channel area and power consumption are decreased to 0.015 mm2 and 0.227 mW, respectively. The maximum frame rate is 384.6 Hz with 10 touch points. The proposed cross-correlation AFE achieves a high frame rate while reducing the die area and power consumption.

Design of a multi‐mode digital pixel with conversion data protection

With the development of semiconductor technology, digital pixel has received widespread attention and is applied to various electronic products. However, due to the limitation of area, it forms a challenging task to design a digital pixel with multiple modes. In this paper, a pulse width modulation based digital pixel is proposed, which is compatible with five different modes. By using the multi-purpose capacitors and static random access memory structure, it can realise multi-mode conversion in an equivalent area to that of the single mode digital pixel without performance degradation. Furthermore, a corresponding logic control method is developed, such that the integrity of the frame data is ensured during mode conversion. The simulation result of our proposed digital pixel in Tower Jazz 0.18 μm process shows that in the bright field it achieves a dynamic range of 67 dB. In the dark field, it achieves a conversion gain up to 13.91 μV/e−, with input noise of 37.89 e−per pixel after correlated double sampling.