A Novel Architecture of Asynchronous Sorting Engine Module for ASIC Design

Abstract

A novel sorting engine called Sorting Grid (SG) is presented in this paper. SG is intended to be used as a hardware module for ASIC design which can be employed for any ASIC chip requiring fast sorting operation. The SG is implemented by simple modular architecture so that it is easily synthesized with conventional ASIC tools. SG allows inputs with the same key and provides stable sorting for those inputs. SG sorts m-bit N binary inputs in (m+1) cycles with variable cycle time. SG employs a self-timed asynchronous clock of which the period changes according to the operation time of each cycle. The clock period greatly decreases along the cycle. With this clock and a multi-level bypassing scheme, SG has O(N+m) time-complexity for pseudo-random binary inputs. By the simulations with 1.2V-0.13 μm process technology, the sorting rate of the SG is about 1 ns per input for 16-bit inputs.