The performance of positive and negative tone resists on the critical levels of a 0.35 μm CMOS process has been evaluated. The use of a darkfield reticle suppresses reflections in lens and resist. Therefore reflection problems are reduced for poly gate patterning with a negative tone resist. If a positive resist is used it should be combined with a bottom ARC. For the contact hole level a positive tone resist is required. Good performance, including batch uniformity is obtained for 0.5 μm holes. For 0.4 μm contact holes, latitudes needed to be improved and this has been realised by either the combination of mask biasing and focus drilling or the use of an attenuated phase shifting reticle. For metal patterning, again positive and negative resists have been studied. An important issue here is the interaction between the acid formed upon exposure and the underlying TiN layer.