Μm Bulk CMOS Research Articles

Exploiting Parasitic Capacitances in 3-D Inductors to Design RF CMOS Quasi-Elliptic-Type Broad-Band Bandpass Filters

A class of RF broad-band bandpass filter (BPF) with quasi-elliptic-type response in low-cost bulk CMOS technology is reported. It is based on the in-series cascade connection of lowpass and highpass filtering stages with 3-D inductors, whose parasitic capacitances are properly exploited. Specifically, they are used to transform the basic inductor into an LC tank, thus allowing to generate an upper transmission zero (TZ) that increases filtering selectivity and out-of-band power-rejection levels in a spurious-free/extended upper stopband. The layout of a basic third-order BPF cell shaped by four 3-D inductors and its lossless equivalent lumped-element circuit are detailed. By means of this lossless equivalent lumped-element model, its scalability to higher-order BPF designs by in-series cascading various BPF-cell replicas is also demonstrated. For experimental-validation purposes, an on-chip RF CMOS BPF prototype with 11-GHz center frequency and 68.5% 3-dB fractional bandwidth is developed using a 0.13- μm bulk CMOS technology. According to the measured results, it shows an upper stopband with minimum attenuation of 31.7 dB from 22.5 GHz to 67 GHz, alongside with TZs at 3.5 GHz and 22.5 GHz to produce sharp-rejection filtering.

Design of a Wideband CMOS Balun and Its Application in a Wideband RF Front-End

This paper presents a 1:2 wideband CMOS balun, and its application for sub-6 GHz wideband front-end. In order to eliminate the amplitude/phase mismatch, the primary and secondary windings are shorted by a transmission line (T-line) for a common ground. The float metal in the primary winding is used for artificial dielectric compensation which further reduce the amplitude imbalance by up to about 0.5 dB. A 2.0-to-3.7 GHz wideband RF front-end is also designed by using the proposed CMOS balun. The balun and RF front-end are fabricated in a 0.13- μm bulk CMOS technology. The bandwidth of the balun with |S11| <; -10 dB is 2.2-to-5.1 GHz. The fractional bandwidth is large than 79.5%. The corresponding maximum amplitude and phase mismatch is 1.5 dB and 2°, respectively. The measured insertion loss is 4.8-to-5.6 dB from 2.2 to 5.1 GHz.

Interview

Guoping Guo Professor Guoping Guo from the Key Laboratory of Quantum Information at the University of Science and Technology of China, talks to Electronics Letters about the paper ‘Modelling and Kink Correction of 0.18 µm Bulk CMOS at Liquid Helium Temperature‘, page 780. I am currently studying solid state quantum computing fields and extreme environment electronics with the University of Science and Technology of China (USTC) alongside my research on quantum transport and its applications. This includes the design and manufacturing process of nanostructure devices. Meanwhile, my group focuses on measurement and control systems for quantum chips, specifically the semiconductor gate quantum dot, using GaAs, Si, graphene, and other 2-D materials. The work in our submitted Electronics Letters paper focuses on cryogenic electronics, including electron devices and circuits which operate at cryogenic temperatures. This temperature range extends from −150°C (123.15 Kelvin) down to absolute zero (0 K or −273.15°C). Cryogenic electronics have good prospects in applications such as space exploration, infrared focal plane array, quantum computing and many fields where electronics face extreme low temperature environments. A quantum computer comprises a quantum processor and a classical electronic control system. The quantum processor works in a dilution refrigerator at deep cryogenic temperatures down to the millikelvin range, while traditional electronic readout and control systems are implemented using room-temperature (RT) laboratory instruments. The cryogenic complementary metal oxide semiconductor (Cryo-CMOS) technology can greatly reduce noises generated by classical electronics and thermal environment, thus enhancing the fidelity and precision of quantum information processing. The first problem to solve when designing Cryo-CMOS circuits is transistor modelling. In answer to this we present the first compact model for 0.18 µm CMOS technology based on BSIM3 down to liquid Helium temperatures (4.2µK). We also present a sub-circuit model to improve the fitting precision at 4.2 K. This work provides experimental evidence for the implementation of cryogenic CMOS technology, a valid model of industrial tape-out process, and promotes the application of integrated circuits in cryogenic environments, for applications such as quantum measurement and for control systems for semiconductor quantum chips at very low temperatures. As it is difficult to build a low-temperature CMOS model by simply extracting parameters, this provided the motivation for us to establish a sub-circuit model to correct the kink deviations. In the short term, we can design and simulate cryogenic CMOS circuits using our model. In the longer term, cryo-CMOS can help us implement the cryogenic readout and control system for quantum computing. We plan to implement ADC (Analog-to-Digital Converter), DAC (Digital-to-Analog Converter), oscillator, FPGA (Field Programmable Gate Array), and other adaptive/passive integrated circuits at cryogenic temperatures or in irradiative environments. This involves research and progress in three main topics, namely: Cryo-CMOS characterization and modelling, Cryogenic integrated circuits on chips and Cryogenic circuits on boards. More and more researchers are beginning to pay attention to cryogenic electronics. With the current standard of, and growing pace of, development in quantum computing, cryogenic electronics will also receive faster development, and can be applied in future quantum computing and space exploration systems.

A 64-channels neural interface for biopotentials recording and PNS stimulation.

A biomedical interface that combines into a single and compact device the recording of biopotentials and the electrical stimulation of neural fibres is presented. It is intended for enabling the control over a robotic hand and for restoring the sensory feedback in amputees by directly interfacing the peripheral nervous system (PNS) in closed-loop. A modular system consisting in one or more independent 16-channels bidirectional units was conceived. Each module is based on three 0.35μm bulk-CMOS integrated circuits (ICs): a recording unit, a High-Voltage (HV) stimulator and a HV booster. A tunable bandwidth (10Hz-8kHz) allows the recording IC to acquire both electroneurographyc (ENG) and electromiographyc (EMG) signals with a programmable gain up to 43.5dB. The signals are then converted into a digital domain by means of a ΣΔ converter. Due to the typical high impedance at the electrode-tissue interface, a programmable HV booster that increases the stimulation voltage up to 19V was designed. It is directly controlled by the stimulation module that generates current-based pulses with a programmable amplitude and pulse-width. The whole system was validated by means of in-vivo experiments in rats.

A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS

Silicon-photonics is an emerging technology that can overcome the tradeoffs faced by traditional electrical I/O. Due to ballooning development costs for advanced CMOS nodes, however, widespread adoption necessitates seamless photonics integration into mainstream processes, with as few process changes as possible. In this work, we demonstrate a silicon-photonic link with optical devices and electronics integrated on the same chip in a 0.18 µm bulk CMOS memory periphery process. To enable waveguides and optics in process-native polysilicon, we introduce deep-trench isolation, placed underneath to prevent optical mode leakage into the bulk silicon substrate, and implant-amorphization to reduce polysilicon loss. A resonant defect-trap photodetector using polysilicon eliminates need for germanium integration and completes the fully polysilicon-based photonics platform. Transceiver circuits take advantage of photonic device integration, achieving 350 fJ/b transmit and 71 µA pp BER = 10 -12 receiver sensitivity at 5 Gb/s. We show high fabrication uniformity and high-Q resonators, enabling dense wavelength-division multiplexing with 9-wavelength 45 Gb/s transmit/receive data-rates per waveguide/fiber. To combat perturbations to variation- and thermally-sensitive resonant devices, we demonstrate an on-chip thermal tuning feedback loop that locks the resonance to the laser wavelength. A 5 m optical chip-to-chip link achieves 5 Gb/s while consuming 3 pJ/b and 12 pJ/bit of circuit and optical energy, respectively.

A Recursive Switched-Capacitor DC-DC Converter Achieving &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$2^{N}-1$&lt;/tex&gt;&lt;/formula&gt; Ratios With High Efficiency Over a Wide Output Voltage Range

A Recursive Switched-Capacitor (RSC) topology is introduced that enables reconfiguration among 2 N -1 conversion ratios while achieving minimal capacitive charge-sharing loss for a given silicon area. All 2 N -1 ratios are realized by strategically interconnecting N 2:1 SC cells either in series, in parallel, or in a stacked configuration such that the number of input and ground connections are maximized in order to minimize cascaded losses. Importantly, all ratios are dynamically reconfigurable without disconnecting a single capacitor, all while ensuring optimal capacitance/conductance relative-sizing. The RSC topology is inherently regular, enabling recursive inter-cell connection and recursive binary-slicing that implement ratio-reconfiguration with minimum complexity and losses. A scalable all-digital binary search controller is employed to perform ratio-reconfiguration among the available 2 N -1 ratios without using any ratio-threshold generation circuitry. To validate the topology, a 4 bit RSC is fully integrated in 0.25 μm bulk CMOS using MIM capacitors, achieving greater than 70% efficiency over a 0.8-2.2 V output voltage range with 85.8% peak-efficiency from a 2.5V input supply. Compared to a co-fabricated three-ratio (1/3, 1/2, 2/3) Series-Parallel SC converter, the RSC achieves a 40.4% larger output operating range (from 0.04 to 2.2 V), and fills the efficiency-drops in-between the three-ratios by 8% with a 940 Ω load.

On-Chip Photovoltaic Energy Conversion in Bulk-CMOS for Indoor Applications

Modeling and design aspects of on-chip photovoltaic energy conversion, voltage boosting and storage in bulk CMOS are investigated under the constraints of indoor illumination and small form factor. A power-supply architecture consisting of a photovoltaic converter, a clock generator, a charge-pump and a storage capacitor is considered. Maximization of the recharging rate of the capacitor at the low end of irradiance is adopted as the aim of design optimization. First, photodiodes available for conversion in bulk CMOS are comparatively evaluated, and potentially the most efficient ones are experimentally characterized for the typical range of indoor irradiance. Next, a generic model is developed and experimentally verified for a clock generator powered by a converter built with these photodiodes. This is followed by the modeling and experimental verification of a Dickson charge-pump whose single-device rectifier is free of body effect and near-ideal in forward characteristic. These models are based on the subthreshold operation of devices as necessitated by optimization under the limitations of bulk-CMOS stacking and indoor irradiance. Guidelines for design optimization are derived from these models. Experimental work is based on two test chips fabricated in 0.18- μm bulk CMOS with deep n-well option.

A 200 °C Quad-Output Buck Type Switched Mode Power Supply IC

A high temperature (&amp;gt;200 °C), quad-output, buck type switched-mode power supply (SMPS) IC capable of operating over a wide input supply range of 6 V to 15 V is described. The IC is a compact power supply solution for multi-voltage microprocessors, sensors, and actuators. The SMPS topology is a 112 kHz fixed-frequency, synchronous buck converter with slope compensation. A novel internal feedback design enables the output voltages to be pin-programmed to one of three common supply voltages—5 V, 3.3 V, or 1.8 V—while an external resistor divider can also be used for arbitrary voltage programming. Integrated power supply output MOSFET switches minimize the external part count and synchronous rectification reduces power dissipation and improves current capacity. The IC was fabricated in a conventional, low-cost, 0.5 μm bulk CMOS foundry process. Patented circuit design techniques allow the IC to operate in excess of 200 °C and circuit operation was demonstrated at ambient temperatures up to 225 °C. The foundry process is optimized for 5 V applications, however, the IC accepts input voltages up to 15 V and can produce outputs up to 10 V by utilizing extended drain single- and double-sided NMOS and PMOS transistors for the linear regulator pass transistor, error amplifier, and SMPS switches. The high-side FETs are controlled through capacitive coupled level shift circuits to ensure the gate-oxide voltage limits are not exceeded while still maintaining fast signal transitions. The IC also includes a tunable, 25 MHz monolithic oscillator that is programmable over a SPI serial interface. The oscillator bias current is comprised of a programmable constant-gm bias current and a programmable PTAT bias current. The programmability can be used to set the oscillation frequency, but can also be used together with a calibration curve on a microcontroller to achieve a more stable oscillation frequency over temperature. The output current of the quad SMPS was limited to 70 mA by a lower than expected saturation current of the extended-drain PMOS switch devices. The system showed good line regulation (&amp;lt;0.1%) and 50% load step response stability (+/− 100 mV) at a nominal output current of 50 mA when tested at 200 °C ambient.

An energy-efficient reconfigurable analog-to-digital converter for orthopedic implants

This paper presents a pipelined analog to digital converter (ADC) with reconfigurable resolution and sampling rate for biomedical applications. Significant power saving is achieved by turning off the sample-and-hold stage and the first two pipeline stages of the ADC instead of turning off the last two stages. The reconfiguration scheme allows having three modes of operation with variable resolutions and sampling rates. Reconfigurable operational transconductance amplifiers and an interference elimination technique have been employed to optimize power-speed-accuracy performance in biomedical instrumentation. The proposed ADC exhibits a 56.9 dB SNDR with 35.4 mW power consumption in 10-bit, 40 MS/s mode and 49.2 dB SNDR with only 7.9 mW power consumption in 8-bit, 2.5 MS/s mode. The area of the core layout is 1.9 mm2 in a 0.35 μm bulk-CMOS process.

A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory

The realization of a low-cost passive radio frequency identification (RFID) tag requires the ability to fabricate the system in a bulk CMOS process without any additional process steps. A recently presented single-poly C-Flash memory bitcell provides an ultralow-power option for implementation of a nonvolatile memory array for use in an RFID system, using only core masks. This cell requires the application of a 10-V potential difference between the cell's control lines for program and erase operations. Providing the required voltages, while using only standard devices results in several design challenges for the voltage drivers, such as the elimination of gate-induced drain leakage (GIDL) currents. In this paper, we present a pair of voltage driver architectures that utilize novel techniques to overcome these challenges. In addition, for the first time, we present an in-depth analysis of the dynamic behavior of standard level shifters. This analysis is applied to our proposed GIDL-free level shifters to provide a sizing methodology for optimization of the area, energy-per-operation, and delay of these circuits. The drivers were designed and fabricated in a TowerJazz 0.18- μm bulk CMOS technology, providing the required functionality with a low static-power figure of 47-49 pW and 0.03-0.36 pJ energy-per-operation.

Highly integrated CMOS RF SPDT switch with ESD and unit cell optimisation in MCM

Presented is the performance of a highly integrated RF single-pole double-throw (SPDT) switch fabricated in a 0.18 µm bulk CMOS process and housed in a low-cost laminated multi-chip module (MCM-L) package. A switch controller is also implemented and consumes ∼40 µA from a 3.4 V supply. The switch, based upon the 1.8 V thin-oxide devices with resistive body-floating and unit cell layout optimisation techniques, achieves an insertion loss of 0.52/0.78 dB at 0.9/2.45 GHz, respectively. TX-to-RX isolation of > 29 dB and return loss of > 15 dB are achieved at these frequencies. The measured IP1dB of 21.7/21.2 dBm and IIP3 of 38.3/37.4 dBm are accomplished at 0.9/2.45 GHz, respectively. Finally, the switch achieves a RF electrostatic discharge (ESD) rating of 4 kV for the ± 2 kV human body model and 500 V for the ± 200 V machine model.

Characterization and Reliability of custom digital ASIC designs using a 0.8μm bulk CMOS process for high temperature applications

With today's quickly changing technology, part obsolescence often forces unanticipated and costly design changes outside the normal product life cycle. Custom ASICs can be used to fill this gap and gain other advantages such as reduced parts count, higher performance, and higher reliability. Two digital 0.8μm bulk CMOS ASICs have been successfully implemented, providing higher reliability and performance than their replacement parts at 225°C. In this paper we examine some of the design issues encountered during their implementation, including process selection, library characterization at 225°C and above, performance, testing and qualification. External analog circuitry was integrated to further reduce parts count and increase reliability. In conclusion, we have found bulk CMOS to be an acceptable process for custom ASICs in high temperature environments.

Fully Integrated Switch-LNA Front-End IC Design in CMOS: A Systematic Approach for WLAN

A fully integrated front-end IC is demonstrated for 802.11b/g transceivers with integrated power amplifiers. The SP3T-LNA architecture integrates Bluetooth® functionality with transmit and receive for wireless LAN. The transmit switch achieves a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> greater than 33.0 dBm at 2.5 GHz by employing a cross-biasing approach, transistor stacking and deep n-well process. Power handling techniques used for the switches and the associated performance tradeoffs are discussed. The measured noise figure of the LNA and the receive chain comprising both an LNA and a switch is 1.5 dB and 3.0 dB, respectively. The LNA achieves an IIP3 of 7.0 dBm while consuming 7.0 mA of current. The measured switching times are less than 350 ns. The front-end IC employs a 3.3 V supply and occupies 0.64 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 0.18 μm bulk CMOS technology.

Suppressing the hot carrier injection degradation rate in total ionizing dose effect hardened nMOSFETs

Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose (TID) effect. However, their capability of resisting the hot carrier effect (HCE) has also been proven to be very weak. In this paper, the reason why the annular gate nMOSFETs have good TID but bad HCE resistance is discussed in detail, and an improved design to locate the source contacts only along one side of the annular gate is used to weaken the HCE degradation. The good TID and HCE hardened capability of the design are verified by the experiments for I/O and core nMOSFETs in a 0.18 μm bulk CMOS technology. In addition, the shortcoming of this design is also discussed and the TID and the HCE characteristics of the replacers (the annular source nMOSFETs) are also studied to provide a possible alternative for the designers.

Design considerations for integration of Horizontal Current Bipolar Transistor (HCBT) with 0.18 μm bulk CMOS technology

Design issues associated with integration of Horizontal Current Bipolar Transistor (HCBT) with 0.18 μm bulk CMOS process are examined and the effects of fabrication parameters on transistor performance analyzed. HCBT is fabricated on a sidewall of a silicon hill defined by shallow trench isolation (STI). Height of the transistor is limited by the STI depth of 350 nm. Impact of vertical and horizontal dimensions on electrical performance of the transistor are analyzed by simulations with emphasis on extrinsic base design. Base current is reduced by high extrinsic base concentration and increased link-base length. Current gain is increased from 16 to 67 for transistor processed with the optimized extrinsic base profile. High-frequency performance is degraded by the collector charge sharing effect and can be improved by the larger separation between the extrinsic base and emitter, which is achieved with a small thickness of emitter polysilicon region. Misalignment tolerances of the extrinsic base implantation mask show no great impact on transistor’s AC performance.

60 GHz compact integrated cross-coupled SIR-MH bandpass filter on bulk CMOS

A new 60 GHz fourth-order cross-coupled bandpass filter using a step-impedance-resonator (SIR) miniaturised open-loop resonator and the miniaturised-hairpin (MH) resonator was designed and fabricated on 0.13 µm bulk CMOS. It has 8.5 GHz (58–66.5 GHz) bandwidth, 5.9 dB insertion loss, and better than 10 dB return loss over the whole passband, and exhibits high selectivity and a compact size of 714.9×484 µm (0.346 mm2). This filter is the first reported cross-coupled filter above 40 GHz on CMOS.

A low-power RF integrated circuit for implantable sensors

A low-power low-voltage analog signal processing circuit has been designed, fabricated, and tested. The circuit is capable of processing an analog sensor current and producing an ASK modulated digital signal with modulating signal frequency proportional to the sensor current level. An on-chip regulator has been included to stabilize the supply voltage received from an external RF power source. The circuit can operate with a power supply as low as 1 V and consumes only about 20 µW of power, which is therefore very suitable for implantable biomedical applications. The whole chip was laid out and fabricated in a 0.35 µm bulk CMOS technology. Experimental results show good agreement with the simulation results.

50 Gbit/s 2:1 multiplexer in 0.13 µm CMOS technology

A fully integrated 2:1 multiplexer IC which operates at up to 50 Gbit/s data rate is presented. The MUX uses inductive shunt peaking and an output series inductor for higher bandwidth. The MUX directly drives the 50 Ω load. The IC is fabricated in a 0.13 µm bulk CMOS technology and draws 65 mA at 1.5 V supply voltage. The output voltage swing is 2×100 mV.

0.35 μm CMOS T/R Switch for 2.4 GHz Short Range Wireless Applications

This paper describes the design and implementation of a transmit/receive switch for 2.4 GHz ISM band applications. The T/R switch is implemented in a 0.35 μm bulk CMOS process and it occupies 150 μm · 170 μm of die area. A parasitic MOSFET model including bulk resistance is used to optimize the physical dimensions of the transistors with regard to insertion loss and isolation. The measured insertion loss is 1.3 dB without port matching. Simulations using measured s-parameters indicate that an insertion loss of 0.8 dB can be obtained with a conjugate match. The measured isolation is 42 dB and the maximum transmit power is 16 dBm.

A new procedure to extract the threshold voltage of MOSFETs using noise-reduction techniques

A new way to extract the threshold voltage of MOSFET is presented. It combines the well known extraction method based on determining the maximum of the second derivative of I D with respect to V GS for V DS approaching zero, with digital signal processing techniques to increase the signal/noise ratio. The derivatives are calculated on the Fourier transform space and a low-pass filter is used to smooth the function before taking the inverse transform. This procedure combines the advantage of being a standard method based on a physical property, with a noise immunity comparable to the most recent extraction methods, without requiring a costly computing effort. The results are compared with other methods using experimental data from 0.7 and 0.07 μm bulk CMOS technologies.