Mixer Topology Research Articles

13…67 GHz Frequency Mixer

Introduction. The requirements for the performance of measuring devices, including their operating frequency, are constantly becoming stricter. This encourages the creation of wide-band microcircuits for application in microwave blocks of devices, such as vector network analyzers (VNA) and spectrum analyzers (SA). One of such microcircuits, used in the receiver system, is a frequency mixer. The operating range of the mixer determines the operating range of the measuring instrument. Aim. Research and development of an ultra-wideband integrated circuit for a 13…67 GHz frequency mixer based on the GaAs QSBD technology by Micran JSC. Materials and methods. An analysis of existing classic and modified circuit transformers used in mixers was conducted. A modification of the transformer circuit, which allowed a frequency range of 10…70 GHz to be achieved,was proposed. Based on the obtained transformer and GaAs diode technology of Micran JSC, a complete mixer topology was developed and produced. An electrodynamic analysis of the integrated circuit was carried out; measurements were performed using a VNA up to 67 GHz. Results. A wideband mixer with a frequency range of 10…67 GHz is developed. A circuit design is proposed based on a balanced circuit with modified transformers and an intermediate frequency output circuit. The calculated dependences and measurement results of the integrated circuit of the mixer are presented. The mixer exhibits a conversion loss of less than 10 dB in the range of 10…67 GHz. Conclusion. A new broadband transformer with a range of operating frequencies from 10 to 70 GHz was developed. On its basis, a mixer microcircuit was simulated and manufactured. This microcircuit can be used in the receiving and transmitting units of modern measuring instruments. In terms of its characteristics, the proposed microcircuit is an analog of the Marki Mikrowave MM1-1467L mixer.

Wideband ring mixer for band #1 of MB-OFDM systems in 180 nm CMOS technology

Abstract A wideband down conversion ring mixer is proposed for multi band orthogonal frequency division multiplexing (MB-OFDM) system in 180 nm CMOS technology. The mixer is essentially used in a heterodyne wireless receiver to enhance the selectivity of the system. Being a nonlinear system, the mixer dominates the overall performance of the system. The design of down conversion mixer is the most challenging part of a receive chain. Wideband impedance matching always remains a challenge in any radio frequency integrated circuit design. This paper presents the design of a ring mixer with high linearity, wideband impedance matching using differential resistive impedance matching and without using any DC bias. The proposed mixer is tuned for a frequency of 3.432 GHz of band 1 of the MB-OFDM system. Mixer core is based on the FET ring mixer topology. The mixer is implemented in 180 nm CMOS technology. The mixer achieves the minimum conversion loss of 10.49 dB, 1 dB compression point (P1) of 12.40 dBm, third order input intercept point (IIP3) of 12.01 dBm, a minimum SSB noise figure of 8.99 dB, and S 11 of less than -10 dB over the frequency range of 0 to 13.61 GHz . The layout of the mixer records an active area of 183.75 μm 2 .

Review of FET Ring mixer topologies for wireless communication

This paper presents an important component of the radio frequency transceiver called as mixer. It is a critical component and plays an important role as it has the ability for frequency conversion in RF systems. This paper focuses on double balanced ring topology of passive mixers. Ring mixer is one of the best example of passive mixers because of double balanced in nature. Double balanced is one of the most widely used topology as it suppresses both LO and RF at the output the of mixer. Various techniques have been used to improve the performance of standard topology of the ring mixer such as noise figure, linearity, conversion gain and port isolation, so these techniques have been re-viewed and compared with the previous studies. This paper also have brief discussion about a useful passive circuitry say balun and its designing with mixer as this is generally used to convert single ended signal to differential signal.

Comparison of active dual‐gate and passive mixers for terahertz applications

The authors propose four versions of a dual-gate active down-conversion mixer for H-band applications. The mixer operates at a local oscillator (LO) frequency of 240 GHz. It is designed for maximum conversion gain and a large bandwidth of at least 50 GHz from 220 to 270 GHz. Furthermore, the mixer is .optimised to operate at low LO power levels beneath 0 dBm. This renders power hungry LO buffer stages redundant. Hereby, the necessary chip size and the overall power consumption of fully integrated receivers can be drastically reduced. Four different versions of the downconverter were designed. Firstly, the layout of the transistors was changed from a conventional multi-transistor cell design to a mixer topology within the multi-finger transistor cell. Secondly, two on-chip solutions to decouple the drain voltage from the intermediate frequency (IF) signal were realised to facilitate zero-IF conversion: a resistive and an active load. The results are presented and the advantages and disadvantages of the four versions for the usage in terahertz applications are thoroughly analysed. Finally, the active dual-gate mixers are compared to a state-of-the-art resistive mixer for H-band with regard to conversion gain, bandwidth, linearity, noise figure and chip size.

A GaN-on-Si passive upconversion mixer for Ku-band applications

This paper showcases a passive single side-band (SSB) subharmonically pumped (SHP) GaN on Si mixer intended for operation in the Ku band. A passive topology has been selected in order to test the viability of these kinds of designs for GaN applications. By utilising the SSB SHP mixer, it is possible to reduce the energy consumption of a complete transmission system implementation. Two techniques to enhance the performance of the mixer are tested. First, the quasi-lumped method has been employed to reduce the size of the stubs needed to implement the mixer topology. Secondly, octagonal tapered inductors were used to obtain higher quality factors and narrow the frequency response of the lumped-element hybrids. The final design occupies an area of 2720μm×1514μm, including pads. Measurements show a performance in line with the simulations, with a slight increase in its losses with respect to the simulation results. Through the measurement of a transistor of the technology, it is demonstrated that this deviation is caused by the variability of the process and its low technology readiness level (TRL). The results are very promising and prove the advantages of implementing passive mixers for high-frequency applications in GaN on Si technologies.

An ultra-low-power 5GHz front end with feedforward body bias LNA and single to double balance subharmonic mixer topology for direct conversion receiver

An ultra-low-power 5GHz front end with feedforward body bias LNA and single to double balance subharmonic mixer topology for direct conversion receiver

An mm-Wave CMOS I–Q Subharmonic Resistive Mixer for Wideband Zero-IF Receivers

In this letter, we propose a novel wideband subharmonically pumped fully differential I–Q resistive mixer architecture, which eliminates the necessity for on-chip dc-blocking capacitors to integrate IF amplifiers. The proposed differential subharmonic mixer topology is verified by presenting a CMOS millimeter-wave monolithic integrated circuit (MMIC), which includes the mixer and two on-chip differential IF amplifiers at the mixer’s I- and Q-channels. The 3-dB IF frequency bandwidth is measured from 0.01 to 5 GHz with a peak conversion gain (CG) of −2 dB and an image rejection ratio (IRR) of more than 25 dB over the IF frequency range. The proposed mixer covers the input signal (RF) frequency from 170 to 185 GHz. The mixer has also been tested with an on-chip voltage-controlled oscillator (VCO) and shows −4.7-dB CG with a 3-dB IF bandwidth from 0.01 to 4.5 GHz.

Linearity improvement of RF mixer using double-linearization for 5 GHz applications

With 5G expected to roll out in 2020, the 5 GHz band will be sort after for sub-6 GHz 5G implementation. The feasibility of the wireless systems at 5 GHz will be primarily determined by the linearity of the RF down-converters in the receiver system. With growing battery-powered, portable, and wearable wireless devices, the task of achieving excellent linearity with low power consumption in RF down-converters is difficult. This work tries to overcome the difficulty by proposing a double-linearization (DL) based RF mixer. The proposed mixer circuit is designed using UMC 180 nm CMOS process libraries, and the post-layout simulations are carried out using Cadence SpectreRF in the presence of single-sideband phase noise. For a fundamental tone at 5 GHz and an interferer at 5.01 GHz, the proposed mixer using double-linearization achieves an input-referred third-order intercept point (IIP3) of 11.04 dBm, which is a 15 dB improvement over the IIP3 obtained before employing the proposed scheme. The proposed RF mixer circuit provides a conversion gain of 15.33 dB and an integrated double-sideband noise figure (DSB-NF) of 16.39 dB while consuming a low power of 1.5mW from a 1 V supply. The circuit also boasts an SFDR of 81.36 dB and IMR2 of 192.1 dB. The IIP3/mW ratio of the DL based mixer is 6.5 dB more than the recently proposed mixer topology. The layout of the proposed mixer consumes 0.57mm2.

Linearization of Active Downconversion Mixers at the IF Using Feedforward Cancellation

A feedforward linearization technique for third-order intermodulation (IM3) distortion cancellation in active downconversion mixers is proposed in this paper. Low-frequency second-order intermodulation (IM2) tones are created and multiplied with the mixer’s output to generate low-frequency IM3 replicas for cancellation. Implemented mostly at the IF band, this technique brings a third-order input intercept point (IIP3) improvement independently of the mixer topology and is robust against parasitic parameters. A 2-GHz current commutating mixer linearized by the proposed technique is designed and fabricated using a 130-nm CMOS process to verify the concept. Experimental results show that the mixer with a unit-gain amplifier delivers 8.5 dB of conversion gain and has an IIP3 of 2.5 dBm before linearization. The linearization technique improves the mixer’s IIP3 by 12 dB for input signals as large as −15 dBm. The technique has a negligible impact on the mixer’s gain and incurs a noise figure penalty of less than 0.2 dB. The mixer with the unit-gain amplifier consumes a current of 8.4 mA, while the proposed technique circuitry consumes an extra current of 4.2 mA, both using a 1.2-V voltage supply.

A Reconfigurable Low-Voltage and Low-Power Millimeter-Wave Dual-Band Mixer in 65-nm CMOS

In this paper, we propose, investigate, and demonstrate a reconfigurable low-voltage and low-power millimeter-wave mixer in a 65-nm CMOS, which can be switched as either a subharmonic mixer (SHM) or a fundamental mixer (FM) for the dual-band applications. Based on a modified Gilbert mixer topology, the proposed CMOS mixer can operate at a low supply voltage and low local oscillator (LO) pumping power while providing good performance in both SHM and FM modes. To the best of our knowledge, this is the first reported Gilbert SHM based on the stacked switching quads in a low-voltage CMOS technology. Under 1-V supply voltage and −3-dBm LO pumping power, the measured conversion gain (CG) of the proposed CMOS mixer is −4.8 ± 1.5 dB from 34 to 56 GHz and −0.1 ± 1.5 dB from 17 to 43 GHz in the SHM and FM modes, respectively. The measured double-sideband (DSB) noise figure (NF) is 18.5–20 dB from 37 to 49 GHz and 12.4–14 dB from 17 to 35 GHz in the SHM and FM modes, respectively. The measured input third-order intercept point (IIP3) is 2.9 and 3.4 dBm, respectively, for the SHM and FM modes at the LO frequency of 22 GHz. In addition, the total dc power consumption of the proposed mixer including output buffers is 7 mW in both the operation modes.

A Methodology Improving Off-Chip, Lumped RF Impedance Matching Network Response Accuracy

Impedance matching is concurrent with any radio frequency (RF) circuit design and is essential for maximizing the gain and efficiency while minimizing the noise of high-frequency amplifiers as well as some mixer topologies. The main impedance matching network components are capacitors, inductors, and RF transformers all of which contain parasitic parameters that influence the matching response S11 curve. After calculating matching network component values using classical matching techniques, the measured and simulated response curves differ depending on the target frequency. This results in multiple calculations and measurement cycles in order to precisely match the source and load at the desired frequency. This article proposes an algorithm and methodology of estimating component parasitic parameters and taking them into account when calculating the main component parameters (capacitance and inductance). The proposed algorithm has been implemented as a toolbox in Cadence Virtuoso and verified through simulation and measurements. Measurement results show, that at 500 MHz 10% tolerance components with parasitics included and values based on classical theory provide a 3.2–9.8% offset from the target frequency. In the same conditions, matching networks with compensated (according to the proposed algorithm) values provide 0.1–8.8% target frequency offset. At 1500 MHz 10% components provided 4–12.3% (non-compensated) and 1–8.7% (compensated) target frequency offset ranges. At 3000 MHz. The frequency offset range of using compensated matching network component values is reduced from 5.5–15.1% to 1.3–8.1%.

Broadband analogue predistortion using a distortion generator based on two-stage RF mixer topology

ABSTRACTAn analogue predistorter using a distortion generator based on a two-stage radio frequency mixer topology is presented. The proposed distortion generator achieves fundamental signal cancellation without using a signal cancellation loop or a resonant circuit, thus it generates an error signal that predominantly consists of unwanted intermodulation distortion (IMD). Measurements are performed using multi-tones, WLAN- and Terrestrial Trunked Radio (TETRA)-modulated signals. Distortion generator provides high levels of IMD and achieves more than 40 dB fundamental signal cancellation across a bandwidth of 120 MHz. A proof-of-concept predistorter was constructed to validate the usefulness of the proposed distortion generator, which achieves up to 15 dB suppression of IMD and adjacent channel power ratio at the output of a power amplifier. Distortion generator and predistorter gave similar results at multiple frequencies between 920 MHz and 2 GHz, with different test signals having bandwidths ranging from 25 kHz to 120 MHz.

A 0.35-V 520- $\mu \text{W}$ 2.4-GHz Current-Bleeding Mixer With Inductive-Gate and Forward-Body Bias, Achieving >13-dB Conversion Gain and >55-dB Port-to-Port Isolation

An ultralow voltage micropower 2.4-GHz current-bleeding active mixer for energy-harvesting Bluetooth low energy/ZigBee applications is reported. It features a double-balanced mixer topology combining nMOS current-bleeding transistors with a pMOS local oscillator switching quad, and forward-body bias and inductive-gate bias techniques to secure an adequate performance at a supply voltage down to 0.35 V. Fabricated in 0.13- $\mu \text{m}$ CMOS, the prototype exhibits a conversion gain of 13.77 dB, a third-order intercept point of −3.5 dBm, and a noise figure of 18 dB. The power consumption is $520~\mu \text{W}$ , and port-to-port isolation is >55 dB. The achieved figure of merit compares favorably with the state of the art.

A Low-Power and High-Gain Ultra-Wideband Down-Conversion Active Mixer in 0.18- $$\upmu $$ μ m SiGe Bi-CMOS Technology

This paper presents an ultra-wideband down-conversion mixer chip covering the frequency range from 3.1 to 10.6 GHz by using TSMC 0.18 $$\upmu $$μm SiGe BiCMOS technology. The architecture used is based on Gilbert-cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. In the proposed circuit, a LO CMOS series-parallel switched topology is adopted to reduce the supply voltage and dc consumption for UWB system. The measured results of the proposed mixer achieve: $$\hbox {Gain}= 9.8$$Gain=9.8---10.6 dB, $$\hbox {flatness} =0.8$$flatness=0.8 dB, IIP$$3 = -8$$3=-8 dBm at 7.26 GHz, and so on. Port-to-port isolations (LO---RF, LO---IF, and RF---IF) are better than about ź40 dB, and the total dc power consumption with output buffers is 4.3 mW from a 1 V supply voltage. The current output buffer is about 3.7 mW. The mixer topology presented in this paper results suitable for low-power UWB system applications.

A New Passive CMOS Mixer With LO Shaping Technique for mmWave Applications

A mmWave (mmW) passive mixer topology based on a novel LO waveform-shaping technique using non-linear transmission line (NLTL) is proposed. The NLTL is constructed using series inductors and shunt varactors. It boosts the LO signal swing and reshapes the LO waveform to have higher amplitude and narrower pulses, resulting in higher gain, better linearity, and lower Noise Figure (NF) of the mixer. Mixers operating at 60 GHz are designed and implemented using 65 nm CMOS process. Simulation results show the mixer with the proposed technique obtains an NF of 5.5 dB, an input-referred $\text{P}_{1 \text{dB}}$ $(\text{IP}_{1 \text{dB}})$ of 0 dBm, and a voltage conversion gain of 1.2 dB with 0 dBm LO signal and zero dc power consumption. Silicon measurement results show that the proposed LO shaping technique improves the conversion gain by 2.5 dB and the $\text{IP}_{1 \text{dB}}$ by 3 dB.

BiCMOS Colpitts oscillator for vector-sum interpolators

Purpose The demand for higher bandwidth has resulted in the development of mm-wave phased array systems. This paper aims to explore a technique that could be used to feed the individual antennas in a mm-wave phased array system with the appropriate phase shifted signal to achieve the required directivity. It presents differential Colpitts oscillators at 5 and 60 GHz that can provide differential output signals to the quadrature signal generators in the proposed phase shifter system. Design/methodology/approach The phase shifter system comprises a differential Colpitts voltage controlled oscillator (VCO) and utilizes the vector-sum technique to generate the phase shifted signal. The differential VCO is connected in the common-collector configuration for the 5-GHz VCO, and is extended using a cascode transistor for the 60-GHz VCO for better stability at mm-wave. The vector sum is achieved using a variable gain amplifier (VGA) that combines the in-phase and quadrature phase signal, generated from oscillator output using hybrid Lange couplers. The devices were fabricated using IBM 130-nm SiGe BiCMOS process, and simulations were performed with a process design kit provided by the foundry. Findings The measured results of the 5-GHz and 60-GHz VCOs indicate that differential Colpitts VCO could generate oscillator output with good phase noise performance. The simulation results of the phase shifter system indicate that the generation of signals with phases from 0° to 360° in steps of 22.5° was achieved using the proposed approach. A Gilbert mixer topology was used for the VGA and the linearity was improved by a pre-distortion circuit implemented using an inverse tanh cell. Originality/value The measurement results indicate that differential Colpitts oscillator in common-collector configuration could be used to generate differential VCO signals for the vector-sum phase shifter. The simulation results of the proposed phase shifter system at mm-wave show that the phase shift could be realised at a total power consumption of 200 mW.

A COMPARATIVE STUDY OF DIFFERENT TYPES OF MIXER TOPOLOGIES

In this paper, a comparative study of different types of mixer topologies is presented. Gilbert cell is widely used as core of the mixer because it provides high conversion gain, good port-to-port isolation and low even-order distortion. It is found that the linearity of mixer is very good for Multi-Tanh technique by incorporating multiple differential trans-conductance stage but it reaches to very low conversion gain whereas, use of current bleeding technique increase linearity and conversion gain of the mixer by adding current source to increase the bias current at the expense of power consumption. A very low value of noise figure can be achieved with the switched biasing technique by replacing current source with parallel connected nMOS transistors but due to use of the transistor in place of tail current source, linearity is degraded and more power is consumed. Folded Cascode Technique is used to reduce DC supply voltage by folding the LO switching stage with pMOS transistors in switching stage but it degrades the noise figure. Bulk-driven technique can be employed to lower down the power consumption by providing the switching action via the gate of LO (RF) and amplification by the bulk of LO (RF) transistors, however it reduces the linearity. High linearity is obtained by using CCPD (Cross coupled post distortion) technique by cancelling of third order derivatives but it decreases the conversion gain and consume more power due to increase in the number of auxiliary transistors. MGTR enables to achieve high linearity by incorporating auxiliary transistor but it decreases the overall conversion gain and increases noise figure of the mixer. So it is observed that there is a trade-off among the performance metrics, i.e., conversion gain, noise figure linearity, and power consumption of the mixer.

Harmonic Rejection in 2.4 GHz Gilbert Cell Mixer for Terrestrial Microwave Communication systems

Mixer is one of the significant components of the radio frequency transceiver that translate baseband signal into RF and vice versa. In this paper, 2.4 GHz double balanced Gilbert Cell Mixer topology was simulated to study its important properties such as Conversion Gain, Linearity, Noise Figure and Port Isolation. Further, a band pass filter is added in to the design at IF port so as to reject harmonics. The mixer topology is designed and simulated using NMOS 180 nm CMOS technology in Advanced Design Systems. As a result, conversion gain of 8.303 dB, high linearity, high port isolation and Harmonic Rejection Ratio > 80 dB is achieved. General Terms Harmonic rejection in down conversion Gilbert cell Mixer

A 90-nm CMOS V-Band Low-Power Image-Reject Receiver Front-End With High-Speed Auto-Wake-Up and Gain Controls

A low-power auto-wake-up image-reject receiver front-end in 90-nm CMOS technology is presented for V-band applications. The proposed front-end generally operates in the sleep mode and consumes 19 mW. When an RF signal greater than ${-}{\hbox{50}}$ dBm is received, the front-end wakes up automatically and enters into the active mode consuming only 46-mW power. Adjustable linearity $({\rm IP}_{{{1{\rm dB}}}})$ of the front-end is provided by changing two gain modes (high- and low-gain modes). When input RF power is higher than $-{\hbox{30}}$ dBm, ${\rm IP}_{{{1{\rm dB}}}}$ will be improved (from high-gain mode to low-gain mode). Experiments show ${\rm IP}_{{{1{\rm dB}}}}$ of $-{\hbox{25.2}}$ and $-{\hbox{22.5}}$ dBm in high- and low-gain modes, respectively. An image-reject ratio greater than 32 dB is measured when using the proposed image-reject mixer topology. All passive phase-shift couplers for realizing the image-rejection are composed of standard CMOS lumped elements, thereby considerably reducing the chip size (0.82 mm $^{{{2}}}$ ).

Double-Balanced Graphene Integrated Mixer with Outstanding Linearity.

A monolithic double-balanced graphene mixer integrated circuit (IC) has been successfully designed and fabricated. The IC adopted the cross-coupled resistive mixer topology, integrating four 500 nm-gate-length graphene field-effect transistors (GFETs), four on-chip inductors, and four on-chip capacitors. Passive-first-active-last fabrication flow was developed on 200 mm CMOS wafers. CMOS back-end-of-line processes were utilized to realize most fabrication steps followed by GFET-customized processes. Test results show excellent output spectrum purity with suppressed radio frequency (RF) and local oscillation (LO) signals feedthroughs, and third-order input intercept (IIP3) reaches as high as 21 dBm. The results are compared with a fabricated single-GEFT mixer, which generates IIP3 of 16.5 dBm. Stand-alone 500 nm-gate-length GFETs feature cutoff frequency 22 GHz and maximum oscillation frequency 20.7 GHz RF performance. The double-balanced mixer IC operated with off-chip baluns realizing a print-circuit-board level electronic system. It demonstrates graphene's potential to compete with other semiconductor technologies in RF front-end applications.