Mixed-signal VLSI Research Articles

Building a Microelectronics Research Group from the Ground Up

Microelectronics are the minuscule components that power our modern world, from your smartphone to the systems that keep jet airliners in the sky. These essential components, such as transistors, resistors, capacitors, and inductors are the building blocks of microchips – the tiny computing units that process vast quantities of binary information. However, the world around us isn’t binary. Engineers must develop ways to translate between the analogue world that we inhabit and the binary world of chips. Over the last 30 years, Professor Rui Martins of the University of Macau has built a world-renowned research lab – the State Key Laboratory of Analog and Mixed-Signal VLSI – focused on further bridging the gap between analogue and digital.

An Initiative Towards Analog And Mixed Signal Design - Prakalp

Abstract This paper presents a case study at School of Electronics and Communication, KLE-Tech which facilitated in preparing students ready for VLSI industry by bridging the gap between industry and institute. Collaboration between School of Electronics and Communication and Sankalp Semiconductors Pvt. Ltd., ventured as Prakalp program. In this program, the selection process of the interested students in the field of VLSI is through screening test. They are trained intensively by experts from industry and academia on fundamentals and advance courses of Analog and Mixed Signal VLSI to do the industry defined projects and experience research at the graduate level. Fundamental courses required for carrying out analog VLSI projects and research are covered as a part of professional core courses in the curriculum and to enhance this activity elective courses such as Analog Circuit Design followed by Physical Design-Analog are being conducted. Design, delivery and project based evaluation is by experts from Academia and Industry. Students are encouraged to submit their work to national conferences and contests. Sankalp and other VLSI companies recruit the best performing students

A low noise low power 45 nm technology based simultaneous switching noise (SSN) reduction model for mixed signal VLSI circuits

A low noise low power 45 nm technology based simultaneous switching noise (SSN) reduction model for mixed signal VLSI circuits

DL Prof. Pui-In Mak Gives a Technical Talk Hosted by imec in Leuven, Belgium [Chapters

The IEEE Solid-State Circuits Society (SSCS) Benelux Chapter organized a technical talk on 23 May 2017 given by Pui-In (Elvis) Mak, associate director of research and associate professor, State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, China. Mak is an SSCS Distinguished Lecturer (DL); the program is aimed at disseminating high-quality technical content to members at a local level. In his talk, "Ultra-Low-Power Radios Using Current-Reuse/Function- Reuse/Ultra-Low-Voltage Techniques," Mak discussed the work his research group is doing in Macau, where over 80 researchers focus on analog and mixed-signal ICs for wireless communications, data converters, biomedical and power electronics, and analytical chemistry. He then positioned his work compared to the state of the art on low-power radio transceivers, where his group targets 10x lower power than existing solutions, for comparable battery life times. In this light, he explored several techniques that led to numerous publications in the International Solid-State Circuits Conference as well as IEEE Journal of Solid-State Circuits.

Mixed-signal VLSI neural network based on Continuous Valued Number System

Mixed-signal neural networks have higher energy efficiency and lower area consumption when compared with their equivalent digital implementations. However, the signal processing precision in mixed-signal implementations is limited. A mixed-signal arithmetic method called Continuous Valued Number Systems (CVNS) is employed for development and implementation of different functions required in a neuronal network. Analog digits of this number system enable the higher accuracy of analog operations, and can efficiently relate with digital and binary values. In this paper, design and implementation of a 2-2-1 mixed-signal CVNS network structure is presented, to confirm the developed arithmetic method. In the proposed structure, weights are stored in the digital registers while the arithmetic is based on the CVNS. The CVNS features have been exploited to address the limited signal processing precision issue, which requires resolutions higher than 12-bit for online training of the network. As a result, the proposed structure satisfies this requirement of neural networks, while yielding an optimized network configuration. The proposed network is designed, fabricated, and tested in 0.18μm technology.

Micropower Mixed-signal VLSI Independent Component Analysis for Gradient Flow Acoustic Source Separation.

A parallel micro-power mixed-signal VLSI implementation of independent component analysis (ICA) with reconfigurable outer-product learning rules is presented. With the gradient sensing of the acoustic field over a miniature microphone array as a pre-processing method, the proposed ICA implementation can separate and localize up to 3 sources in mild reverberant environment. The ICA processor is implemented in 0.5 µm CMOS technology and occupies 3 mm × 3 mm area. At 16 kHz sampling rate, ASIC consumes 195 µW power from a 3 V supply. The outer-product implementation of natural gradient and Herault-Jutten ICA update rules demonstrates comparable performance to benchmark FastICA algorithm in ideal conditions and more robust performance in noisy and reverberant environment. Experiments demonstrate perceptually clear separation and precise localization over wide range of separation angles of two speech sources presented through speakers positioned at 1.5 m from the array on a conference room table. The presented ASIC leads to a extreme small form factor and low power consumption microsystem for source separation and localization required in applications like intelligent hearing aids and wireless distributed acoustic sensor arrays.

A Mixed-Signal VLSI System for Producing Temporally Adapting Intraspinal Microstimulation Patterns for Locomotion.

Neural pathways can be artificially activated through the use of electrical stimulation. For individuals with a spinal cord injury, intraspinal microstimulation, using electrical currents on the order of 125 μ A, can produce muscle contractions and joint torques in the lower extremities suitable for restoring walking. The work presented here demonstrates an integrated circuit implementing a state-based control strategy where sensory feedback and intrinsic feed forward control shape the stimulation waveforms produced on-chip. Fabricated in a 0.5 μ m process, the device was successfully used in vivo to produce walking movements in a model of spinal cord injury. This work represents progress towards an implantable solution to be used for restoring walking in individuals with spinal cord injuries.

Conceptual-level bio-inspired retinal design using analogue VLSI systems

One way to understand a neurobiological system is by building a simulacrum that replicates its behaviour in real time using similar constraints. Bionic eye helps visually impaired people. A neuromorphic system concepts and circuit design method involved is discussed in this paper. The mathematical model has been simulated and validated in MATLAB using artificial stimulus. A photoreceptors circuit realised and simulated using analogue mixed-signal VLSI behavioural modelling. The estimated parameters using the mathematical model are incorporated in behavioural model to describe neuromorphic retinal system topology and performance. The behavioural models hold up the signal flow correlation between input and outputs. A one-dimensional hardware photoreceptors circuit was constructed and the performance is studied under the steady state condition, tested with impulses or step input that simulates the physical dynamics of the biological system using VHDL-AMS which illustrate the specific features of system level design. Finale future scopes are also presented evidently.

FPGA Implementation of Sigma-Delta ADCUsing IC MCP3208

Analog-to-digital converters have many applications in our daily life. The Sigma-Delta converter is an attractive ADC for future communication systems due to its high number of bit rate. The aim of this project is to design of sigma-delta ADC and it is implemented using SPARTAN 3e FPGA.In this project sigma-delta conversion can be done by using the advanced IC MCP3208 and bit by bit transmission is done finally the output is displayed on monitor of pc.The main aim of this project is to power reduction and the converter is used to achieve 12-bit resolution. In MATLAB Simulink the converter done but greater filter delay in the output and it is not suitable for FPGA implementation. To overcome this problems sigma-delta conversion is done using the Xilinx ISE design tool 14.6 and the power comparison calculation is done. In its supply voltage 5v, analog input is taken as potentiometer, by varying the input voltage(12-bits)0-2^12 that means up to 4096 range, through rs232 cable, the output is displayed on monitor. The sigma-delta analog-to-digital converter is suitable for embedded FPGA applications. The sigma-delta architecture has become more and more popular realizing high-resolution ADCs in mixed-signal VLSI processes. This converter is inherently an oversampling converter, although sigma-delta converter is just one of the techniques contributing to the overall performance

A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses.

Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks, with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm2, and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities.

Mixed-signal VLSI independent component analyzer for hearing aid applications.

We present a mixed-signal architecture for implementation of independent component analysis designed for the task of blind source separation of acoustic sources interfacing miniature microphone array. The matrix-vector multiplication is implemented through integration of switched current sources controlled by the pulse-width modulated signals. The proposed architecture implementing 3×3 static ICA in 0.5μm CMOS technology occupies chip area of 0.49 mm(2) with the power consumption of 80μW at 5 V supply voltage.

Development of Ni-Zn Ferrite Based Smart Humidity Sensor Module by Using Mixed Signal Programmable System-on-Chip

Synthesis of materials for sensor and development of smart sensor module, of promising characteristics, large adoptability and great portability, plays significant role in designing of sophisticated instrumentation. Therefore, based on an innovative technology, analogue and mixed signal VLSI design, a smart humidity sensor module is designed and presented in this paper. The composition of nano sized Nickel-Zinc ferrites are synthesised by co-precipitation and formation of single phase spinel ferrites are confirmed by X-powder diffraction. The inter-digitated sensor is fabricated by screen printing technique and implemented for sensor module development. The electrical resistance (R), measured against humidity shows exponential decrease with increase in the humidity (RH %) and supports the photonic conductivity. This nature of the sensor is considered for designing of sensor module. A programmable System on-chip, Cypress PSoC, emphasizes mixed signal VLSI technology. The sensor under investigation is interfaced to the cypress PSoC. On reconfiguring the analogue as well as digital parts a system on chip is designed. The system is calibrated to RH%. Actually, the sensor materials are exhibiting semiconductor nature. The exponential behaviour of the sensor material is linearised by deploying the features of the firmware. The present sensor module is showing humidity reading in RH% with great accuracy. It also provides linear response during humidity 30 RH% to 95 RH%. This low cost and high reliable sensor could be utilized for monitoring relative humidity different environment.

Spike-Timing-Dependent Plasticity With Weight Dependence Evoked From Physical Constraints

Analogue and mixed-signal VLSI implementations of Spike-Timing-Dependent Plasticity (STDP) are reviewed. A circuit is presented with a compact implementation of STDP suitable for parallel integration in large synaptic arrays. In contrast to previously published circuits, it uses the limitations of the silicon substrate to achieve various forms and degrees of weight dependence of STDP. It also uses reverse-biased transistors to reduce leakage from a capacitance representing weight. Chip results are presented showing: various ways in which the learning rule may be shaped; how synaptic weights may retain some indication of their learned values over periods of minutes; and how distributions of weights for synapses convergent on single neurons may shift between more or less extreme bimodality according to the strength of correlational cues in their inputs.

High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity

Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices.

Computing based on the physics of nano devices—A beyond-CMOS approach to human-like intelligent systems

This paper proposes a new computing architecture to build human-like intelligent systems by best utilizing the physics of nano devices, or more specifically, the exotic current–voltage characteristics of nano-functional devices. The resonance characteristics arising from quantum effects in nano-scale devices are utilized as computing primitives of correlation and employed in building brain-mimicking VLSI systems. A number of subconscious processing taking place in our brains including early visual processing will be implemented in fine-grain parallel processing architectures using nano devices. In order to demonstrate the concept, the resonance characteristics of nano devices have been emulated by simple MOS bump circuitries, and real working proof-of-concept chips have been developed. Image recognition algorithms specifically developed for such brain mimicking systems are described, and the experimental results obtained form the measurement of analog, digital and mixed-signal VLSI chips as well as from computer simulations are presented as illustrative examples. In the last part of this paper, a perspective to the future is presented as a summary.

Hybrid System Approach to On-Line Testing of Mixed Signal VLSI Circuits: A Case Study of DC-DC Buck Converters

This work is concerned with the development of a method for the design of Mixed Signal VLSI circuits with on line testing capability. A novel theory of Fault Detection and Diagnosis of Hybrid Systems has been applied for the on-line detection of catastrophic stuck-at faults in mixed VLSI circuits. Based on this an FPGA based system has been developed to design a DC-DC buck converter with on-line testing capability. To the best of our knowledge the proposed methodology is one of the first attempts to provide a solution for On-Line Testing of mixed signal VLSI circuits using a formal theory, which is applicable to a very large class of low frequency analog circuits.

480-GMACS/mW Resonant Adiabatic Mixed-Signal Processor Array for Charge-Based Pattern Recognition

A resonant adiabatic mixed-signal VLSI array delivers 480 GMACS (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> multiply-and-accumulates per second) throughput for every mW of power, a 25-fold improvement over the energy efficiency obtained when resonant clock generator and line drivers are replaced with static CMOS drivers. Losses in resonant clock generation are minimized by activating switches between the LC tank and DC supply with a periodic pulse signal, and by minimizing the variability of the capacitive load to maintain resonance. We show that minimum energy is attained for relatively wide pulse width, and that typical load distribution in template-based charge-mode computation implies almost constant capacitive load. The resonantly driven 256 times 512 array of 3-T charge-conserving multiply-accumulate cells is embedded in a template matching processor for image classification and validated in a face detection task.

A Multichip Neuromorphic System for Spike-Based Visual Information Processing

We present a multichip, mixed-signal VLSI system for spike-based vision processing. The system consists of an 80 x 60 pixel neuromorphic retina and a 4800 neuron silicon cortex with 4,194,304 synapses. Its functionality is illustrated with experimental data on multiple components of an attention-based hierarchical model of cortical object recognition, including feature coding, salience detection, and foveation. This model exploits arbitrary and reconfigurable connectivity between cells in the multichip architecture, achieved by asynchronously routing neural spike events within and between chips according to a memory-based look-up table. Synaptic parameters, including conductance and reversal potential, are also stored in memory and are used to dynamically configure synapse circuits within the silicon neurons.

Mixed-signal neuron-synapse implementation for large-scale neural network

This paper describes a mixed-signal neural networks VLSI for low power and asynchronous operation. The voltage-controlled transconductance produces the synaptic function of multiplication and summation of synaptic currents for neuron, by compensating the non-linearity of MOSFET resistance in the triode region. The flexible configuration of synapse accommodates the spike-based neural networks, inspired by the biological plausibility and low power requirement. The neuron with a combination of synapses demonstrates asynchronous spikes of integration-and-firing with a refractory period. The speed of individual synapse is simulated up to 300 Mega operations/s with the power consumption of less than 33 μW, using 0.18 μm CMOS.