Mixed-mode Device Simulation Research Articles

Effects of Pillar Conditions on DC/AC Characteristics of Tunnel Field-effect Transistor with Vertical Structures

To investigate the effects of various pillar conditions such as pillar thickness (T<SUB>pillar</SUB>), pillar height (T<SUB>Si</SUB>), and doping concentration of pillar on DC characteristics of TFETs with vertical structures (TFET<SUB>VS</SUB>) and AC switching characteristics of TFET<SUB>VS</SUB> inverters, Mixed-mode device and circuit TCAD simulations are performed. As 1) the T<SUB>pillar</SUB> is thicker, 2) the T<SUB>Si</SUB> is increased, and 3) the doping concentration of the pillar is reduced, the tunneling current between source and channel gets increased and the gate-to-drain capacitance (C<SUB>GD</SUB>)-gate voltage (V<SUB>G</SUB>) curve becomes positive-shifted due to the weaker controllability of V<SUB>G</SUB> on the drain-side channel. Through the transient responses of TFET<SUB>VS</SUB> inverters with various pillar conditions, it is revealed that AC switching performance can be improved by the enhanced tunneling current and the positive-shifted C<SUB>GD</SUB>-V<SUB>G</SUB> curve caused by the weaker V<SUB>G</SUB> controllability on the drain-side channel.

Effective Drive Current for Near-Threshold CMOS Circuits’ Performance Evaluation: Modeling to Circuit Design Techniques

This paper presents an effective current model ( ${I}_{\textsf {eff}}$ ) for a near-threshold voltage (NTV) inverter and two-input NAND/NOR gates. The proposed model is validated by 2-D technology computer-aided design mixed-mode device simulations and HSPICE simulations at two different technology nodes. When compared with our model, the existing nominal supply voltage ${I}_{\textsf {eff}}$ models fail to estimate an inverter/NAND/NOR gate performance in the NTV regime. The proposed model is also validated for process, voltage, and temperature variations. Performance variation due to layout-dependent effects (LDEs) and inverse narrow width effect (INWE) are significant in the NTV regime. Therefore, the model is validated while considering LDEs. We show that due to LDEs and INWE, the value of ${I}_{\textsf {eff}}$ per unit width is a function of the device width and the number of fingers. To account for this effect, a systematic methodology is presented to optimize a circuit performance in the NTV domain. An inverter chain with ${C}_{\textsf {out}}/{C}_{\textsf {in}}=\textsf {2000}$ designed employing our methodology results in 3.2%, 35%, and 30% improvement in the delay, energy per operation, and total transistor width, respectively, as compared with existing methodologies. Similarly, data paths resized using the proposed methodology result in a significant performance improvement when compared with their conventionally designed counterparts.

Effects of Localized Body Doping on Switching Characteristics of Tunnel FET Inverters With Vertical Structures

In order to verify the effects of localized body doping (LBD) on alternating current switching performances of tunnel FETs (TFETs) with vertical structures, The TFET inverter composed of n-/p-type TFET with the localized p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> body doping is simulated with the help of mixed-mode device and circuit simulations. As a result, falling/rising delay is significantly improved due to the locally high channel-to-drain side energy barrier induced by the LBD. Furthermore, LBD conditions, such as doping concentration, depth, and width, are optimized to maximize the improvement of falling/rising delay. Based on the optimization results, it is found that enough wide doping width and deep depth are inevitable to minimize the drain voltage (VD)-induced lowering of the locally increased barrier and the increase of ambipolar current and too wide doping width cannot be applied due to the ON-current reduction caused by the degraded controllability of gate voltage on channel similarly to short channel effects. Moreover, the doping width and depth should be adjusted according to LBD concentration.

Effects of drain doping concentration on switching characteristics of tunnel field-effect transistor inverters

In order to investigate the effects of the modulation of drain doping concentration (Ndrain) on alternating current (AC) switching characteristics of a tunnel filed-effect transistor (TFET) inverter, the characteristics of TFETs with various Ndrains are analyzed rigorously through mixed-mode device and circuit TCAD simulations. As the Ndrain gets decreased, the drain current (ID) becomes reduced and the gate-to-drain capacitance (CGD) reflects the entire gate capacitance (CGG) at a lower gate voltage (VG), which leads to the degradation of falling/rising delay in TFET inverters. These phenomena are explained successfully by the change of quasi-Fermi energy in the drain (EF_drain) as a function of VG. The EF_drain rises dramatically from when tunneling current starts to flow from the source in the n-type TFET with low Ndrain. As a result, drain-side channel inversion occurs at a lower VG due to the reduction of the energy barrier between the EF_drain and the conduction band edge of the channel.

Physically Based Predictive Model for Single Event Transients in CMOS Gates

An analytical model is presented to understand the time response of an inverter to ionizing particles based on physical equations. The model divides the output voltage transient response of an inverter into three time segments, where an ionizing particle striking through the drain–body junction of the OFF-state nMOS is represented as a photocurrent pulse. If this current source is large enough, the output voltage can drop to a negative voltage. In this model, the OFF-state nMOS is represented as the parallel combination of an ideal diode and the intrinsic capacitance of the drain–body junction, while a resistance represents an ON-state pMOS. The proposed model is verified by 3-D TCAD mixed-mode device simulations. In order to investigate the flexibility of the model, the effects of important parameters, such as ON-state pMOS resistance, doping concentration of P-region in the diode, and the photocurrent pulse are scrutinized.

Effect of Metal Gate Granularity Induced Random Fluctuations on Si Gate-All-Around Nanowire MOSFET 6-T SRAM Cell Stability

In this paper, we present a variability-aware 3-D mixed-mode device simulation study of Si gate-all-around (GAA) nanowire mosfet (NWFET)-based 6-T static random access memory (SRAM) bit-cell stability and performance considering metal-gate granularity (MGG) induced intrinsic device random fluctuations and quantum corrected room temperature drift-diffusion transport. The impact of MGG contributed intrinsic variability on Si GAA n- and p-NWFETs-based SRAM cell static noise margins (SNM), write and read delay time are statistically analyzed. Our statistical simulations predict acceptable stability for the Si NWFET 6-T SRAM cell with $V_{{\rm DD}}$ downscaling up to 0.5 V. The simulation estimated mean hold SNM values follow a lowering trend with $V_{{\rm DD}}$ downscaling, similar to the hold SNM experimental data reported in the literature for Si GAA NWFET-based SRAM arrays. We further show a linear variation in statistical variance of hold SNM with gate metal grain size and work function.

Conceptual Study of Sub-600 V IGBTs

Very low voltage, 60–600 V insulated-gate bipolar transistors (IGBTs) were compared to power mosfet s with conventional and superjunction drift layers of identical voltage classes using mixed-mode numerical device simulation. This study was done in the light of forthcoming 400 V class IGBTs for use in electric vehicle/hybrid electric vehicle: the 600 V borderline, which previously separated the bulk of power mosfet from IGBT applications, has become fragile recently. We find that the 400 V class must not represent a lower limit for IGBTs based on silicon: in fact, LV IGBTs could offer lower losses down to the 60–100 V level. Most importantly, low-voltage IGBTs may outperform power mosfet s not only with respect to on-state voltage drop but also regarding switching offering up to 30% lower turn-off losses. This paper presents physics-based arguments focusing on the device transconductance to augment these projections. LV IGBTs or hybrid devices (monolithic integration of mosfet plus IGBT) could become lower cost, high performance alternatives to SJ power mosfet s thanks to short development cycles common in mature silicon technologies.

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction

We propose an efficient physics-based mixed-mode statistical simulation methodology for nanoscale devices and circuits. Here, 3-D Technology Computer Aided Design models pose a barrier for efficient simulation of variability as they generally involve millions of nodes in their mesh representations. The proposed methodology, which has been implemented for FinFET/tri-gate static random access memory (SRAM) design, overcomes this barrier by leveraging advanced physics-based 2-D (P2-D) devices with optimized meshes that are derived from 3-D FinFET models with tuned device parasitics. This enables physics-based simulation as well as physics-based variability input parameters. To improve accuracy, an embedded automated flow enables extraction of all external nodal parasitics, directly from a 3-D FinFET circuit layout representation. The circuits consisting of advanced P2-D devices are then back annotated with the nodal parasitics to enable fast and accurate SRAM dynamic margin mixed-mode simulations. Results demonstrate up to 200× speedup compared with traditional 3-D device simulations, and around five orders of magnitude wall clock time improvement on account of fast statistical methodologies, which are superior in comparison with traditional Monte Carlo analysis. This makes it feasible to supplant often inaccurate compact model-based simulations by true mixed-mode device simulations in statistical engines. The proposed physics-based methodology is also shown to corroborate well with hardware measurements.

A Simulation Study of Colpitts Oscillator Reliability and Variability

Nanoscale CMOS reliability and process variation effect on the LC Colpitts oscillator has been examined. Mixed-mode device and circuit simulation is used to investigate the physical insight of impact ionization to the Colpitts oscillator. An analytical equation of phase noise as a function of offset frequency, transistor parameters, and body bias has been derived. The analytical predictions are in good agreement with ADS simulation results. An adaptive body bias to minimize process variation effect on the Colpitts oscillator has also been proposed. The adaptive body bias technique effectively reduces the hot electron effect and process variability on the Colpitts oscillator performance, as supported by Monte Carlo simulation results.

A novel superjunction MOSFET with improved ruggedness under unclamped inductive switching

The ruggedness of a superjunction metal—oxide semiconductor field-effect transistor (MOSFET) under unclamped inductive switching conditions is improved by optimizing the avalanche current path. Inserting a P-island with relatively high doping concentration into the P-column, the avalanche breakdown point is localized. In addition, a trench type P+ contact is designed to shorten the current path. As a consequence, the avalanche current path is located away from the N+ source/P-body junction and the activation of the parasitic transistor can be effectively avoided. To verify the proposed structural mechanism, a two-dimensional (2D) numerical simulation is performed to describe its static and on-state avalanche behaviours, and a method of mixed-mode device and circuit simulation is used to predict its performances under realistic unclamped inductive switching. Simulation shows that the proposed structure can endure a remarkably higher avalanche energy compared with a conventional superjunction MOSFET.

Analysis of Dynamic Avalanche Phenomenon in SOI Lateral High-speed Diode during Reverse Recovery and Development of a Novel Device Structure for Suppressing Dynamic Avalanche

We have studied the dynamic avalanche phenomenon in an SOI lateral diode during reverse recovery by using a mixed-mode device simulation. In the study, it has been found that local impact ionization occurs near an anode-side field oxide edge, where a high-density hole current flows and a high electric field appears simultaneously. We propose that a p-type anode extension region (AER) along a trench side wall effectively sweeps out stored carriers beneath an anode p-diffusion layer during reverse recovery, resulting in reduction of the electric field and remarkable suppression of the dynamic avalanche. The AER reduces the total recovery charge and does not cause any increase in the total stored charge under a forward bias operation. This effect is verified experimentally by the fabricated device with AER. Thus, the developed SOI lateral diode is promising as a high-speed and highly rugged free-wheeling diode, which can be integrated into next-generation SOI microinverters.

Adaptive Gate Bias for Power Amplifier Temperature Compensation

Mixed-mode device and circuit simulation is used to examine device self-heating during power amplifier (PA) transient response. Lattice temperature increases with time and eventually saturates beyond the thermal time constant. Temperature variation on the effect of PA performances has been modeled and analyzed. Different gate biasing schemes that reduce the temperature drift of PA output power and power-added efficiency are evaluated. A simple adaptive gate bias technique effectively provides temperature compensation of PA performances over a wide range of temperatures.

Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Results

Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in the processing level or the adoption of a more variation tolerant process flow, device architecture, or design on circuit or chip level. Five Fraunhofer institutes joined forces to address these issues. Their own software tools, e.g., for lithography/topography simulation, mixed-mode device simulation, compact model extraction, and behavioral modeling, have been combined with commercial tools to establish a hierarchical system of simulators in order to analyze process variations from their source, e.g., in a lithography step, through device fabrication up to the circuit and system levels.

Mixed Mode Modeling and Characterization of a 4H-SiC Power DMOSFET Based DC-DC Power Converter

We present detailed mixed-mode simulations of a DC-DC converter based on 4H-SiC DMOSFETs. The mixed-mode modeling enables the use of complex physics based models for the interface trap occupation and surface mobility that are typical for 4H-SiC devices, and apply them to a practical circuit application such as a DC-DC boost converter. The mixed mode simulations are performed for a reduced DC-DC converter circuit to evaluate the performance of the DMOSFET when it has an inductive load. The current inside the device and its power dissipation during switching are evaluated numerically. Further, the mixed-mode device simulation shows that the majority carriers (electrons) inside the 4H-SiC DMOSFET require a finite time to go from the ON (strongly inverted) to the OFF (depleted) state, thereby causing power dissipation and heating during the turn-off period. The peak power is dissipated in the JFET region of the device which indicates that maximum heat and therefore maximum temperature may be generated there.

Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Through mixed-mode device and circuit simulation, this paper provides an estimate of the effective output capacitance <formula formulatype="inline"><tex Notation="TeX">$(C_{\rm EFF})$</tex></formula> and drive current <formula formulatype="inline"><tex Notation="TeX">$(I_{\rm EFF})$</tex></formula> for delay (<formula formulatype="inline"><tex Notation="TeX">$ \tau_{f} = \hbox{0.69} R_{\rm sw}C_{\rm EFF}$</tex></formula>, where <formula formulatype="inline"><tex Notation="TeX">$R_{\rm sw} = V_{\rm DD}/\hbox{2}\ I_{\rm EFF}$</tex></formula>) estimation of unloaded tunnel field-effect transistor (TFET) inverters. It is shown that unlike MOSFET inverters, where <formula formulatype="inline"><tex Notation="TeX">$C_{\rm EFF}$</tex> </formula> is approximately equal to the gate capacitance <formula formulatype="inline"><tex Notation="TeX">$(C_{\rm gg})$</tex> </formula>, in TFET inverters, the output capacitance can be as high as 2.6 times the gate capacitance. A three-point model is proposed to extract the effective drive current from the real-time switching current trajectory in a TFET inverter. </para>

Low Reverse-Recovery Stress in High-Power Converters Achieved by Self-Resetting Saturable Cores

A clamp circuit using nonlinear reactors is proposed for use with high-power inverters. For stable inverter operation under all typical operation conditions, the cores have self-resetting characteristics by the introduction of an air gap. The circuit configurations are investigated using a 6-kA/6-kV gate commutated thyristor (GCT) chopper. The results are compared to those of a traditional GCT clamp-snubber circuit using a linear anode reactor. New simulation models developed for the cores and diodes are tuned by the experimental results and applied to investigate two- and three-level circuits. Using self-resetting saturable reactors, low freewheel-diode reverse-recovery stress is achieved with a very high value of di/dt . The benefits of the new circuit also are demonstrated by mixed-mode device simulation.

Feasibility Study of a Table-Based SET-Pulse Estimation in Logic Cells From Heavy-Ion-Induced Transient Currents Measured in a Single MOSFET

A table-based technique for estimating single-event transient pulses is evaluated in the most crucial case for bulk MOSFET technologies where an ion penetrates the drain region. A device model of a bulk MOSFET is built in a 2-D numerical device simulation framework, and heavy-ion-induced transient currents flowing through its drain terminal are calculated. From the currents, single-event transient voltage pulses in an inverter are estimated with the table-based estimation technique. The results are compared with ones simulated in the mixed mode with the same device model and circuit configuration. The estimated pulses are comparable to the results in the mixed-mode device simulations. Moreover, the estimation accuracy can be improved by using a drain-capacitance compensation technique. An extrapolation technique based on the drain-voltage dependency of heavy-ion-induced transient currents is also presented to reduce the experimental costs for modeling.

Estimation of Single Event Transient Voltage Pulses in VLSI Circuits From Heavy-Ion-Induced Transient Currents Measured in a Single MOSFET

Described is an estimation technique of single event transient voltage pulses in VLSI circuits from heavy-ion-induced transient currents measured in a single MOSFET. Waveforms of the transient voltage pulses are fully estimated by using transient current data obtained in various drain voltage conditions. Modeling of the irradiated device behavior for use in device/circuit simulations is not required. The concept is validated using a 2-D mixed-mode device simulation.

Fully coupled electrothermal mixed-mode device simulation of SiGe HBT circuits

It is well known that for the design and simulation of state-of-the-art circuits thermal effects like self-heating and coupling between individual devices must be taken into account. As compact models for modern or experimental devices are not readily available, a mixed-mode device simulator capable of thermal simulation is a valuable source of information, Considering self-heating and coupling effects results in a very complex equation system which can only be solved using sophisticated techniques. We present a fully coupled electrothermal mixed-mode simulation of an SiGe HBT circuit using the design of the /spl mu/A709 operational amplifier. By investigating the influence of self-heating effects on the device behavior we demonstrate that the consideration of a simple power dissipation model instead of the lattice heat flow equation is a very good approximation of the more computation time consuming solution of the lattice heat flow equation.

Clock buffer circuit soft errors in antifuse-based field programmable gate arrays

Three-dimensional mixed-mode device simulation is used to investigate the clock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned with improved SEU hardness. The threshold LET of each version was simulated both at static and during transition. Compared to the test data, the simulated results consistently underestimate the LET/sub th/. The difference between LET/sub th/ at static and during transition is relatively small. This disagrees with the previous speculation that the clock upset is due to heavy-ion strikes very close to the clock edge. Efforts were also made to optimize the simulation methodology to reduce the simulation time for practicality.