Mixed-mode Circuit Simulation Research Articles

Air-spacers as analog-performance booster for 5 nm-node N-channel nanosheet transistor

This work investigates the use of air-spacers as an analog-performance booster for nanosheet transistors (NSTs) at 5 nm node. The NSTs with air-spacers are evaluated across the design space for analog circuits. A fully calibrated three-dimensional technology computer-aided design platform was used for the device and mixed-mode circuit simulations. The use of air-spacers improves the output impedance (r o) from 974 kΩ to 1.32 MΩ, as well as the intrinsic gain (A v) from 90 to 118, for the NST with L g/W g = 240 nm/15 nm. The air-spacers also improve analog performance parameters such as the unit-gain frequency (f T) from 562 to 596 GHz; gain-frequency product from 4.76 to 5 THz; transconductance-frequency product from 2.11 to 2.22 THz; and the gain-transconductance-frequency product from 17.9 to 18.7 THz; for the NST with L g/W g value of 12 nm/15 nm. In addition, the discharge time (t d) also improves from 1.64 to 1.5 ns, for NST with L g/W g = 12 nm/120 nm. The oscillation frequency of a three-stage ring-oscillator is also reported to improve from 68.3 to 88.2 GHz by the use of air-spacers.

On the logic performance of bulk junctionless FinFETs

In this paper, a one-to-one comparison of the logic performance is made between CMOS circuits built with bulk junctionless (JL) FinFETs and that with SOI JL FinFETs for three different technology nodes as per the ITRS roadmap. For such comparison: (i) the rise time and fall time are evaluated from the transient analysis of a CMOS inverter,(ii) the propagation delay per stage for a three-stage ring oscillator is estimated from its frequency of oscillation, and (iii) the static noise margin of a 6 T SRAM cell is evaluated from its butterfly plot. A three-dimensional numerical device and mixed-mode circuit simulator is used for the performance estimation. CMOS circuits implemented with bulk JL devices are found to have comparable logic performance with their SOI JL counterparts.

Performance of Ge p-channel junctionless FinFETs for logic applications

In this paper, we report an investigation of the performance of a Ge junctionless (JL) p-FinFET and compare it with that of a Si JL p-FinFET for logic applications. CMOS inverters are built with such Ge p-FinFETs and Si n-FinFETs for three different technology nodes as per the ITRS roadmap. Transient analysis of CMOS inverters is made to evaluate the logic performance parameters such as rise time and fall time. Then, mixed-mode circuit simulations are performed for a three-stage ring oscillator, build with such CMOS inverters, to evaluate frequency of oscillation and propagation delay. Our investigations reveal that CMOS circuits built with Ge JL p-FinFETs outperform their equally sized all Si counterpart. Reduction of ~ 70% in the rise time for the CMOS inverters and improvement of more than 75% in the frequency of oscillation for the ring oscillators are observed for all three technology nodes when Ge p-channel devices are used.

Study of circuit performance and non quasi static effect in germanium tunnel FET for different temperatures

Recent days, for low power applications, germanium (Ge) is considered to be a good alternative of Silicon (Si) as channel material for TFETs to boost the on current. This study reports on the reliability of Ge-pTFET in presence of temperature variability. The reliability is studied through comparative analysis of Analog and Small-signal parameters. The variation in lattice temperature is a crucial issue for reliability of any device since it modulates the band gap narrowing at the tunneling junctions and hence tunneling characteristics of the device. In this work, the impact of temperature variation is systematically analyzed in Ge-pTFET in terms of Non-Quasi-static small-signal-model parameters along with Analog Figure-of-Merits. Also, linearity performance is investigated by means of IIP3 and 1-dB compression point for the variation of temperature, ranges from 200 K to 400 K. Finally, the impact of temperature variation is analyzed in mixed mode circuit simulations for the applications of cascode amplifier circuit and common source amplifier circuit.

Parameter Extraction and Power/Performance Analysis of Monolithic 3-D Inverter (M3INV)

An equivalent circuit model of monolithic 3-D inverter (M3INV) considering the electrical coupling between the stacked metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed. We conduct the parameter extraction with technology computer-aided design (TCAD) simulations, where LETI-UTSOI model in HSPICE is used for the bottom PFET and the top NFETs. Their parameters are extracted by fitting their current–voltage (for dc analysis) and capacitance–voltage (for transient ac analysis) characteristics. The parameters extracted from the LETI-UTSOI model contain the electrical coupling at the gate of the bottom MOSFET. In order to extract external capacitances such as monolithic intertier via (MIV)-to-MIV and MIV-to-contact in M3INV, we use two structures, the first that contains MIVs and metal lines and the second that does not. We observe that the dc and transient characteristics of M3INVs built using our extracted parameters match the TCAD mixed-mode circuit simulation results considerably well. Finally, we build and analyze ring oscillators using our M3INV to demonstrate the coupling impact on power and performance.

Electrically Driven Insulator–Metal Transition-Based Devices—Part I: The Electrothermal Model and Experimental Analysis for the DC Characteristics

We present a device model for the electrically driven insulator-to-metal transition (E-IMT) that captures the essential physics in E-IMT and can be used for physical device simulations and mixed-mode simulations of circuits containing IMT elements. Aspects of the model include the temperature-dependent resistivity, Joule heating, heat transport, and the spatial and dynamic coupling of the above phenomenon. We show that the model captures the dc and transient characteristics as measured by experiments. The model points out the existence of two critical transition voltages (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) under bidirectional sweep, the physical origin of this hysteresis, and correctly predicts the scaling of the critical voltage for transition V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> with the device size. The models' effectiveness as a basis for developing a mixed-mode circuit simulator is shown via comparison with experimental data for a steep-swing hybrid-field-effect transistor.

Investigation of metal-gate work-function variability in FinFET structures and implications for SRAM cell design

In sub-20 nm CMOS technology nodes, the parameter variability has become a main hurdle during the scaling of devices. Recently, the use of metal gate stacks in nano-scale FinFET structure has a significant impact on the intrinsic parameter fluctuations due to the granular nature of metals. A 14 nm FinFET structure has been considered to study the impact of metal-gate work-function variability by using the 3-D device and mixed mode circuit simulation. The present work investigates the impact of work function variability (WFV) on electrical characteristics of various possible FinFET architectures followed by the regression model. Further, the investigation has been extended to study the stability performance of 6-T SRAM cell under the influence of WFV. It is observed that work function variation may result in considerable performance degradation in device as well as SRAM operation in nano domain.

Analytical modeling of subthreshold characteristics of ion-implanted symmetric double gate junctionless field effect transistors

This paper reports a 2D analytical model for the subthreshold current and subthreshold swing (SS) of ion-implanted Double-Gate Junctionless Field Effect Transistors (DG-JLFETs) with a vertical Gaussian-like doping profile. The effects of gate length, straggle parameter, oxide thickness, channel thickness, and peak doping concentration on subthreshold current and subthreshold swing have been demonstrated. The model results are validated with the simulation data obtained by 2-D TCAD ATLASTM device simulator. Finally, the performance of a CMOS inverter using the DG-JLFET device has been investigated through ATLASTM TCAD mixed mode circuit simulations.

Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology

The device and circuit performance of a 20-nm gate length InGaAs and Ge hybrid CMOS based on an implant free quantum well (QW) device architecture is studied using a multiscale approach combining ensemble Monte Carlo simulation, drift-diffusion simulation, compact modeling, and TCAD mixed-mode circuit simulation. We have found that the QW and doped substrate, used in the hybrid CMOS, help to reduce short-channel effects by enhancing carrier confinement. The QW also reduces the destructive impact of a low density of states in III–V materials. In addition, the calculated access resistance is found to be a much lower than in Si counterparts thanks to a heavily doped overgrowth source/drain contact. We predict an overall low gate capacitance and a large drive current when compared with Si-CMOS that leads to a significant reduction in a circuit propagation time delay ( ${\sim }5.5$ ps).

Exploration of Si/Ge Tunnel FET Bit Cells for Ultra-low Power Embedded Memory

Ultra-low-power embedded memory is emerging as a key challenge to design systems with stringent energy but relaxed performance constraints like various wireless sensors and Internet-of-Things (IoT) devices. This paper explores the potential of Si/Ge tunnel FETs (TFET) in designing ultra-low power embedded memory bit cells, namely, Static Random Access Memory (SRAM) and embedded Dynamic RAM (eDRAM). A Technology CAD (TCAD)-based model of 22-nm Si/Ge TFET is designed and coupled with mixed-mode circuit simulation. The circuit-level analysis is performed to study the standby power, performance, and robustness characteristics of TFET SRAM and eDRAM. The results are compared with 22 nm FinFET-based design. The analysis shows that at higher performance targets, TFET-based embedded memory consumes higher standby energy; however, the energy-efficiency of TFET is much better when compared at reduced performance targets. Moreover, it is observed that the cell and array level circuit design strategies that exploit unique TFET properties can help improve robustness at low power regimes.

Self-Boosted Tunnel Field-Effect Transistor Using Nitride Charge Trapping Layer for Low Supply Voltage Operation.

Tunneling field-effect transistors (TFETs) have been studied as a candidate for low-power device due to the remarkable subthreshold characteristics. However, digital circuits composed of TFET have significantly large propagation delay compared with the conventional MOSFET circuits because of small current drivability and large gate-to-drain capacitance. In this work, the electrical characteristics of the self-boosted TFETs with nitride charge trapping layer have been studied using TCAD simulations. Trapped charges in the nitride layer improve subthreshold characteristics and on-current (I(ON)) of both nTFET and pTFET during gate bias sweep. In addition, the benefits of the self-boosted TFET devices to low supply voltage system application are investigated. Energy consumption and propagation delay of both conventional and self-boosted TFET inverters are compared by the mixed-mode circuit simulation study. Energy consumption is almost same but the propagation delay of the self-boosted TFET inverter is reduced especially for ultra-low voltage operation where system delay is increased dramatically.

Electrical Coupling of Monolithic 3-D Inverters

In this brief, we investigate the electrical coupling between stacked field-effect transistors (FETs) in monolithic 3-D inverters (M3INVs). We study the range of interlayer dielectric (ILD) thickness ( $T_{\text {ILD}}$ ) and channel length $L_{g}$ values that lead to a strong coupling between stacked FETs. Our device simulations show that M3INVs with $T_{\text {ILD}} \geq 50$ nm lead to negligible interaction between the stacked FETs. In addition, our 3-D mixed-mode circuit simulations show that the switching threshold voltages, propagation delays, and fall times of M3INVs with $T_{\text {ILD}} nm are significantly affected by other tiers. This means that new circuit simulation techniques that consider the electrical coupling between the stacked devices are required in monolithic 3-D integrated circuits.

Compact Design of Low Power Standard Ternary Inverter Based on OFF-State Current Mechanism Using Nano-CMOS Technology

We propose a novel standard ternary inverter (STI) based on nanoscale CMOS technology for a compact design of multivalued logic. Using the gate bias independent OFF-state mechanisms of junction band-to-band tunneling (BTBT), tristate STI operation has been demonstrated in the conventional binary CMOS inverter by TCAD device and mixed-mode circuit simulation with 32-nm high- $\kappa $ /metal-gate technology. Through analytical device modeling on BTBT and subthreshold current, static noise margin (SNM), off-leakage variation (OLV), and operation voltage ( $V_{\mathrm {DD}})$ scaling limits of STI have been investigated. The typical SNM is 200 mV and the variability of the intermediate level ( $\Delta V_{\mathrm {OM}}\sim 50$ mV) from OLV can be allowable into the worst SNM (>100 mV) of STI operation at $V_{\mathrm {DD}}= 1$ V. Exponentially reduced BTBT off-leakage around minimum $V_{\mathrm {DD}}\sim 0.1$ V is promising for ultimate low-power application of our STI.

Mixed-Mode Analysis of Different Mode Silicon Nanowire Transistors-Based Inverter

In this paper, we focused on the comparison and analysis of the performance of inversion-mode (IM), accumulation-mode (AM), and junctionless (JL) silicon nanowire field-effect transistors (NWTs)-based inverter. The effects of the radius, equivalent oxide thickness and source/drain doping in the different mode nanowire device structure are investigated. The capacitance components and transient characteristics, which determine the behavior of devices in the circuits, are studied and compared among different mode nanowire devices. The mixed-mode circuit simulations have been performed for the inverter circuit and three-stage ring oscillator consist of n-type and p-type IM/AM/JL NWTs. JL NWTs show lower Miller capacitance which contributes to suppressing the overshoot effect in the circuits. Results of these simulations can give insights into the in-circuit behavior of these future generation devices.

A Simulation Study of Colpitts Oscillator Reliability and Variability

Nanoscale CMOS reliability and process variation effect on the LC Colpitts oscillator has been examined. Mixed-mode device and circuit simulation is used to investigate the physical insight of impact ionization to the Colpitts oscillator. An analytical equation of phase noise as a function of offset frequency, transistor parameters, and body bias has been derived. The analytical predictions are in good agreement with ADS simulation results. An adaptive body bias to minimize process variation effect on the Colpitts oscillator has also been proposed. The adaptive body bias technique effectively reduces the hot electron effect and process variability on the Colpitts oscillator performance, as supported by Monte Carlo simulation results.

Establishing Best-Practice Modeling Approaches for Understanding Single-Event Transients in Gb/s SiGe Digital Logic

Single-event transient (SET) simulations of a Gb/s SiGe BiCMOS master/slave D flip-flop circuit are performed, employing both a decoupled current-injection SET modeling technique and a fully-coupled mixed-mode TCAD technique to model heavy-ion strikes to the storage and input cells. New insights are provided into the physical mechanisms underlying the single-event upset (SEU) sensitivity of high-speed SiGe digital latches and shift registers. A close analysis of the transient circuit behavior identifies the limitations of the current-injection approach in predicting SEU in fast SiGe digital logic. Furthermore, the physical ion track linear energy transfer (LET) is varied to establish the threshold LET for SEU using each simulation technique, further highlighting the SEU prediction error inherent to conventional decoupled modeling approaches. Finally, clocked mixed-mode circuit simulations are used to explain the fundamental SEU mechanisms and relate them to corresponding regions of the device-level SET.

Co-Integration of Nano-Scale Vertical- and Horizontal-Channel Metal-Oxide-Semiconductor Field-Effect Transistors for Low Power CMOS Technology

In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

Adaptive Gate Bias for Power Amplifier Temperature Compensation

Mixed-mode device and circuit simulation is used to examine device self-heating during power amplifier (PA) transient response. Lattice temperature increases with time and eventually saturates beyond the thermal time constant. Temperature variation on the effect of PA performances has been modeled and analyzed. Different gate biasing schemes that reduce the temperature drift of PA output power and power-added efficiency are evaluated. A simple adaptive gate bias technique effectively provides temperature compensation of PA performances over a wide range of temperatures.

Inter-band Tunnel Transistor Architecture using Narrow Gap Semiconductors

The inter-band tunnel transistor (TFET) architecture features a sub-kT/q sub-threshold slope operation and can potentially support high ION/IOFF ratios over small gate voltages. Based on two-dimensional numerical simulations, we investigate TFET in various material systems ranging from silicon to indium arsenide. TFET performance can be enhanced when heterojunctions are employed at the source side to enhance tunneling, nonequilibrium carrier population is maintained in the channel and one dimensional tunneling junction are incorporated. Mixed mode circuit simulations using TFETs highlight the impact of feed forward gate-to-drain capacitance in these devices during transient switching operation and reveal important differences with MOSFETs. Narrow gap semiconductors with low density of states are projected as viable candidates to implement TFET architecture in sustaining an aggressive supply voltage scaling roadmap for future digital logic applications

A Novel and Robust Approach for Common Mode Feedback Using IDDG FinFET

In this paper, we propose a novel and robust approach for common mode feedback (CMFB) for a differential amplifier using independently driven double gate (IDDG) FinFET technology. The performance of a differential amplifier with and without the proposed CMFB scheme is compared using 2-D mixed mode device and circuit simulations. It is shown from extensive simulation results that it is possible to achieve a common mode rejection ratio of 90 dB with improved performance in terms of area, power, and bandwidth even in the presence of process variations. Stability analysis shows that the proposed CMFB scheme does not need any compensating network. The idea is validated using extensive mixed-mode circuit simulations on IDDG FinFET circuits in sub-45-nm node technologies.