Mixed-criticality Real-time Systems Research Articles

Energy-Aware Nonpreemptive Scheduling of Mixed-Criticality Real-Time Task Systems

Energy-aware real-time scheduling for mixed-criticality (MC) systems with different criticality levels has drawn many researchers’ attentions. However, most of the studies focus on the preemptive MC task model and few studies consider the nonpreemptive MC task model, in which all jobs cannot be preempted until completion. In this article, we address the energy minimization problem for MC systems with nonpreemptive dynamic priority scheduling. First, we develop schedulability test of nonpreemptive earliest deadline first (NP-EDF) in single processor MC systems. Second, we extend the results to nonpreemptive earliest deadline first with virtual deadline (NP-EDFVD), which is the first attempt for nonpreemptive dynamic priority scheduling in single processor MC systems. Third, the energy-aware nonpreemptive scheduling algorithm (EANPS) based on NP-EDFVD is proposed to solve the energy minimization problem for MC systems with nonpreemptive dynamic priority scheduling. Finally, an industrial use-case and extensive simulations are used to validate the performance of the proposed algorithm, and the experimental results show that the EANPS algorithm consumes average 25.72% less energy than that of NP-EDFVD.

Energy aware algorithm based on actual utilization for periodic tasks in mixed-criticality real-time systems

Many real-time applications with different criticalities are integrated into a single mixed-criticality (MC) real-time system. Previous studies on MC systems assume that all tasks are executed in their worst case execution time and ignore the energy consumption in the high-criticality mode. In this paper, we focus on the actual execution time of tasks and consider the energy consumption in both the low-criticality mode and the high-criticality mode. First, we present a novel algorithm called EAU, which applies the actual execution time to re-compute the utilization of the task when a job is completed early or is released. In addition, it can apply the slack time generated from the early completion jobs and the jobs for which the processor speed is lower than the maximum processor speed in the high-criticality mode. Secondly, we analyze the scheduling feasibility of EAU. Finally, experiments are conducted to evaluate the performance of the proposed algorithm. The experimental results show that EAU can save up to 46.84% of energy compared with existing algorithms.

Reducing Dynamic Power Consumption in Mixed-Critical Real-Time Systems

In this paper, we study energy minimization consumption of a mixed criticality real-time system on uni-core. Our focus is on a new scheduling scheme to decrease the frequency level in order to conserve power. Since many systems are equipped with dynamic power and frequency level memory, power can be saved by decreasing the system frequency. In this paper, we provide new dynamic energy minimization consumption in mixed-criticality real-time systems. Recent research has been done on low-criticality mode for power reduction. Thus, the proposed scheme can reduce the energy both in high-criticality and low-criticality modes. The effectiveness of our proposed scheme in energy reduction is clearly shown through simulations results.

Commentary to: An exact schedulability test for fixed-priority preemptive mixed-criticality real-time systems

In this paper we point to some errors in recent paper by Asyaban et al. in which they devise an exact schedulability test. These errors are critical for the correct operation of the algorithm and they should be corrected.

Enhancing Real-Time and Determinacy for Network-Level Schedule in Distributed Mixed-Critical System

Time-triggered Ethernet (TTE) is designed as a deterministic real-time network for mixed-critical real-time systems, such as industrial automation, aerospace, and aviation. Due to asynchrony between tasks and the network in end systems (ESes), time-triggered (TT) messages have to spend uncertain time in waiting for being scheduled after they are generated. The waiting time uncertainly increases end to end delays for TT messages and will degrade the real-time and determinacy of TT messages sequentially. The contribution of this paper is to present a new architecture SDTTE to minimize the end to end delays, so as to enhance real-time and determinacy of TT messages. More specifically, a frame-based network model is built to describe distributed network resources. Under the network model, the end to end delay model with asynchrony between tasks and the network is analyzed. To match the generated time with the triggered time for TT messages, the triggered mechanism of the TT traffic in ESes is regarded as event strategy to detect the generated time of TT messages automatically. Based on this, the software defined TTE (SDTTE) is presented to optimize TT schedule online in switches. Furthermore, a simplified algorithm based on Satisfiability Modulo Theories (SMT) is proposed to satisfy real-time computing requirements. Finally, experiments with three network sizes verify the availability of SDTTE and analyze its performance. The results show that end to end delays for TT messages in SDTTE are decreased by about 95% compared with those in TTE. And the delays for rate-constrained and best-effort messages in SDTTE are almost as well as those in TTE. The processing time is less than 10s. In general, SDTTE provides a method to optimize end to end delays for TT messages in TTE, thus SDTTE has more determinacy and real-time than TTE. Meanwhile, SDTTE makes dynamic reconfiguration possible in practice.

A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems

This paper presents a novel design of a coprocessor that performs hardware-accelerated task scheduling for embedded real-time systems consisting of mixed-criticality real-time tasks. The proposed solution is based on the Robust Earliest Deadline (RED) algorithm and previously developed hardware architectures used for scheduling of real-time tasks. Thanks to the HW implementation of the scheduler in the form of a coprocessor, the scheduler operations (i.e., instructions) are always completed in two clock cycles regardless of the actual or even maximum task amount within the system. The proposed scheduler was verified using simplified version of UVM and applying billions of randomly generated instructions as inputs to the scheduler. Chip area costs are evaluated by synthesis for Intel FPGA Cyclone V and for 28-nm TSMC ASIC. Three versions of real-time task schedulers were compared: EDF-based scheduler designed for hard real-time tasks only, GED-based scheduler and the proposed RED-based scheduler, which is suitable for tasks of various criticalities. According to the synthesis results, the RED-based scheduler consumes LUTs and occupies larger chip area than the original EDF-based scheduler with equivalent parameters used. However, the RED-based scheduler handles variations of task execution times better, achieves higher CPU utilization and can be used for the scheduling of hard real-time, soft real-time and nonreal-time tasks combined in one system, which is not possible with the former algorithms.

Providing Integrity in Real-Time Networks-on-Chip

Mixed-critical real-time systems must meet strict integrity, resilience, and timing constraints, as specified by safety standards. Due to the increasing threat of random hardware faults, efficiently achieving high reliability and dependability calls for cross-layer fault-tolerance solutions. This paper introduces the Advanced Integrity Q-service (AIQ), a mechanism to ensure the integrity and predictability of on-chip communication under random hardware faults. Devised for cross-layer and hierarchical fault-tolerance solutions, AIQ realizes low-overhead error detection in hardware and delegates error handling to arbitrary strategies in software. Experimental evaluation featuring benchmark applications and an industrial avionics use case shows that AIQ operates with high reliability and availability and low hardware and performance overheads. In a many-core mixed-critical platform under expected real-time scenarios, AIQ performs with execution time overhead between 1.4% and 7.1%.

Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems

A Mixed Criticality System (MCS) combines real-time software tasks with different criticality levels. In a MCS, the criticality level specifies the level of assurance against system failure. For high-critical flows of messages, it is imperative to meet deadlines; otherwise, the whole system might fail, leading to catastrophic results, like loss of life or serious damage to the environment. In contrast, low-critical flows may tolerate some delays. Furthermore, in MCS, flow performances such as the Worst Case Communication Time (WCCT) may vary depending on the criticality level of the applications. Then execution platforms must provide different operating modes for applications with different levels of criticality. To conclude, in Network-On-Chip (NoC), sharing resources between communication flows can lead to unpredictable latencies and subsequently turns the implementation of MCS in many-core architectures challenging. In this article, we propose and evaluate a new NoC router to support MCS based on an accurate WCCT analysis for high-critical flows. The proposed router, called Double Arbiter and Switching router (DAS), jointly uses Wormhole and Store And Forward communication techniques for low- and high-critical flows, respectively. It ensures that high-critical flows meet their deadlines while maximizing the bandwidth remaining for the low-critical flows. We also propose a new method for high-critical communication time analysis, applied to Store And Forward switching mode with virtual channels. For low-critical flows communication time analysis, we adapt an existing wormhole communication time analysis with share policy to our context. The second contribution of this article is a multi-abstraction-level evaluation of DAS. We evaluate the communication time of flows, the system mode change, the cost, and four properties of DAS. Simulations with a cycle-accurate SystemC NoC simulator show that, with a 15% network use rate, the communication delay of high-critical flows is reduced by 80% while communication delay of low-critical flow is increased by 18% compared to solutions based on routers with multiple virtual channels. For 10% of network interferences, using system mode change, DAS reduces the high-critical communication delays about 66%. We synthesize our router with a 28nm SOI technology and show that the size overhead is limited of 2.5% compared to the solution based on virtual channel router. Finally, we applied model checking verification techniques to automatically prove several DAS properties required by critical systems designers.

Energy optimization of security-sensitive mixed-criticality applications for distributed real-time systems

Existing studies on mixed-criticality systems are usually safety-oriented, which seriously ignore the security and energy related requirements. In this paper we are interested in the design of security-sensitive mixed-criticality real-time systems. We first establish the system model to capture security-critical applications in mixed-criticality systems. Higher security-criticality protection always results in significant time and energy overhead in mixed-criticality systems. Thus, this paper proposes a system-level design framework for energy optimization of security-sensitive mixed-criticality system with hard real-time constraints. Since the time complexity of finding optimal solutions grows exponentially as problem size grows, a GA (Genetic Algorithm) based on efficient heuristic algorithm is devised to address the system-level optimization problem. Extensive experiments and a real-life case study have been conducted to show the efficiency of the proposed technique, which can obtain balanced minimal energy consumption while satisfying strict security and timing constraints. The proposed approach can save up to 28.9% energy consumption compared with other three candidates.

Efficient Schedulability Test for Dynamic-Priority Scheduling of Mixed-Criticality Real-Time Systems

Systems in many safety-critical application domains are subject to certification requirements. In such a system, there are typically different applications providing functionalities that have varying degrees of criticality. Consequently, the certification requirements for functionalities at these different criticality levels are also varying, with very high levels of assurance required for a highly critical functionality, whereas relatively low levels of assurance are required for a less critical functionality. Considering the timing assurance given to various applications in the form of guaranteed budgets within deadlines, a theory of real-time scheduling for such multi-criticality systems has been recently under development. In particular, an algorithm called Earliest Deadline First with Virtual Deadlines (EDF-VD) has shown a lot of promise for systems with two criticality levels, especially in terms of practical performance demonstrated through experiment results. In this article, we design a new schedulability test for EDF-VD that extends these performance benefits to multi-criticality systems. We propose a new test based on demand bound functions and also present a novel virtual deadline assignment strategy. Through extensive experiments, we show that the proposed technique significantly outperforms existing strategies for a variety of generic real-time systems.

An exact schedulability test for fixed-priority preemptive mixed-criticality real-time systems

The current literature of fixed-priority scheduling algorithms relies on sufficient tests to determine if a set of mixed-criticality sporadic tasks is schedulable on a single processor. The drawback of these safe tests is their pessimism, a matter that could be solved if an exact schedulability analysis is used. However, because of the non-deterministic behavior of tasks in the mentioned setups, exact quantification of worst-case response times, needed for the test, is a difficult problem; more precisely, such a quantification needs evaluation of enormous sequences of job executions. The core problem is thus to merge such sequences to make the analysis practical. This paper, for the first time, gives an algorithm for exact worst-case response time characterization of mixed-criticality sporadic real-time tasks executing according to a given fixed-priority scheduler. We use a set of techniques which carefully consider the task properties and their relation to the worst scenarios to prune the analysis state space. We also show an interesting result that if an exact schedulability test is used, the Audsley's optimal priority assignment algorithm is not applicable to the mixed-criticality case. Accordingly, we need new priority assignment algorithms to work with the exact test; we give a simple task priority assignment algorithm to this aim. The performance of the proposed exact test (in terms of time complexity) is examined and the effectiveness of some heuristic priority assignment algorithms using the test (in terms of the ratio of task sets which are deemed schedulable) are compared.

Cluster-based multicore real-time mixed-criticality scheduling

Abstract Cluster-based scheduling is recently gaining importance to be applied to mixed-criticality real-time systems on multicore processors platform. In this approach, the cores are grouped into clusters, and tasks that are partitioned among different clusters are scheduled by global scheduler in each cluster. This research work introduces a new cluster-based task allocation scheme for the mixed-criticality real-time task sets on multicore processors. For task allocation, smaller clusters sizes (sub-clusters) are used for mixed-criticality tasks in low criticality mode, while relatively larger cluster sizes are used for high criticality tasks in high criticality mode. In this research paper, the mixed-criticality task set is allocated to clusters using worst-fit heuristic. The tasks from each cluster are also allocated to its sub-clusters, using the same worst-fit heuristic. A fixed-priority response time analysis approach based on Audsley’s approach is used for the schedulability analysis of tasks in each cluster and sub-cluster. If the high criticality job is not completed after its worst case execution time in low mode, then the system is switched to high criticality mode. After mode switch, all the low criticalities tasks are discarded and only high criticality tasks are further executed in high criticality mode. Simulation results indicate that the percentage of schedulable task sets significantly increases under cluster scheduling as compared to partitioned and global mixed-criticality scheduling schemes.

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER11This project and the research leading to these results has received funding from the European Communitys H2020 program [H2020-ICT-2015] under grant agreement 687902. targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This article will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.

Dynamic Partitioned Cache Memory for Real-Time MPSoCs with Mixed Criticality

Shared cache interference in multi-core architectures has been recognized as one of major factors that degrade predictability of a mixed-critical real-time system. Due to the unpredictable cache interference, the behavior of shared cache is hard to predict and analyze statically in multi-core architectures executing mixed-critical tasks, which will not only result in difficulty of estimating the worst-case execution time (WCET) but also introduce significant worst-case timing penalties for critical tasks. Therefore, cache management in mixed-critical multi-core systems has become a challenging task. In this paper, we present a dynamic partitioned cache memory for mixed-critical real-time multi-core systems. In this architecture, critical tasks can dynamically allocate and release the cache resourse during the execution interval according to the real-time workload. This dynamic partitioned cache can, on the one hand, provide the predicable cache performance for critical tasks. On the other hand, the released cache can be dynamically used by non-critical tasks to improve their average performance. We demonstrate and prototype our system design on the embedded FPGA platform. Measurements from the prototype clearly demonstrate the benefits of the dynamic partitioned cache for mixed-critical real-time multi-core systems.

Fault Tolerant Scheduling of Mixed Criticality Real-time Tasks under Error Bursts

Dependability is an important requirement in hard real-time applications due to the potentially catastrophic consequences of failures. In these systems, fault tolerance mechanisms like temporal redundancy are adopted to improve reliability. Most of these types of systems are increasingly moving towards integrating critical and non-critical functionalities on the same platform to, e.g., better utilize resources and further reduce cost, and are commonly deployed in environments where errors typically occur in the form of bursts e.g., due to Electro Magnetic Interference (EMI). Consequently, in mixed criticality real-time systems, the designer must guarantee that critical tasks are feasible even under the presence of the error burst, while ensuring the feasibility of the non-critical tasks that are not affected by the burst. We refer to this as Fault Tolerance feasibility (FT-feasibility) of mixed-criticality real-time systems.In this paper, we build on the well established results on Earliest Deadline First (EDF) scheduling, to derive a sufficient test that determines the FT-feasibility of a set of mixed criticality real-time tasks under the assumption that the inter-arrival time between two consecutive error bursts is at least equal to the hyper-period of the taskset.

Fixed-priority global scheduling for mixed-criticality real-time systems

There has been a growing interest in recent years in mixed-criticality real-time systems in which tasks are attributed different levels of criticality based on the degree to which their deadlines must be assured. While most of the initial efforts on mixed-criticality systems targeted single-processor systems, the research community has recently started to investigate multiprocessor mixed-criticality real-time systems. In this paper we investigate how global, fixed-priority algorithms can be applied in the context of multiprocessor mixed-criticality systems. We identify the two key dimensions of the problem – priority assignment and schedulability testing, and consider candidate algorithms for each dimension. We also propose a new and simple priority assignment policy called CPRatio that considers both task criticality and timing constraints to improve the schedulability of mixed-criticality task sets. We experimentally evaluate the performance of priority assignment strategies and schedulability tests in the global multiprocessor mixed-criticality scheduling context.

Architecture for adaptive resource assignment to virtualized mixed-criticality real-time systems

System virtualization is a powerful approach for the creation of integrated systems, which meet the high functionality and reliability requirements of complex embedded applications. It is in particular well-suited for mixed-criticality systems, since the often applied pessimistic manner of critical system engineering leads to heavily under-utilized resources. Existing static resource management approaches for virtualized systems are inappropriate for the dynamically varying resource requirements of upcoming adaptive systems. In this paper, we propose a dynamic resource management protocol for system virtualization that factors criticality levels in and allows the addition of subsystems at runtime. The two-level architecture offers flexibility across virtual machine borders and has the potential to improve the resource utilization. In addition, it provides the capability to adapt at runtime according to defects or changes of the environment.