MixColumn Transformation Research Articles

PROVING THE SECURITY OF AES BLOCK CIPHER BASED ON MODIFIED MIXCOLUMN

Block ciphers in general, Substitution-Permutation Network (SPN) block ciphers in particular are cryptographic fields widely applied today. AES is an SPN block cipher used in many security applications. However, there are many strong attacks on block ciphers as linear attacks, differential attacks, and algebraic attacks which are challenging for cryptographers. Therefore, the research to improve the security of block ciphers in general and AES, in particular, is a topic of great interest today. Along with security, the issue of the execution cost of block ciphers is also crucial in practice. In this paper, we clarify the role of the MDS matrix in increasing the branch number of the diffusion layer of the block ciphers, thereby improving the security of the block ciphers. We propose a method improving the security of the AES block cipher by changing the Mixcolumn transformation of AES using execution-efficient MDS matrices of size 4, 8, or 16. We present a method to find a new diffusion matrix of modified AES block ciphers from which to evaluate the number of fixed points and coefficient of fixed points of the modified AES diffusion layers. In addition, we prove the branch number of the modified AES diffusion layers with MDS matrices of sizes 8, and 16. Then we also analyze the security, statistical standards and execution speed of modified AES block ciphers generated from those MDS matrices. The results show that our proposed method can significantly improve the security of the AES block cipher.

A modified MixColumn-InversMixColumn in AES algorithm suitable for hardware implementation using FPGA device

This article described the Advanced Encryption Standard (AES) encryption and decryption process without using lookup tables in the MixColumns transformation and parallelizing the transformation process implemented in the Field Programmable Gate Array (FPGA) hardware. Parallelism of the hardware process conducted to the transformation of key schedule, addroundkey, subbyte and shiftrows (subshift) and mixcolumns in the first 5 rounds of the encryption process. The decryption process was parallelized in subshift transformations, both transformations were implemented at the same time. This research produced a modified AES encryption and decryption method and algorithm with the aim of minimizing the resources required for hardware implementation. The method in this article was applied to Xilinx ISE 14.7 software. The experimental results showed that the encryption process required 2,357 slice LUT's, 845 occupied slices and 26 IOB's, while the decryption process required 2,896 LUT's, 1,323 occupied slices and 26 IOB's resources. The encryption and decryption processes each took an average of 2.891 nanoseconds and 3.467 nanoseconds for every 128 bits of data. This approach leads us to obtain a component with minimum resources and enough computational speed.

Ukrainian National Encryption Standards for FPGA Based Embedded Systems

The paper presents the hardware implementation based on FPGA of the main cryptographic transformations of the symmetric transformation algorithm of DSTU 7624:2014 and the stream cipher of DSTU 8845:2019, which are the national encryption standards of Ukraine. In the case of DSTU 7624: 2014 developed and implemented a hardware implementation for multiplication of two polynomials modulo x8+x4+x3+x2+1 in the form of a combinational circuit that allows to execute the MixColumn transformation by one cycle. SubBytes transformation is implemented based on asynchronous read-only memory. For stream cipher, DSTU 8845:2019 the nonlinear function T are implemented as subtitution byte operation in the form of precalculated cells of ROM memory. The multiplication function by α and α-1 in Galois field arithmetic GF (2 64) is realized based on ROM and combinational logic. The control of the modes of operation of the shift register with linear feedback is performed based on a FSM. Both hardware implementations of encryption standards have been verified by the authors according to the specified data in the standard, and their HDL code can be provided by the authors for further research to interested parties.

Modified Advanced Encryption Standard for Boost Image Encryption

Cryptography is a field of study that deals with converting data from a readable to an unreadable format. It can provide secrecy, data integrity, authenticity, and non-repudiation services. Security has become a concern for the community because of the technology’s potential use in numerous sectors of any company, market, agency, or governmental body, information. The cryptosystems ensure that data are transported securely and only authorized individuals have access to it. Deeply encrypted data that cannot be deciphered through cryptanalysis are in high demand right now. There are a variety of encryption algorithms that can guarantee the confidentiality of data. For multimedia data, standard symmetric encryption algorithms (AES) can give superior protection. However, using the symmetric key encryption approach on more complicated multimedia data (mainly photos) may result in a computational issue. To address this issue, the AES has been modified to satisfy the high computing requirements due to the complex mathematical operations in MixColumns transformation, which slow down the encryption process. The modified AES uses bit permutation to replace the MixColumns transformation in AES because it is simple to construct and does not require any complex mathematical computation. This research focuses on using the Modified Advanced Encryption Standard (MAES) algorithm with 128 and 256 bit key sizes to encrypt and decrypt image data. The algorithms were implemented using the Python programming language without complex mathematical computation. By comparing the MAES algorithm with the original AES algorithm, the results showed that the MAES requires less encrypting and decryption time with higher efficiency for all file sizes.

DIVERSITY AES IN MIXCOLUMNS STEP WITH 8X8 CIRCULANT MATRIX

In AES MixColumns operation, the branch number of circulant matrix is raised from 5 to 9 with 8´8 circulant matrices that can be enhancing the diffusion power. An efficient method to compute the circulant matrices in AES MixColumns transformation for speeding encryption is presented. Utilizing 8´8 involutory matrix multiplication is required 64 multiplications and 56 additions in in AES Mix-Columns transformation. We proposed the method with diversity 8´8 circulant matrices is only needed 19 multiplications and 57 additions. It is not only to encryption operations but also to decryption operations. Therefore, 8´8 circlant matrix operation with AES key sizes of 128bits, 192bits, and 256 bits are above 29.1%, 29.3%, and 29.8% faster than using 4´4 involutory matrix operation (16 multiplications, 12 additions), respectively. 8´8 circulant matrix encryption/decryption speed is above 78% faster than 8´8 involutory matrix operation. Ultimately, the proposed method for evaluating matrix multiplication can be made regular, simple and suitable for software implementations on embedded systems.

Image encryption method based on improved ECC and modified AES algorithm

Currently, embedded systems can be found everywhere in quotidian life. In the development of embedded systems, information security is one of the important factors. Encryption is an efficient technique to protect information against attacks. However, because of constraints, existing encryption functions are not compatible and do not agree with real-time applications in embedded systems. In this paper, an improved cryptographic approach with a high level of security and high speed is put forward. Our work uses an efficient version of a hybrid scheme comprising an Advanced Encryption Standard (AES) - Elliptic Curve Cryptography (ECC) for medical image encryption, which combines the benefits of the symmetric AES to speed-up data encryption and asymmetric ECC in order to secure the interchange of a symmetric session key. The contribution of this paper consists of the following two main points: First, we put forward an optimized ECC hardware architecture to respect the compromise between area, power dissipation, and speed. Thus, we primarily utilize only two multipliers to develop the Point Addition (PA) block and the Point Doubling (PD) block, which reduces time complexity. Then, a 32-bit multiplier and a 32-bit inverter architecture based on shifts and XORs are proposed to reduce power consumption and area occupancy. Second, for image encryption, we primarily propose to modify the AES by eliminating the mix-columns transformation and replacing it with a permutation based on the shifts of columns, which decreases time complexity while maintaining the Shannon diffusion and the confusion principle. Then, an adjustment of the rearrangement of the general structure is given to enhance the entropy value. The global cryptosystem is implemented using a co-design approach where the modified AES runs on the NIOS II processor, and the scalar ECC multiplication is designed as a hardware accelerator. The suggested cryptographic system spends much less execution time, which is a significant factor for being applied in practice. Security analysis is successfully performed, and our experiments prove that our proposed technique provides the basics of cryptography with more simplicity and correctness. In fact, the results of the evaluation prove the effectiveness, rapidity and high security of the suggested algorithm.

FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

Advanced Encryption Standard (AES) is a thriving cryptographic algorithm that can be utilized to guarantee security in electronic information. It remains to uphold to be resistive from most of the attacks. In this work, AES-128 encryption iterative architecture is designed to achieve minimum area and less hardware utilization. Reduced area is attained by introducing a renovated S-box structure into the AES algorithm. Furthermore, hardware utilization is minimized by incorporating the Vedic multiplier in the Mix column transformation of the AES Encryption process. The proposed encryption architecture is of 128-bit size and was executed on the Xilinx Spartan FPGA series, namely, Spartan 3, Virtex-4 and Virtex-5 devices. The optimization result exhibits that the proposed S-box technique has a smaller area than other existing conventional works.

Enhancing advance encryption standard security based on dual dynamic XOR table and MixColumns transformation

An efficient approach to secure information is critically needed at present. Cryptography remains the best approach to achieve security. On this basis, the National Institute of Standards and Technology (NIST) selected Rijndael, which is a symmetric block cipher, as the advanced encryption standard (AES). The MixColumns transformation of this cipher is the most important function within the linear unit and the major source of diffusion. Dynamic MixColumns transformation can be used to enhance the AES security. In this study, a method to enhance the AES security is developed on the basis of two methods. The first method is an extension of a previous study entitled “A novel Approach for Enhancing Security of Advance Encryption Standard using Private XOR Table and 3D chaotic regarding to Software quality Factor.” In the current study, the fixed XOR operation in AES rounds is replaced with a dual dynamic XOR table by using a 3D chaotic map. The dual dynamic XOR table is based on 4 bits; one is used for even rounds, and the other is used for odd rounds. The second method is dynamic MixColumns transformation, where the maximum distance separable (MDS) matrix of the MixColumns transformation, which is fixed and public in every round, is changed with a dynamic MDS matrix, which is private, by using a 3D chaotic map. A 3D chaotic map is used to generate secret keys. These replacements enhance the AES security, particularly the resistance against attacks. Diehard and NIST tests, entropy, correlation coefficient, and histogram are used for security analysis of the proposed method. C++ is used to implement the proposed and original algorithms. MATLAB and LINX are used for the security analysis. Results show that the proposed method is better than the original AES.

Implementation of a bit permutation-based advanced encryption standard for securing text and image files

<span>The paper proposes a modification of the Advanced Encryption Standard (AES) to address its high computational requirement steaming from the complex mathematical operations in the MixColumns Transformation which makes the encryption process slow. Bit Permutation was used instead of the MixColumns Transformation since the use of bit permutation in an encryption algorithm achieves efficiency by providing minimum encryption time and memory requirement. Results of the study showed that the modified AES algorithm exhibited faster encryption by 18.47% and faster decryption by 18.77% for text files. The modified AES algorithm also resulted to 16.53% higher avalanche effect compared with the standard AES thus improving the security performance. Application of the modified AES in encrypting images in Cipher Block Chaining mode showed that the modified algorithm also exhibited 16.88% faster encryption and 11.96% decryption compared with the standard AES. Likewise, modifying the algorithm achieved the ideal result in the histogram analysis, information entropy, the correlation coefficient of adjacent pixels to resist statistical attack. The ideal value in number of pixels change rate and unified average change intensity were also achieved making the modified algorithm resistant to differential attack. These results show that modifying AES by using bit permutation to replace MixColumns Transformation was able to address the high computational requirement of the algorithm resulting in a faster and more secure encryption algorithm for text files and images</span><span>.</span>

Enhancing advance encryption standard security based on dual dynamic XOR table and mixcolumns transformation

Enhancing advance encryption standard security based on dual dynamic XOR table and mixcolumns transformation

Performance Evaluation of Lightweight Advanced Encryption Standard Hardware Implementation

Advanced Encryption Standard (AES) is one of the most secured encryption algorithm because of its robustness and complexity. Because of its complexity, AES has slow computation. This paper presents a Lightweight Advanced Encryption Standard (LAES) design by replacing the MixColumn transformation of the traditional AES with a 128-bit permutation to lessen its computational complexity. Implementation of hardware cryptographic encryption aims to find the best trade-off between throughput and resource utilization. The proposed design is synthesized on various Field Programmable Gate Array (FPGA) devices and achieves the maximum clock frequency of 480.50 MHz with the highest throughput of 6.15 Gbps when synthesized on Virtex 7 XC7VX690T. The results on other devices show a higher throughput, better performance efficiency, and lesser area utilization when compared to the existing AES hardware implementation.

A Method to Bound the Number of Active S-Boxes for a Kind of AES-Like Structure

AbstractDue to the strong security and high performance of the AES block cipher, many hash functions take AES-like structures as building blocks. To evaluate the security of these AES-like structures against differential cryptanalysis, giving the lower bounds on the number of active S-boxes in a differential trail, is an important perspective. However, the original ‘wide-trail strategy’ for AES becomes less effective to get tight bounds for these AES-like structures, because of the different state dimensions (M×M2, instead of M×M) and different round functions from AES. In this paper, we focus on a kind of AES-like structure with state dimensions M×M2, diffusion-optimal permutations and MixColumns transformations using MDS matrices. Inspired by the ‘wide-trail strategy’, we propose a theoretical method to count active S-boxes, by which we prove that there are at least rBd(Bd−1) active S-boxes in any 2r(r≥3) rounds of such an AES-like structure, where Bd is the differential branch number of the MixColumns transformation and equals to M+1. What’s more, this lower bound can be achieved by some diffusion layers. As examples, we apply our method to the LANE hash function and 3D block cipher, optimal lower bounds are both got.

Modified AES for Text and Image Encryption

Advanced Encryption Standard (AES) is one of the most frequently used encryption algorithms. In the study, the Advanced Encryption Standard is modified to address its high computational requirement due to the complex mathematical operations in MixColumns Transformation making the encryption process slow. The modified AES used Bit Permutation to replace the MixColumns Transformation in AES since bit permutation is easy to implement and it does not have any complex mathematical computation. Results of the study show that the modified AES algorithm exhibited increased efficiency due to the faster encryption time and reduced CPU usage. The modified AES algorithm also yielded higher avalanche effect which improved the performance of the algorithm.

Improvement of Data Security Using Mixcolumn

Advanced Encryption Standard is the security based algorithm used to protect the data from the attackers.In this paper, Optimized Inverse MixColumn transformation has been designed with the help of Xtime multiplication process. Xtime multiplication performs the multiplication function for ‘m X m’ data; results will be m-bit data. Further the complexity of Xtime multiplication process has been identified and re-designed with the help of effective CSE techniques. Developed Reduced Xtime based optimized Inverse MixColumn transformation provide better performances than traditional Xtime based Inverse MixColumn multiplication.

VLSI Architecture Based Advanced Encryption Standard (AES) With Optimized Inverse Mix-Column and X-Time Multiplication Process

Rijndael is the security based methodology used to protect the information from the attackers. Rijndael algorithms perform with the data encryptions and data decryptions. Data Encryption is transform the plain text into the cipher text and the data decryption is recovering the original data. Mix-column and Inverse Mix-column is one of the difficult operations in the Rijndael algorithm. In this paper, Optimized Inverse Mix-Column transformation has been designed with the help of Xtime multiplication process. Xtime multiplication performs the multiplication function for „m X m‟ data; results will be m-bit data. Further the complexity of Xtime multiplication process has been identified and re-designed with the help of effective CSE techniques. Developed Reduced Xtime based optimized Inverse Mix-Column transformation provide better performances than traditional Xtime based Inverse Mix-Column multiplication. The proposed mix column and X-time multiplication design is implemented in terms of the VLSI Design Environment.

Hybrid Approach of Modified AES

Advanced Encryption Standard is one of the most popular symmetric key encryption algorithms to many works, which have employed to implement modified AES. In this paper, the modification that has been proposed on AES algorithm that has been developed to decrease its time complexity on bulky data and increased security will be included using the image as input data. The modification proposed itself including alteration in the mix column and shift rows transformation of AES encryption algorithm, embedding confusion-diffusion. This work has been implemented on the most recent Xilinx Spartan FPGA.

Improvement of Advanced Encryption Standard Algorithm With Shift Row and S.Box Modification Mapping in Mix Column

Cyber Security has become rising issue in recent years where encryption is one of solution and has an important role in data protection. Encryption algorithms that widely used in information security are asymmetric and symmetric. Advanced Encryption Standard (AES) is one of symmetric encryption that most used often and the most secure encryption today. However, AES encryption has slow computation. Our experiment show that both of algorithms combination needs 3.045 milliseconds for 1024 bytes of data and increase 3-4 milliseconds for 2048 bytes of data and so on. This paper proposes a novelty method to improve AES algorithm with Shift Row and S.Box modification for Mix Column transformation. The result show that our optimization has reduced 3 milliseconds and continue to increase as the number of bytes increases. Percentage average of the optimization is 86.143%.

High Throughput AES Algorithm Using Parallel Subbytes and MixColumn

Data Security and speed is very important in many on line transaction applications. It is necessary to provide security to all the on line transaction which is done on wireless medium. Cryptography is a technique used to give protection to all the confidential data. In this paper an efficient AES cryptographic algorithm is proposed. To achieve high speed in AES algorithm an eight stage Parallel accessing technique is used in SubByte transformation S-box and an eight stage parallel computation is applied in MixColumn transformation round. The results show that AES architecture with eight stage parallelism introduced in SubByte transformation and MixColumn transformation achieves high throughput than the other architectures. In S-box eight stage parallelism gives delay of 1.013 ns and in MixColumn it gives 0.835 ns delay. Parallel processing is used AES algorithm is used to increase the throughput with the trade off of increase in area. Using the proposed architecture 58.764 Gbps throughput is achieved with the expense of 6568 slices usage when implemented on virtex5 architecture which is recorded as a higher throughput than other architectures in the literature.

An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box

In this paper an efficient structural architecture is proposed for AES Encryption process to achieve high throughput with less device utilization. Breakable and controllable structures for main AES blocks at the gate level are designed and used here. The control unit using high speed combinational logic circuit is designed to control the AES structural architecture. Modified MUX based S-Box is introduced in AES instead of S-Box to reduce the area without affecting the throughput. In addition Encryption process Mix-columns transformation is modified to reduce the hardware complexity. The five stage subpipelining is introduced in AES MUX based S-Box with six pipelining stages in AES encryption process to increase throughput further. The aim of this work is to investigate both the existing and new architectures. The modified MUX based S-Box for Rijndael algorithm has been used in the 128-bit AES encryption process. The role of five stage sub-pipelined MUX based S-Box of 128-bit pipelined AES is to reduce the critical path delay to minimum for achieving high clock frequency. The rows of multiplexer in AES architecture were used for the breaking and controlling of the design. The modified 128-bit encryption was implemented on Virtex-4, Virtex-5, and Spartan 3 FPGA Devices. The results of the proposed architecture are analysed, throughput and area for the implemented design are calculated. The calculated results are compared with other architecture (Liberatori et al. in 3rd southern proceedings of the IEEE conference on programmable logic, SPL'07, pp 195---198, 2007; Farashahi et al. in Microelectron J 45:1014---1025, 2014; Good and Benaissa in IET Inf Secur 1(1):1---10, 2007; Sireesha and Madhava Rao in Int J Sci Res 3(9):1---5, 2013; Gielata et al. in Proceedings of the international conference on signals and electronic systems (ICSES), pp 137---140, 2008; El Adib and Raissouni in Int J Inf Netw Secur 1(2):1---10, 2012; Good and Benaissa in Lecture Notes Computer Science, vol 3659, pp 427---440, 2005). From the results it is obtained that the proposed architecture gives 58 % improvement with 1.08 % reduction in area.

Enhanced MixColumn Design for AES Encryption

The main aim of the current research work is to reduce the complexity path of AES (Advanced Encryption Standard) Encryption. Architecture of MixColumn transformation has been optimized in this research work. Traditional methods of MixColumn transformation methods has been realized and re-designed by reducing the redundant logical functions. Verilog Hardware Description Language (Verilog HDL) has been used to design the optimized MixColumn transformation of AES Encryption. Further optimized MixColumn design has been incorporated into AES Encryption with appropriate input points. Common Sub-expression Elimination (CSE) algorithm is used in developed AES Encryption algorithm. Proposed optimized MixColumn design offers 10.93% improvements in hardware slices, 13.6% improvements in LUTs and 1.19% improvements in delay consumption than traditional MixColumn design. Further proposed optimized MixColumn design has been incorporated into AES Encryption design. Further, proposed optimized MixColumn based AES Encryption design offers 4.75% improvements in silicon area, 4.56% reduction in power consumption than traditional MixColumn based AES Encryption. In future, proposed optimized MixColumn design will be useful in space and terrestrial applications for exhibiting secure transmissions.