Mismatch Errors Research Articles

Improved Offline Calibration of DAC Mismatch Errors in Delta–Sigma Data Converters

Element mismatch in the digital-to-analog converter (DAC) of a multibit $\Delta \Sigma $ data-converter greatly degrades the modulator’s in-band performance. One approach to correct these errors is to use an offline calibration method, based on measuring the output of the modulator in response to an in-band sinusoid. The drawback of this method, however, is the necessity for a distortion-free input sine-wave excitation. We propose a technique that dispenses with the need for a distortion-free input, thereby paving the way for the generation of the input tone on-chip. Apart from being a useful tool for debugging designs, it is a potential candidate for foreground calibration. Experimental results from a multibit modulator test chip, designed in a 180nm CMOS technology, are given.

Joint Compensation of Jitter Noise and Time-Shift Errors in Multichannel Sampling System

In high-speed analog-to-digital converters (ADCs), two main factors contribute to high power consumption. The first is the super linear relationship with the sampling rate; i.e., by doubling the sampling rate, the power consumption more than doubles. The second factor arises from the consumption of analog circuitry responsible to mitigate the jitter noise. By employing a multichannel sampling system, one can achieve high sampling rates by incorporating multiple low sampling-rate channels, which results in a linear scaling of power consumption with the number of channels. The main drawback of this system is the timing mismatch between the sampling channels. In this paper, we intend to jointly compensate the jitter noise and the timing mismatch between the channels using statistical methods. We first approximate the acquisition system and derive a stochastic model. Then, we propose an iterative maximum likelihood algorithm to estimate the parameters of the input signal. We further evaluate the Cramer-Rao lower bound (CRLB) for the estimation error to examine the proposed algorithm. Simulation results indicate that our algorithm is capable of closely following the CRLB curve for reasonable values of jitter noise and a wide range of timing mismatch errors. Moreover, it is shown that the mismatch-compensated multichannel sampling system performs almost equivalently to a single-channel high rate sampler without having its shortcomings.

Robust adaptive beamforming method for large‐scale array with automatic diagonal loading and steering vector estimation

Here, the authors propose a novel robust adaptive beamforming method, which is robust to both of the covariance matrix mismatch and the steering vector estimation mismatch. Their method was based on a recently proposed adaptive beamforming technique for large-scale arrays. In this beamforming technique, a sparse sub-array having much smaller number of antenna elements is first selected from the original physical array to perform digital sampling, and then the beamforming coefficients for the original full array are calculated by using only the digital samples from the selected sub-array. In their robust method, they calculate the diagonal loading level automatically by using the spatial-matched method. Then, the steering vector of the desired signal is estimated by maximising the beamformer output power under a constraint that the estimated steering vector does not converge to any of the interference steering vectorsor their linear combinations. Numerical examples are provided to demonstrate the effectiveness of the proposed method against covariance matrix mismatch and steering vector error.

Description of short circuit current of outdoor photovoltaic modules by multiple regression analysis under various solar irradiance levels

Short-circuit current (ISC) values of test photovoltaic (PV) modules, i.e., multi-crystalline silicon, heterostructure-with-intrinsic-thin-layer, single-crystalline silicon back-contact, CuInSe2 (CIS), and CdTe modules, are descripted using multiple regression analysis based on environmental factors (solar irradiance, average photon energy (APE), and module temperature (Tmod)) under several solar irradiance levels. The APE is an index of the solar spectral irradiance distribution. PV module irradiance sensor (PVMS), single-crystalline silicon PV module, is used to investigate simultaneous solar irradiance (IrrTPVMS). It is disclosed that ISC is primarily determined by IrrTPVMS. Error between the estimated ISC and measured ISC of test PV modules is investigated. Consequently, precise ISC description (low error) is obtained when IrrTPVMS is utilized. The more precise description of the ISC for CIS and CdTe PV modules, having the bandgap (Eg) different from PVMS, is realized when adding APE environment factor even under low IrrTPVMS (≥0 kW/m2), accumulated on both sunny day and cloudy day suggesting the enhancement of investigation opportunity. This is because APE minimizes spectral mismatch error caused by Eg difference between PVMS and test PV module. Moreover, the precision of ISC description is further increased under enhanced IrrTPVMS of ≥0.5 kW/m2 (on sunny day) due to stable solar irradiance.

Computational Imaging Method with a Learned Plug-and-Play Prior for Electrical Capacitance Tomography

Electrical capacitance tomography (ECT) is a potent image-based measurement technology for monitoring industrial processes, but low-quality images generally limit its application scope and measurement reliability. To increase the precision of reconstruction, in this study, a data-driven plug-and-play prior abstracted by a deep convolutional neural network (DCNN) and the sparseness prior of imaging objects, in form of regularizers, are jointly leveraged to generate a potent imaging model, in which the L1 norm of the mismatch error acts as a data fidelity term (DFT) to weaken the sensitivity of estimation result to noisy input data. The DCNN is embedded into the split Bregman (SB) technique to generate a powerful computing scheme for solving the built imaging model and the fast iterative shrinkage-thresholding algorithm (FISTA) is applied to solve the sub-problems efficiently. Extensive numerical results verify that the proposed imaging technique has competitive reconstruction ability and better robustness in comparison with the state-of-the-art methods. This study demonstrates the validity and efficacy of the proposed algorithm in reducing reconstruction error. Most importantly, the research outcomes verify that the data-driven plug-and-play prior and the sparseness prior can be jointly embedded into the imaging model, leading to a remarkable decline in reconstruction error.

Robust adaptive beamforming via subspace for interference covariance matrix reconstruction

Adaptive beamforming may cause performance degradation when model mismatch errors exist. In this paper, we have developed subspace methods for robust adaptive beamforming (RAB). The two proposed methods utilize the orthogonality of subspace to reconstruct the interference covariance matrix (ICM). Above all, the steering vector (SV) of desired signal in proposed methods is estimated from the desired signal covariance matrix, where desired signal covariance matrix is reconstructed based on the modified Capon spatial power spectrum estimator and it contains the less useless components. In the first proposed method, the ICM is reconstructed from the projected snapshots. Through projection, the desired signal in snapshots is eliminated and the interference components is retained to reconstruct the ICM. Based on the proposed-1 method, the peaks of spatial power spectrum corresponding to the reconstructed ICM indicate the nominal interference SVs which are used in the second proposed method. In the second proposed method, we reconstruct the ICM by each interference SV and corresponding power, and all interference SVs are exploited by solving a quadratic convex problem, where it depends on the orthogonality between interference SVs and interference subspace. The proposed-2 method is the extension of proposed-1 and it can achieve the better performance. Simulation results demonstrate that the two proposed methods are robust against types of mismatch to achieve well performance.

Tonal signal detection in passive sonar systems using atomic norm minimization

Frequency estimation of a tonal signal in passive sonar systems is crucial to the identification of the marine object. In the conventional techniques, a basis mismatch error caused by the discretization of the frequency domain is unavoidable, resulting in a severe degradation of the object detection quality. To overcome the basis mismatch error, we propose a tonal frequency estimation technique in the continuous frequency domain. Towards this end, we formulate the frequency estimation problem as an atomic norm minimization problem. From the numerical experiments, we show that the proposed technique is effective in identifying the tonal frequency components of marine objects.

Dither‐based background calibration of capacitor mismatch and gain error in pipelined noise shaping successive approximation register ADCs

A dither-based background calibration with data-weighted averaging logic to correct capacitor mismatch and inter-stage gain error in pipelined noise shaping successive approximation register ADCs is proposed. By injecting the dither signal in the background, the inter-stage gain is obtained. Besides, the data-weighted averaging logic is adopted to dissipate harmonics caused by the mismatch of capacitors. Owing to the effective combination of the two methods, there is no need to detect the conditions of injecting the dither signal. As a result, the calibration requires simple logic and adds little analogue overhead.

Compensation of inherent bias errors in using the three-dimensional acoustic intensimetry for sound source localization

The three-dimensional acoustic intensimetry has not been found useful for the sound source localization, although it was developed a long time ago. One of the leading causes is the significant amount of inherent bias error in the measured intensity vector. In addition to the well-known phase mismatch and finite difference errors, the two crucial bias error mechanisms exist yet. Both of them are principally caused by employing the limited number of microphones in estimating the direction-of-arrival vector. One is the spectral bias error exhibiting a significant fluctuation in the intensity spectrum, which is due to the time-delay of the incident and reflected sounds travelling between microphones. The other is the spatial bias error exhibiting the intensity variation depending on the probe orientation, which is due to the spatial inhomogeneity of the microphone distribution. In this work, two parameters are considered in the compensation of spectral bias error: the phase of cross-spectrum and the time contents of cross-correlation function. Also, an error map associated with the incident direction of sound is calculated for a sphere surrounding the probe to compensate for the spatial bias error. Experiments are conducted with two different source types emitting a band-limited noise and an impulsive sound, and also varying the source positions to investigate the effect of main parameters. A tetrahedral intensity probe consisted of 4 pressure microphones with 30-mm spacing is used for the test in a reverberant space. The result shows that the mean localization error is less than 3° for 0.3 < kd < 2.5, while the error without compensation is 18°. It is found that the spectral bias error can be reduced effectively by using the linearized phase of the cross-spectrum or the cross-correlation function with the truncated early-time components only.

A 600-MS/s DAC With Over 87-dB SFDR and 77-dB Peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error

This paper presents a Nyquist-rate current-steering digital-to-analog converter that achieves a peak spurious-free dynamic range better than 87 dB and a peak signal-to-noise-and-distortion ratio better than 77 dB over a 265-MHz signal band. It is enabled by a fully integrated digital calibration technique that measures and cancels both static and dynamic mismatch errors over the first Nyquist band, and various circuit-level techniques that mitigate the effects of jitter and inter-symbol interference.

A 3-mW 12b 160-MS/s 2-Way Time-Interleaved Subrange SAR ADC in 65-nm CMOS

This brief presents a 12-bit 2-way time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). This brief applied the master clock sampling and gain/offset correction schemes to mitigate channel mismatch errors. In the channel ADC, the subrange SAR ADC architecture was used to maintain high-speed and low-power features. A common bootstrapping circuit was proposed for suppressing the sampling error between coarse and fine ADCs. An intrinsic random sequence was applied to the capacitor swapping. The prototype ADC was fabricated using 65-nm CMOS technology, and it consumed 3 mW from a 1.2-V supply at a sampling rate of 160-MS/s. The measured peak signal-to-noise ratio and spurious-free dynamic range were 60.5 and 80 dB, respectively. The measured peak effective number of bits was 9.76, which is equivalent to a figure-of-merit of 21.6 fJ/conversion-step.

Bandpass mismatch error for satellite CMB experiments II: correcting for the spurious signal

Future Cosmic Microwave Background (CMB) satellite missions aim at using the B-mode polarisation signal to measure the tensor-to-scalar ratio r with a sensitivity σ(r) of the order of ⩽ 10-2. Small uncertainties in the characterisation of instrument properties such as the spectral filters can lead to a leakage of the intensity signal to polarisation and can possibly bias any measurement of a primordial signal. In this paper we discuss methods for avoiding and correcting for the intensity to polarisation leakage due to bandpass mismatch among detector sets. We develop a template fitting map-maker to obtain an unbiased estimate of the leakage signal and subtract it out of the total signal. Using simulations we show how such a method can reduce the bias on the observed B-mode signal by up to 3 orders of magnitude in power.

A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters

In time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches, caused by the limited bandwidth of input signal traces and sample circuits, seriously deteriorate the spurious-free dynamic range (SFDR) of the system. This paper analyzes the influence of bandwidth mismatch errors under different sampling sequences. Eventually, based on a randomization technique and the simulated annealing algorithm (SAA), a bandwidth mismatch optimization technique is presented that can work well with other bandwidth mismatch calibration methods. The behavior simulation results indicate that an improvement of 7[Formula: see text]dB in the SFDR can be achieved with this technique in a 16-channel TI-ADC after timing and gain calibration.

Highly-matched sub-ADC cells for pipeline analogue-to-digital converters

ABSTRACTThe conventional single-stage comparators, as the basic elements of analogue-to-digital converters (ADCs), are modified for offset and mismatch errors to be utilised in multi-bit per stage pipeline structures. At first, in single-stage comparators, pre-amplification and latch operations are managed by temporary domination of positive or negative feedback via the bulk potential variations in PMOS (p-channel metal oxide semiconductor) devices. Then, the offset correction scheme is added to provide highly matched unit cells within the sub-ADCs of the pipeline structure. Monte-Carlo analysis with 100 iterations shows that input-referred offset reduces to 0.35 mV at σ, while input offset was randomly applied from a Gaussian distribution with 30 mV at 3σ. Using as unit cells of sub-ADCs in a 12-bit 100 MS/s pipeline ADC, ENOB (and SFDR) would be improved from 8.5-bits (and 53.6 dB) to 11.25-bits (and 74.2 dB), when offset error and bulk potential of PMOS devices experiences random variations with 25 mV and 60 mV at 3σ, respectively. Power consumption reaches to 0.45 mW at 625MS/s comparison speed. Post-Layout simulation results are presented at all process corners using the BSIM3v3 model of a 0.18 µm CMOS technology.

Approximate cover of strings

Regularities in strings arise in various areas of science, including coding and automata theory, formal language theory, combinatorics, molecular biology and many others. A common notion to describe regularity in a string T is a cover, which is a string C for which every letter of T lies within some occurrence of C. The alignment of the cover repetitions in the given text is called a tiling. In many applications finding exact repetitions is not sufficient, due to the presence of errors. In this paper, we use a new approach for handling errors in coverable phenomena and define the approximate cover problem (ACP), in which we are given a text that is a sequence of some cover repetitions with possible mismatch errors, and we seek a string that covers the text with the minimum number of errors. We first show that the ACP is NP-hard, by studying the cover-length relaxation of the ACP, in which the requested length of the approximate cover is also given with the input string. We show that this relaxation is already NP-hard. We also study another two relaxations of the ACP, which we call the partial-tiling relaxation of the ACP and the full-tiling relaxation of the ACP, in which a tiling of the requested cover is also given with the input string. A given full tiling retains all the occurrences of the cover before the errors, while in a partial tiling there can be additional occurrences of the cover that are not marked by the tiling. We show that the partial-tiling relaxation has a polynomial time complexity and give experimental evidence that the full-tiling also has polynomial time complexity. The study of these relaxations, besides shedding another light on the complexity of the ACP, also involves a deep understanding of the properties of covers, yielding some key lemmas and observations that may be helpful for a future study of regularities in the presence of errors.

Quantitative evaluation of different thresholding methods using automatic reference image creation via PCA

This article proposes a principal component analysis-based automatic approach to generate reference image for evaluating different thresholding techniques. Twenty one thresholding methods have been considered for reference image creation and evaluated using five standard performance indices. Literature suggests a few performance measures, among which F-measure, modified Hausdorff distance, edge mismatch error, relative area error and object level consistency error are popular. However, correlation analysis of these metrics reveal that only F-measure, modified Hausdorff distance and edge mismatch error retain non-redundant information. Thus the best thresholding method can be determined from these three indices for different types of images, automatically. Experimental results demonstrate the potential of different thresholding methods and select the best binary segmentation technique for particular type of image set.

A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch

This paper proposes averaging correlated level shifting (ACLS) and reference swapping (RS) techniques for simultaneously reducing errors from the finite opamp gain and capacitor mismatch in a pipelined analog-to-digital converter (ADC). The ACLS technique reduces the sensitivity of ADC accuracy to the opamp gain by averaging the finite opamp gain errors in two amplifying phases, where the error in the second amplifying phase is designed to have the opposite polarity to the one in the first amplifying phase. Meanwhile, ACLS also decreases the opamp’s thermal noise. In addition, the RS utilizes the averaging operation to reduce capacitor random mismatch error and combines a simple capacitor layout arrangement to decrease capacitor gradient mismatch error. Using the ACLS and RS techniques, a 16-bit ring amplifier-based pipelined ADC without calibration is realized in a 90-nm CMOS technology. Operating at 24 MS/s for a 10-MHz sine wave input, the proposed ADC achieves a 74.3-dB signal-to-noise-and-distortion ratio (SNDR) and 85.5-dB spurious free dynamic range (SFDR), and consumes 5.1 mW, yielding Walden and Schreier figure of merits of 50.1 fJ/conversion-step and 168 dB, respectively.

An Adaptive Blind Calibration Technique for Frequency Response Mismatches in M-Channel Time-Interleaved ADCs

This brief proposes a novel adaptive architecture for blind estimation and calibration of the frequency response mismatches in an M-channel time-interleaved analog-to-digital converter (TI-ADC). Based on the basis functions generated from the measured TI-ADC output, the mismatch errors could be reconstructed blindly and subtracted from the TI-ADC output adaptively. The advantage of the proposed technique is that it only needs to know the measured output signal without requiring any additional information and it is applicable to any channel TI-ADCs. Specially, the calibration structure only needs several differentiators with fixed coefficients without requiring a bank of adaptive FIR filters. In addition, the numerical simulations have been presented to demonstrate the effectiveness and superiority of the proposed technique, which shows that the proposed technique can improve the SNR and SFDR by over 25 dB.

Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters

Device mismatch is a key concern for high-resolution data converters. This paper presents a comprehensive study of the error-feedback (EF)-based mismatch error shaping (MES) technique. EF MES overcomes the key challenge of the classic dynamic element matching-based MES whose complexity grows exponentially with the number of bits; however, the prior EF MES comes with the limitations of limited shaping capability and reduced dynamic range. This paper demonstrates how to perform more advanced EF MES for various types of data converters. Moreover, this paper also proposes the use of digital prediction to address the dynamic range loss issue.

A 550-$\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS

This paper presents an incremental analog-todigital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signalto-quantization-noise ratio (SQNR) exponentially with a few number of clock cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniformexponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 μW, and 0.134 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/-0.27 LSB and +0.84 LSB/-0.81 LSB, respectively.