MIS Devices Research Articles

The III-Nitride Double Heterostructure Revisited: Benefits for Threshold Voltage Engineering of MIS Devices

GaN-based devices are seen as ideal candidates for power-switching applications. For the acceptance of GaN-based devices by module designers, obtaining enhancement-mode (e-mode) behavior in GaN-based heterostructure field-effect transistors (HFETs) has long been in the focus. Although the gate-injection approach appears to be the most promising one to achieve e-mode devices, using a double heterostructure in conjunction with a gate insulator has still its advantages, such as steeper turn-ON characteristics and lower leakage currents. An analytical expression to predict the threshold voltage $V_{\mathrm {th}}$ for a given double heterostructure device has not yet been derived. Moreover, neither an evaluation of the tradeoff between $V_{\mathrm {th}}$ and ON-state resistance $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}}$ has been performed to date. This paper addresses these two aspects. We will show an analytical expression for a metal–insulator–semiconductor double HFET (MIS-DHFET), which in certain cases is also valid for the gate-injection transistor. On the basis of this, we will discuss the actual influence of the Al concentration in the backbarrier on $V_{\mathrm {th}}$ . We will further employ technology computer aided design (TCAD) device simulations to evaluate the impact on $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}}$ when using MIS-DHFETs. It will be shown that by implementing a double heterostructure in MIS devices, it is possible to suppress the typically observed negative $V_{\mathrm {th}}$ –oxide thickness relationship while maintaining a constant $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}}$ .

Study on the effect of PVDF-TrFE layer to the electrical properties of MIS devices

This paper investigates the effect of PVDF-TrFE layer to the electrical properties of MIS device. The MIS (Al/PMMA:TiO2/PVDF-TrFE/Si) structures were fabricated on n-type Si substrate. The results indicate that the properties of MIS improved drastically with PVDF-TrFE layer. I-V and C-V characteristics shows that the MIS has a fast operating voltage approximately 1 V, low leakage current, large capacitance. No hysteresis was observed compared to MIS without PVDF-TrFE layer. The improvement in the electrical properties of MIS (Al/PMMA:TiO2/PVDF-TrFE /Si) is due to the increment in the real permittivity, ε’ value of the insulator.

Current conduction mechanism of MIS devices using multidimensional minimization system program

The present work presents an evaluation approach which enables the in-depth analysis of current–voltage (I–V) characteristics of MIS devices to determine their current transport mechanisms using a multidimensional minimization system program.Exemplarily, the current transport mechanisms were determined for a TiN/SiO2/p-Si MOS and a TaN/HfSiO/SiO2/p-Si MIS structure by fitting the analytical expressions for different current transport mechanisms to experimental I–V data in a wide range of applied biases and temperatures. The considered mechanisms for the investigated samples include temperature dependent Fowler–Nordheim (FN) tunneling and Poole–Frenkel (PF) emission as well as ohmic conduction. The presented approach can easily be extended to account for additional mechanisms such as trap assisted tunneling (TAT) if relevant for different samples. In contrast to typical extraction procedures which determine current conduction mechanism parameters sequentially, in this work, the adjustable fit parameters are extracted in a single operation using the Levenberg–Marquardt algorithm (Nash, 1990) to obtain a least-square fit of the model to measured I–V characteristics. Thus, simultaneously occurring current mechanisms can properly be evaluated which allows to determine the fraction of each conduction mechanism quantitatively for each voltage.

Control current stress technique for the investigation of gate dielectrics of MIS devices

AbstractIn this study, a modified technique of control current stress to investigation thin gate dielectric of MIS structures is proposed. This technique allows to monitor charge trapping in gate dielectric of MIS structures under high‐field and another stress situations (irradiation, plasma, hot carriers, etc.). The technique also may be used for testing thin gate dielectric defects. Unlike simple techniques, for example constant current stress and J‐ramp current stress, the proposed method uses a sequence of stress current and measuring current pulses. At the same time, the processes of charging and discharging of the MIS structure capacitance as well as the charge trapping in the gate dielectric are taken into account. Charging of MIS structure from inversion to accumulation modes or back way allows one to retrieve a low frequency capacitive‐voltage characteristic. Account charging capacitance of MIS structure and charge trapping in gate dielectric at injective mode lets considerably increase metrological characteristics of this technique and reduce inaccuracies. The models describing the change in the charge state of MIS structures, both in the charge capacity, and in the mode of injection of charge carriers were developed. Using these models let to choose optimal algorithm of current stress and increase measurement accuracy. (© 2015 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Adaptation of the model of tunneling in a metal/CaF2/Si(111) system for use in industrial simulators of MIS devices

An approach toward simplification of the model of the tunneling transport of electrons through a thin layer of crystalline calcium fluoride into a silicon (111) substrate with subsequent implementation in simulators of semiconductor devices is suggested. The validity of the approach is proven by comparing the results of modeling using simplified formulas with the results of precise calculations and experimental data. The approach can be applied to calculations of tunneling currents in structures with any crystalline insulators on Si (111).

Ni/CNT/SiO2 구조의 4H-SiC MIS 캐패시터의 전기적 특성

본 연구에서는, Ni/CNT/<TEX>$SiO_2$</TEX> 구조의 4H-SiC MIS 캐패시터를 제작하고 전기적 특성을 조사하였다. 이를 통하여 4H-SiC MIS 소자에서 탄소나노튜브의 역할을 분석하고자 하였다. 탄소나노튜브는 이소프로필알코올과 혼합하여 <TEX>$SiO_2$</TEX> 표면에 분산하였다. 소자의 전기적 특성 분석을 위하여 300-500K의 온도 범위에서 소자의 정전용량-전압 특성을 측정하였다. 밴드 평탄화 전압은 양의 방향으로 shift되었다. 정전용량-전압 그래프로부터 계면 포획 전하 밀도 및 산화막 포획 전하 밀도가 유도되었다. 산화막의 상태는 4H-SiC MIS 구조의 계면에서 전하 반송자 또는 결함 상태와 관련된다. 온도가 증가함에 따라 밴드 평탄화 전압은 음의 방향으로 shift되는 결과를 얻었다. 실험 결과로부터, Ni과 <TEX>$SiO_2$</TEX> 계면에 탄소나노튜브를 첨가함에 따라 4H-SiC MIS 캐패시터의 게이트 특성을 조절 가능할 것으로 판단된다. In this study, the electrical characteristics of Ni/CNT/<TEX>$SiO_2$</TEX> structures were investigated in order to analyze the mechanism of carbon nanotubes in 4H-SiC MIS device structures. We fabricated 4H-SiC MIS capacitors with or without carbon nanotubes. Carbon nanotubes were dispersed by isopropyl alcohol. The capacitance-voltage (C-V) is characterized at 300 to 500K. The experimental flat-band voltage (<TEX>$V_{FB}$</TEX>) shift was positive. Near-interface trapped charge density and oxide trapped charge density values of Ni/CNT/<TEX>$SiO_2$</TEX> structure were less than values of reference samples. With increasing temperature, the flat-band voltage was negative. It has been found that its oxide quality is related to charge carriers or defect states in the interface of 4H-SiC MIS capacitors. Gate characteristics of 4H-SiC MIS capacitors can be controlled by carbon nanotubes between Ni and <TEX>$SiO_2$</TEX>.

Modification and reduction of defects in thin gate dielectric of MIS devices by injection‐thermal and irradiation treatments

AbstractThe effect of high‐field injection‐thermal and irradiation treatments on the MIS structures reliability and defect reduction in the nanoscale gate dielectric has been investigated. Injection‐thermal treatment (ITT) of MIS structures consisted of high‐field electron injection into gate dielectric with the charge of defined value and subsequent parameter stabilization of MIS structures by means of thermal annealing. The MIS structures have been studied using novel techniques of multilevel current stress. Our study shows that the ITT can improve reliability of MIS structures (increase of charge‐to‐breakdown value) and identify defective structures. The ITT provides structural modification of SiO2 and Si–SiO2 interfaces. It has been shown that the ITT at elevated temperatures can reduce the reliability of MIS devices. Performing ITT at high temperatures leads to decrease of charge‐to‐breakdown average value in MIS structures. It has been demonstrated that irradiation treatment allows to reduce density of defects in thermal SiO2 films, SiO2 films doped with phosphorus, oxynitride films and as a result to increase reliability of MIS devices. (© 2015 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Fermi level depinning and contact resistivity reduction using a reduced titania interlayer in n-silicon metal-insulator-semiconductor ohmic contacts

Experimental evidence of reduction of ultrathin TiO2 by Ti is presented and its effect on Fermi level depinning and contact resistivity reduction to Si is experimentally studied. A low effective barrier height of 0.15 V was measured with a Ti/10 Å TiO2−x/n-Si MIS device, indicating 55% reduction compared to a metal/n-Si control contact. Ultra-low contact resistivity of 9.1 × 10−9 Ω-cm2 was obtained using Ti/10 Å TiO2−x/n+ Si, which is a dramatic 13X reduction from conventional unannealed contacts on heavily doped Si. Transport through the MIS device incorporating the effect of barrier height reduction and insulator conductivity as a function of insulator thickness is comprehensively analyzed and correlated with change in contact resistivity. Low effective barrier height, high substrate doping, and high conductivity interfacial layer are identified as key requirements to obtain low contact resistivity using MIS contacts.

BOEMDET-Band Offsets and Effective Mass Determination Technique utilizing Fowler-Nordheim tunneling slope constants in MIS devices on silicon

The Fowler-Nordheim carrier tunneling slope constants for electron and hole conduction through MOS devices fabricated on silicon substrate are utilized to determine the conduction and valence band offsets, carrier effective masses in the SiO2 and its unknown bandgap, independent of photoemission spectroscopic measurements of band offsets on SiO2/Si samples. The slope constants are obtained from the electron and hole tunneling currents versus voltage characteristics on a pair of n-MOS and p-MOS devices in accumulation or an n-channel MOSFET device in inversion that allows carrier separation. This characterization technique called BOEMDET, can be applied to other insulating materials grown or deposited on silicon, such as JVD nitride, HfSiON, SiOxNy, and high-K oxides found viable for future MOS technology. To an accuracy of one decimal place, the conduction band offset for the SiO2/Si MIS structure is determined to be 3.2 eV, the valence band offset obtained is 4.6 eV and the bandgap of SiO2 is found to be 8.9 eV. The electron and hole effective masses in the SiO2 are calculated to be 0.42m and 0.58m, where m is the free electron mass. In case of quantum confinement at the SiO2/Si interface, the electron and hole masses correct to 0.51m and 0.65m. Also, the carrier effective masses in thermal SiO2 are found to be the same for all thickness of the oxide. Keywords: effective mass, FN-tunneling, band offsets, metal-insulator-semiconductor

BOEMDET-Band Offsets and Effective Mass Determination Technique applied to MIS devices on silicon to obtain the unknown bandgap of insulators

The Fowler-Nordheim carrier tunneling slope constants for electron and hole conduction through MOS devices fabricated on silicon substrate can be utilized to determine the conduction and valence band offsets, carrier effective masses in the SiO2 and its unknown bandgap, independent of photoemission spectroscopic measurements of band offsets on SiO2/Si samples. The slope constants can be obtained from the electron and hole tunneling currents versus oxide voltage characteristics on a pair of n-MOS and p-MOS devices in accumulation. This characterization technique called BOEMDET, can be applied to other insulating materials grown or deposited on silicon, such as jet vapor deposited (JVD) nitride, HfSiON, SiOxNy, AlN, BN, high-K oxides, and transparent conducting oxides (TCO).

The analysis of the current–voltage characteristics of the high barrier Au/Anthracene/n-Si MIS devices at low temperatures

The Au/Anthracene/n-Si/Al MIS device was fabricated on the basis of anthracene film covalently bonded to a Si substrate. The MIS device showed Schottky behavior with barrier heights of 0.85 eV and ideality factors of 1.88 at 300 K. The barrier height of the Au/n-Si has increased after deposition of the anthracene layer onto Si. Temperature dependent current–voltage (I–V) measurements were performed on the Au/Anthracene/n-Si/Al MIS diodes in the range 140–300 K. From the temperature dependence of forward bias I–V, the barrier height was observed to increase with temperature. However, the ideality factor decreased with increasing temperature. The values of activation energy (Ea) and Richardson constant (A*) were determined as 0.24 eV and 7.57 × 10−6 A cm−2 K−2 from the slope and the intercept at ordinate of the linear region of Richardson plot, respectively. The increase of the series resistance Rs with the fall of temperature was attributed to lack of free carrier concentration at low temperatures.

Barrier height enhancement of metal/semiconductor contact by an enzyme biofilm interlayer

A metal/interlayer/semiconductor (Al/enzyme/p-Si) MIS device was fabricated using α-amylase enzyme as a thin biofilm interlayer. It was observed that the device showed an excellent rectifying behavior and the barrier height value of 0.78 eV for Al/α-amylase/p-Si was meaningfully larger than the one of 0.58 eV for conventional Al/p-Si metal/semiconductor (MS) contact. Enhancement of the interfacial potential barrier of Al/p-Si MS diode was realized using enzyme interlayer by influencing the space charge region of Si semiconductor. The electrical properties of the structure were executed by the help of current–voltage and capacitance–voltage measurements. The photovoltaic properties of the structure were executed under a solar simulator with AM1.5 global filter between 40 and 100 mW/cm2 illumination conditions. It was also reported that the α-amylase enzyme produced from Bacillus licheniformis had a 3.65 eV band gap value obtained from optical method.

High permittivity gadolinium oxide deposited on indium phosphide by high-pressure sputtering without interface treatments

Two-step high-pressure sputtering for Gd2O3 deposition on InP substrates.Working MIS devices for all sputtering and plasma oxidation conditions.High capacitance (CET of 2.4nm) with moderate leakage (under 10-3Acm-2 at a gate voltage of 1V). We show working metal-insulator-semiconductor devices fabricated on InP with high-k gadolinium oxide deposited by a two-step high-pressure sputtering procedure. Functional devices are obtained in all cases, with a full accumulation-depletion-inversion sweep. An intermixing of the Gd2O3 with the Pt/Al gate was found, which limited accumulation capacitance. After changing the process to pure Pt gates, the accumulation capacitance increased by a factor of ~2. The devices show an unpinned Fermi level and moderate leakages, although there is a high level of interfacial traps. These traps are not passivated after a soak anneal at 325?C.

Preparation and Characterization of (Au/n-Sn/Si/Si/Al) MIS Device for Optoelectronic Application

SnO₂ thin films were prepared by using rapid thermal oxidation (RTO) of Sn at oxidation temperature 873&#x2009;K and oxidation time 90&#x2009;sec on semiconductor n-type and p-type silicon substrate. In order to characterize the prepared device, the electrical properties have been measured which revealed that the barrier height is greatly depended on interfacial layer thickness (SiO₂). The value of peak response (n-SnO₂/SiO₂/n-Si) device was 0.16&#x2009;A/W which is greater than that of (n-SnO₂/SiO₂/p-Si) device whose value was 0.12&#x2009;A/W, while the rise time was found to be shorter.

Effect of temperature on the capacitance–frequency and conductance–voltage characteristics of polyaniline/p-Si/Al MIS device at high frequencies

A polyaniline/p-Si/Al MIS device has been fabricated by forming a polyaniline layer on Si by using the electrochemical polymerization method. The conductance–voltage and capacitance–frequency measurements have been performed as a function of temperature. The capacitance of the device decreased with increasing frequency. The increase in capacitance results from the presence of interface states. The peaks have been observed in the conductance curves of the device and attributed to the presence of an interfacial layer between polyaniline and p-Si. For each temperature, the plot of series resistance/voltage gave a peak. The voltage and temperature dependence of series resistance has been attributed to the particular distribution density of interface states and the interfacial insulator layer.

Study and modeling of the transport mechanism in a Schottky diode on the basis of a GaAs semiinsulator

The current through a metal—semiconductor junction is mainly due to the majority carriers. Three distinctly different mechanisms exist in a Schottky diode: diffusion of the semiconductor carriers in metal, thermionic emission-diffusion (TED) of carriers through a Schottky gate, and a mechanical quantum that pierces a tunnel through the gate. The system was solved by using a coupled Poisson—Boltzmann algorithm. Schottky BH is defined as the difference in energy between the Fermi level and the metal band carrier majority of the metal—semiconductor junction to the semiconductor contacts. The insulating layer converts the MS device in an MIS device and has a strong influence on its current—voltage (I—V) and the parameters of a Schottky barrier from 3.7 to 15 eV. There are several possible reasons for the error that causes a deviation of the ideal behaviour of Schottky diodes with and without an interfacial insulator layer. These include the particular distribution of interface states, the series resistance, bias voltage and temperature. The GaAs and its large concentration values of trap centers will participate in an increase in the process of thermionic electrons and holes, which will in turn act on the I—V characteristic of the diode, and an overflow maximum value [NT = 3 × 1020] is obtained. The I—V characteristics of Schottky diodes are in the hypothesis of a parabolic summit.

Reliability issues of double gate dielectric stacks based on hafnium dioxide (HfO 2) layers for non-volatile semiconductor memory (NVSM) applications

In this study, we present selected reliability issues of double gate dielectric stacks for non-volatile semiconductor memory (NVSM) applications. Fabricated gate structures were consisted of PECVD silicon oxynitride layer (SiO x N y ) as the pedestal layer and hafnium dioxide layer (HfO 2) as the top gate dielectric. In the course of this work, obtained MIS structures were investigated by means of current–voltage characteristics, as well as applying dc stresses in constant current (CCS) and voltage (CVS) mode. Presented results have shown that the application of ultra-thin PECVD silicon oxynitride layer results in significant increase of breakdown voltage value in comparison to MIS structure with only hafnia as the gate dielectric. Moreover, due to the high temperature annealing of deposited SiO x N y layers, MIS device demonstrates much lower leakage currents, as well as higher breakdown voltage values in comparison to device with ‘as-deposited’ SiO x N y bottom layer. The results also proved larger immunity to dc stresses and better retention characteristics of MIS devices with ‘annealed’ oxynitride, in comparison to ‘as-deposited’ pedestal layer.

Electrical Characterization and Reliability of Nitrided-Gate Insulators for N- and P-Type 4H-SiC MIS Devices

In this paper, nitrided insulators such as N2O-grown oxides, deposited SiO2 annealed in N2O, and deposited SiNx/SiO2 annealed in N2O on thin-thermal oxides have been investigated for realization of high performance n- and p-type 4H-SiC MIS devices. The MIS capacitors were utilized to evaluate MIS interface characteristics and the insulator reliability. The channel mobility was determined by using the characteristics of planar MISFETs. Although the N2O-grown oxides are superior to the dry O2-grown oxides, the deposited SiO2 and the deposited SiNx/SiO2 exhibited lower interface state density (n-MIS: below 7x1011 cm-2eV-1 at EC-0.2 eV, p-MIS: below 6x1011 cm-2eV-1 at EV+0.2 eV) and higher channel mobility (n-MIS: over 25 cm2/Vs, p-MIS: over 10 cm2/Vs). In terms of reliability, the deposited SiO2 annealed in N2O exhibits a high charge-to-breakdown over 50 C/cm2 at room temperature and 15 C/cm2 at 200°C. The nitrided-gate insulators formed by deposition method have superior characteristics than the thermal oxides grown in N2O.

Electronic properties of the metal/organic interlayer/inorganic semiconductor sandwich device

In this study, we prepared a Metal(Al)/Organic Interlayer(Congo Red=CR)/Inorganic Semiconductor ( p-Si) (MIS) Schottky device formed by coating of an organic film on p-Si semiconductor wafer. The Al/CR/ p-Si MIS device had a good rectifying behavior. By using the forward bias I– V characteristics, the values of ideality factor ( n) and barrier height ( Φ b ) for the Al/CR/ p-Si MIS device were obtained as 1.68 and 0.77 eV, respectively. It was seen that the Φ b value of 0.77 eV calculated for the Al/CR/ p-Si MIS device was significantly higher than value of 0.50 eV of the conventional Al/ p-Si Schottky diodes. Modification of the interfacial potential barrier of the Al/ p-Si diode was achieved by using a thin interlayer of the CR organic material. This was attributed to the fact that the CR organic interlayer increased the effective barrier height by influencing the space charge region of Si. The interface-state density of the MIS diode was found to vary from 1.24×10 13 to 2.44×10 12 eV −1 cm −2.

Study on C60 Doped PMMA for Organic Memory Devices

AbstractIn this paper, fabrication of nanocomposite thin films with introduction of fullerene (C60) molecules in PolyMethyl MethAcrylate resist (PMMA) was investigated from a material and electrical point of view. The effective inclusion of C60 molecules in the samples was characterized by using UV-vis and Tof-SIMS instruments. The modified resist PMMA:C60 was also studied with Thermal analysis (TGA, DSC) where modification of physical properties is reported. Films were included in MIS and MIM devices and results on non volatile trapping of C60 doped PMMA are presented. Moreover, e-beam exposure tests showed that PMMA:C60 active layers for memory devices, were scalable in size.