MIPS R3000 Research Articles

Model of a hybrid processor executing C++ with additional quantum functions

The objective of this paper is to model a hybrid quantum processor capable of executing both classical and quantum instructions. The processor is modeled and simulated using VHDL. It consists of a MIPS R2000 processor with a quantum processing module embedded within it. Additionally, an assembler has been developed capable of interpreting assembly programs modeling quantum algorithms or circuits, containing instructions from both the standard MIPS instruction set as well as the Quantum Assembly (QASM) instruction set. Furthermore, a quantum C++ library has been developed, with methods and classes to encapsulate the QASM instructions so that a programmer may use it to develop a C++ program implementing a quantum algorithm containing both classical and quantum parts.

Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs

The design of complex systems-on-chip (SoCs) in the upcoming complementary metal-oxide-semiconductor (CMOS) technologies has become increasingly challenging due to the high levels of integration, the excessive energy consumption, the clock distribution problems and the increased process variability impact. To deal with these issues, we consider network-on-chip (NoC) architectures partitioned into several voltage-frequency domains and propose an efficient control algorithm for on-the-fly workload monitoring and management. This algorithm is able to cope with the technology-related variability and with the variable workload of the system. It dynamically controls the speed of the different voltage-frequency islands with respect to the process variability impact on each island. Within this work, a new clock synchronization scheme is also presented. Simulation results demonstrate the effectiveness of our approach in guarantying the average speed performance of the system under different cases of the process variability effect while keeping reduced the overall system energy consumption. Moreover, this is achieved with a small area overhead. The results are validated on a MIPS R2000 processor node using the 45 nm CMOS technology from STMicroelectronics.

에너지 소비 모니터링을 위한 재목적 인스트럭션-셋 시뮬레이터

Retargetability is typically achieved by providing target machine information, ADL, as input. The ADL are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, etc. Simulator are critical components of the exploration and software design toolkit for the system designer. They can be used to perform diverse tasks such as verifying the functionality and/or timing behavior of the system, and generating quantitative measurements(e.g., power energy consumption) which can be used to aid the design process. In this paper, we generate the energy consumption estimation simulator through ADL. For this goal, firstly, we describes the energy consumption estimation and monitoring informations on the ADL based on EXPRESSION. Secondly, we generate the energy estimation and monitoring simulation library and then constructs the simulator, RenergySim. Lastly, we represent the energy estimations results for MIPS R4000 ADL description. From this subjects, we contribute to the efficient architecture developments and prompt SDK generation through programmable experiments in the field of mobile software development.

임베디드 코어 설계시 효율적인 설계 공간 탐색을 위한 컴파일드 코드 방식 시뮬레이터 생성 시스템 구축

본 논문은 어플리케이션에 최적화된 임베디드 시스템 설계에 있어 효율적인 설계 공간을 탐색할 수 있도록 머신 기술 언어를 기반으로 한 컴파일드 코드 방식 시뮬레이터 생성 시스템을 제안한다. 제안된 시스템 event-driven 시뮬레이션의 융통성을 유지하면서 많은 시뮬레이션 시간을 소요하는 인스트럭션 펫치와 디코딩 과정을 정적으로 결정하여 빠른 수행시간을 갖는 컴파일드 코드 방식 시뮬레이터를 생성한다. 생성된 시뮬레이터는 임베디드 코어의 성능 측정을 위한 사이클 수준과 인스트럭션 수준의 시뮬레이션을 가진다. 구축된 컴파일드 코드 방식 시뮬레이터 생성기의 효율성을 확인하기 위해 JPEG 인코더 어플리케이션에 대한 아키텍처 탐색을 수행하였다. 제안된 시스템은 MIPS R3000 프로세서의 초기 임베디드 코어로 시작하여 어플리케이션에 최적화된 임베디드 코어를 얻어내었다. 이 과정에서 많은 시뮬레이션 시간이 요구되었다. 사이클 수준 컴파일드 코드 빙식 시뮬레이터는 event-driven 시뮬레이션의 정확성을 가지며 평균 21.7%의 향상된 시뮬레이션의 수행 속도를 보인다. This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.

Code Compression with Split Echo Instructions

Code density is often a critical issue in embedded computers, since the memory size of embedded systems is strictly limited. Echo instructions have been proposed as a method for reducing code size. This paper presents a new type of echo instruction, split echo, and evaluates an implementation of both split echo and traditional echo instructions on a MIPS R3000 based processor. Evaluation results show that memory requirement is reduced by 12% on average with small additional hardware cost.

RENO

RENO is a modified MIPS R10000 register renamer that uses map-table "short-circuiting" to implement dynamic versions of several well-known static optimizations: move elimination, common subexpression elimination, register allocation, and constant folding. Because it implements these optimizations dynamically, RENO can apply optimizations in certain situations where static compilers cannot. Several of RENOýs component optimizations have been previously proposed as independent mechanisms. Unified renaming [13] implements dynamic move elimination and speculative memory bypassing [19] (the dynamic counterpart of register allocation). Register integration [21] implements common-subexpression elimination and speculative memory bypassing. RENO unifies these mechanisms and adds a dynamic version of constant folding, RENOCF. RENOCF uses an extended map table format and a limited form of dynamic operation fusion. Cycle-level simulation shows that RENO dynamically eliminates (i.e., optimizes away) 22% of the dynamic instructions in both SPECint2000 and MediaBench. RENOCF is responsible for 12% and 17% of the eliminations, respectively. Because dataflow dependences are collapsed around eliminated instructions, performance improves by 8% and 13%, respectively. Alternatively, because eliminated instructions do not consume issue queue entries, physical registers, or issue, bypass, register file, and execution bandwidth, RENO can be used to absorb the performance impact of a significantly scaled-down execution core.

Dynamic Data Layouts for Cache-Conscious Implementation of a Class of Signal Transforms

Effective utilization of cache memories is a key factor in achieving high performance for computing large signal transforms. Nonunit stride access in the computation of large signal transforms results in poor cache performance, leading to severe degradation in the overall performance. In this paper, we develop a cache-conscious technique, called a dynamic data layout, to improve the performance of large signal transforms. In our approach, data reorganization is performed between computation stages to reduce cache misses. We develop an efficient search algorithm to determine an optimal tree with the minimum execution time among possible factorization trees based on the size of the signal transform and the data access stride. Our approach is applied to compute the fast Fourier transform (FFT) and the Walsh-Hadamard transform (WHT). Experiments were performed on Alpha 21264, MIPS R10000, UltraSPARC III, and Pentium 4. Experimental results show that our FFT and WHT achieve performance improvement of up to 3.52 times over other state-of-the-art FFT and WHT packages. The proposed optimization is portable across various platforms.

A Parallel Boundary Value Technique for Singularly Perturbed Two-Point Boundary Value Problems

A class of singularly perturbed two-point boundary-value problems (BVPs) for second-order ordinary differential equations (DEs) is considered here. In order to obtain numerical solution to these problems, an iterative non-overlapping domain decomposition method is suggested. The BVPs are independent in each subdomain and one can use parallel computers to solve these BVPs. One of the characteristics of the method is that the number of processors available is a free parameter of the method. Practical experiments on a Silicon Graphics Origin 200, with 4 MIPS R10000 processors have been performed, showing the reliability and performance of the proposed parallel schemes. Error estimates for the solution and numerical examples are provided.

Code compression by register operand dependency

This paper proposes a dictionary-based code compression technique that maps the source register operands to the nearest occurrence of a destination register in the predecessor instructions. The key idea is that most destination registers have a great possibility to be used as source registers in the following instructions. The dependent registers can be removed from the dictionary if this information can be specified otherwise. Such destination–source relationships are so common that making use of them can result in much better code compression. After removing the dependent register operands, the original dictionary size can be reduced significantly. As a result, the compression ratio can benefit from: (a) the reduction of dictionary size due to the removal of dependent registers, and (b) the reduction of program encoding due to the reduced number of dictionary entries. A set of programs has been compressed using this feature. The compression results show that the average compression ratio is reduced to 38.41% on average for MediaBench benchmarks compiled for MIPS R2000 processor, as opposed to 45% using operand factorization.

Compressing MIPS code by multiple operand dependencies

Intuitively, destination registers of some instructions have great possibilities to be used as the source registers of the immediately subsequent instructions. Such destination register/source register pairs have been exploited previously to improve code compression ratio [ compression ratio = ( Dictionary Size + Encoded Program Size )/ Original Program Size ]. This paper further examines the exploitation of both register and immediate operand dependencies to improve the compression ratio. A mapping tag is used to flag dependency relationships so that dependent operands can be omitted during compression. The compression ratio is enhanced by both the removal of dependent operands and the sharing of mapping tags between different types of dependencies and between different instructions. Simulation results show that the proposed method results in the best compression ratio achieved so far, giving average compression ratios of 33.8% for MediaBench benchmarks and 33.6% for SPEC95 benchmarks, both compiled for a MIPS R2000 processor.

Tight bounds on cache use for stencil operations on rectangular grids

We derive tight bounds on cache misses for evaluation of explicit stencil operators on rectangular grids. Our lower bound is based on the isoperimetric property of the discrete crosspolytope. Our upper bound is based on a good surface-to-volume ratio of a parallelepiped spanned by a reduced basis of the interference lattice of a grid. Measurements show that our algorithm typically reduces the number of cache misses by a factor of three, relative to a compiler optimized code. We show that stencil calculations on grids whose interference lattices have a short vector feature abnormally high numbers of cache misses. We call such grids unfavorable and suggest to avoid these in computations by appropriate padding. By direct measurements on a MIPS R10000 processor we show a good correlation between abnormally high numbers of cache misses and unfavorable three-dimensional grids.

Rsim: simulating shared-memory multiprocessors with ILP processors

The early 1990s saw several announcements of commercial shared-memory systems using processors that aggressively exploited instruction-level parallelism (ILP), including the MIPS R10000, Hewlett-Packard PA8000, and Intel Pentium Pro. These processors could potentially reduce memory read stalls by overlapping read latency with other operations, possibly changing the nature of performance bottlenecks in the system. The authors' experience with Rsim demonstrates that modeling ILP features is important even in shared-memory multiprocessor systems. In particular, current simple processor-based approximations cannot model significant performance effects for applications exhibiting parallel read misses. Further, recent shared-memory designs such as aggressive implementations of sequential consistency use the aggressive ILP-enhancing features of modern processors that simple processor-based simulators do not model. As microprocessor systems become more complex, the availability of shared infrastructure source code is likely to become increasingly crucial. The authors plan to release a new Rsim version shortly that will include instruction caches, TLBs, multimedia extensions, simultaneous multithreading, Rabbit fast simulation mode, and ports to Linux platforms.

Parallel Multigrid for Anisotropic Elliptic Equations

In this paper two well-known robust multigrid solvers for anisotropic operators on structured grids are compared: alternating-plane smoothers combined with full coarsening and plane smoothers combined with semi-coarsening. The study has taken into account not only numerical properties but also architectural ones, focusing on cache memory exploitation and parallel characteristics. Experimental results for the sequential algorithms have been obtained on two different systems based on the MIPS R10000 processor, but with different L2 cache sizes and memory bandwidths (an SGI O2 workstation and an SGI Origin 2000 system). Although the alternating-plane approach is the best choice for sequential implementations, experimental estimations show poor parallel efficiencies. For the semicoarsening alternative two different parallel implementations have been considered. The first one has optimal parallel characteristics but due to deterioration of the convergence properties its realistic efficiency is not satisfactory. In the second one, some processors remain idle during a short period of time on every multigrid cycle. However, the second parallel algorithm is more efficient since it preserves the numerical properties of the sequential version. Parallel experiments have also been taken on a Cray T3E system.

Expression-tree-based algorithms for code compression on embedded RISC architectures

Reducing program size has become an important goal in the design of modern embedded systems targeted to mass production. This problem has driven efforts aimed at designing processors with shorter instruction formats (e.g., ARM Thumb and MIPS16) or able to execute compressed code (e.g., IBM PowerPC 405), This paper proposes three code compression algorithms for embedded RISC architectures. In all algorithms, the encoded symbols are extracted from program expression trees. The algorithms differ on the granularity of the encoded symbol, which are selected from whole trees, parts of trees, or single instructions. Dictionary-based decompression engines are proposed for each compression algorithm. Experimental results, based on SPEC CINT95 programs running on the MIPS R4000 processor, reveal an average compression ratio of 53.6% (31.5%) if the area of the decompression engine is (not) considered.

Learning operating systems structure and implementation through the MPS computer system simulator

Lab activity is fundamental for the real understanding of several computer science topics such as operating systems. We have built our own hardware emulator after using software tools from other Universities for several years. MPS is a general-purpose computer system simulator based on MIPS R3000 processor. Together with the main processor, RAM, ROM, disks, tapes, printer and terminal interfaces are carefully emulated and fully configurable; non-volatile memory units may be retained between simulations.MPS features a full-fledged graphic user interface running under X Window, complete sources and documentation. Along with it we present TINA, an experimental project on operating system development, together with several other project proposals.

Automatic selection of instruction op-codes of low-power core processors

A methodology is presented for automatically determining an assignment of instruction op-codes that guarantees the minimisation of bit transitions occurring inside the registers of the pipeline stages involved in instruction fetching and decoding. The assignment of the binary patterns to the op-codes is driven by the statistics concerning instruction adjacency collected through instruction-level simulation of typical software applications. Therefore the technique is best exploited when applied to encode the instruction set of core processors and microcontrollers, since components of these types are commonly used to execute fixed portions of machine code within embedded systems. The effectiveness of the methodology is illustrated through experimental data obtained on a realistic case study, namely, the MIPS R4000 RISC microprocessor.

Random permutations on distributed, external and hierarchical memory

A simple randomized algorithm for generating a uniformly distributed random permutation of size n is investigated. It works in time O( n P + T comm( n P , P) + T prefix(P)) on P processors with high probability, where T comm ( k, P) is the time for randomly sending or receiving k elements on each processor and T prefix ( P) is the time for computing a prefix sum. The algorithm can be directly translated into an optimal external memory algorithm if fast memory for √ nB(1 + o(1)) + O( B) elements is available where B is the page size. Due to its simplicity, the same algorithm even outperforms the straightforward method on mainstream workstations if the cache is taken to be the fast memory and the main memory is treated like external memory. The algorithm is almost four times faster on a MIPS R10000 machine.

Informing memory operations

Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to address this problem successfully in specific situations. However, the generality of these software approaches has been limited because current architecturtes do not provide a fine-grained, low-overhead mechanism for observing and reacting to memory behavior directly. To fill this need, this article proposes a new class of memory operations calledinforming memory operations, which essentially consist of a memory operatin combined (either implicitly or explicitly) with a conditional branch-and-ink operation that is taken only if the reference suffers a cache miss. This article describes two different implementations of informing memory operations. One is based on acache-outcome condition code,and the other is based onlow-overhead traps.We find that modern in-order-issue and out-of-order-issue superscalar processors already contain the bulk of the necessary hardware support. We describe how a number of software-based memory optimizations can exploit informing memory operations to enhance performance, and we look at cache coherence with fine-grained access control as a case study. Our performance results demonstrate that the runtime overhead of invoking the informing mechanism on the Alpha 21164 and MIPS R10000 processors is generally small enough to provide considerable flexibility to hardware and software designers, and that the cache coherence application has improved performance compared to other current solutions. We believe that the inclusion of informing memory operations in future processors may spur even more innovative performance optimizations.

Avoiding secondary cache conflict misses in a real-time system

The performance of real-time systems (RTS) with large-scale direct-mapped secondary caches is largely dependent on the state of physical memory page allocation when the cache hit rate is not high. To overcome that problem, the author proposes two optimization methods for minimizing secondary cache conflict misses, assuming an RTS for which page allocation is not performed during a service, and evaluates these methods by simulations based on actual RTS trace data. The evaluations show a performance improvement of from 30% to 100% for secondary cache capacities ranging from 128 KB to 1 MB in a system that employs the MIPS R4000 processor. © 1998 Scripta Technica, Syst Comp Jpn, 29(4): 43–59, 1998

Avoiding secondary cache conflict misses in a real‐time system

The performance of real-time systems (RTS) with large-scale direct-mapped secondary caches is largely dependent on the state of physical memory page allocation when the cache hit rate is not high. To overcome that problem, the author proposes two optimization methods for minimizing secondary cache conflict misses, assuming an RTS for which page allocation is not performed during a service, and evaluates these methods by simulations based on actual RTS trace data. The evaluations show a performance improvement of from 30% to 100% for secondary cache capacities ranging from 128 KB to 1 MB in a system that employs the MIPS R4000 processor. © 1998 Scripta Technica, Syst Comp Jpn, 29(4): 43–59, 1998