Minority Carrier Generation Lifetime Research Articles

Evaluation of Minority Carrier Generation Lifetime for Oxide Semiconductors

In this study, the transfer characteristics of InGaZnO (IGZO) and InSnZnO (ISZO) thin-film transistors are compared using the minority carrier generation lifetime method. Capacitance-voltage and capacitance-time characteristics of IGZO- and ISZO-based capacitors with a p+-Si/SiO2/IGZO or ISZO structure were evaluated at a 100 kHz frequency. Although the intrinsic carrier concentrations of IGZO and ISZO films are on the order of ~10−7 cm−3, which is conjectured to result in a very low off-state drain current (ID,OFF), even as small as zero, a magnitude of 10−12 – 10−11 A for ID,OFF was measured in this study. We propose that this is due to the minority carriers, which are thermally generated from the channel defects. Furthermore, ISZO films exhibited faster transient capacitance characteristics compared to the IGZO films, which is associated with the amount of defect sites in the channel substrate. Thus, the lower transient time for the ISZO films is attributed to a larger number of oxygen vacancies in the channel layer than in IGZO films.

Investigating the transient response of Schottky barrier back-gated MoS2 transistors

Molybdenum disulfide (MoS2) MOSFETs have been widely reported to exhibit hysteresis behavior, which is usually attributed to charge trapping effects due to defective/sub-stoichiometric compositions in the material, or defects near, or at, the oxide/channel interfaces. It is also suggested that defective MoS2 transistors show current limitations caused by the Schottky barrier junctions formed at the contacts. Here, we report on the static and dynamic device response of back-gated MoS2 transistors directly fabricated on a SiO2/Si substrate using chemical vapor deposition synthesis, without film transfer, and standard CMOS optical lithography. The devices exhibit an atypical hysteresis in the transfer characteristics, as well as a delayed response in the formation of the conducting channel in response to voltage pulses applied to the back gate. Analysis of the output characteristic is consistent with two back-to-back Schottky diodes, allowing the Fermi level pinning position at the Ni/MoS2 source and drain contacts and blocking the MoS2 hole channel. Capacitance-voltage characterization demonstrates that the grown MoS2 thin film is p-type, resulting in a nominally-off, inversion mode, n-channel device. Analysis of the transient response and hysteresis as a function of device temperature, illumination and ambient conditions indicates that the dynamic response of the device is determined by the net charge in the MoS2 film combined with the minority carrier generation lifetime in the underlying silicon substrate. The work demonstrates the strong dependence of the device response time on substrate, temperature, illumination, and net charge in the MoS2 layer opening the possibility of applications in photo-detectors and sensors.

Inversion in the In0.53Ga0.47As metal-oxide-semiconductor system: Impact of the In0.53Ga0.47As doping concentration

In0.53Ga0.47As metal-oxide-semiconductor (MOS) capacitors with an Al2O3 gate oxide and a range of n and p-type In0.53Ga0.47As epitaxial concentrations were examined. Multi-frequency capacitance-voltage and conductance-voltage characterization exhibited minority carrier responses consistent with surface inversion. The measured minimum capacitance at high frequency (1 MHz) was in excellent agreement with the theoretical minimum capacitance calculated assuming an inverted surface. Minority carrier generation lifetimes, τg, extracted from experimentally measured transition frequencies, ωm, using physics based a.c. simulations, demonstrated a reduction in τg with increasing epitaxial doping concentration. The frequency scaled conductance, G/ω, in strong inversion allowed the estimation of accurate Cox values for these MOS devices.

Effect of forming gas annealing on the inversion response and minority carrier generation lifetime of n and p-In0.53Ga0.47As MOS capacitors

In0.53Ga0.47As MOS capacitors with a range of Al2O3 oxide thickness values were examined using multi-frequency capacitance–voltage and conductance–voltage characterization for n and p-type In0.53Ga0.47As epitaxial layers. The samples exhibited a minority carrier response consistent with surface inversion for both n and p-type In0.53Ga0.47As MOS structures. An equality between the peak magnitude of the frequency scaled conductance, G/ω, and the derivative of capacitance with frequency, −ωdC/dω in strong inversion allows estimation of accurate Cox values for the varying thickness MOS devices. Minority carrier generation lifetimes, τg, were extracted from the experimentally measured transition frequencies, ωm, through physics based a.c. simulations. It was observed that τg was reduced following a post-metallization 275°C forming gas anneal treatment over both n and p-In0.53Ga0.47As. This is indicative of an improvement in the In0.53Ga0.47As quality by means of hydrogen passivation of the mid-gap bulk defects responsible for the observed minority carrier response.

Capacitance and Conductance for an MOS System in Inversion, with Oxide Capacitance and Minority Carrier Lifetime Extractions

Experimental observations for the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As metal-oxide-semiconductor (MOS) system in inversion indicate that the measured capacitance (C) and conductance (G or G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ), are uniquely related through two functions of the alternating current angular frequency (ω). The peak value of the first function (G/ω) is equal to the peak value of the second function (-dC/dlog <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</sub> (ω) ≡ -ωdC/dω). Moreover, these peak values occur at the same angular frequency (ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ), that is, the transition frequency. The experimental observations are confirmed by physics-based simulations, and applying the equivalent circuit model for the MOS system in inversion, the functional relationship is also demonstrated mathematically and shown to be generally true for any MOS system in inversion. The functional relationship permits the discrimination between high interface state densities and genuine surface inversion. The two function peak values are found to be equal to C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /(2(C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> + C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> )) where C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> is the oxide capacitance per unit area and C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> is the semiconductor depletion capacitance in inversion. The equal peak values of the functions, and their observed symmetry relation about ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> on a logarithmic ω plot, opens a new route to experimentally determining C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> . Finally, knowing ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> permits the extraction of the minority carrier generation lifetime in the bulk of the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As layer.

Effect of Bias Temperature Stress on the Anti-Reflection HfO2 Layer in Complementary Metal Oxide Semiconductor Image Sensors

The effects of various electrical characteristics of HfO2 in CMOS image sensors on bias-thermal stress instability were evaluated. In this work, the HfO2 dielectric layer was used as the anti-reflection layer of image sensors because it had negative charges and could electrically form a p+ layer on a silicon photodiode surface. After the HfO2 layer was stressed with electric field 0.5 MV/cm, 200 °C, and 10 min, there was severe electrical degradation such as +18.8 V flatband voltage shift. In order to investigate this degradation, the oxide trap charges and border trap charges of the HfO2 layer were measured and calculated. Based on these results, the interface trap density and minority carrier generation lifetime, which are directly related to the dark current in CMOS image sensors, were measured. The interface trap density degraded from 4.5×1011 to 1.0×1012 cm-1 eV-1 and the generation lifetime also degraded from 983 to 17 µs after stress application. This trap generated degradation model is suggested for CMOS image sensors. Therefore, pre-stabilization of bias-thermal stress should be implemented to use the HfO2 layer in modern CMOS image sensors.

High-quality epitaxial Si growth at low temperatures by atmospheric pressure plasma CVD

We have studied the epitaxial Si growth on 4-inch-(001) Si wafers by atmospheric pressure plasma chemical vapor deposition (AP-PCVD) using a porous-carbon electrode. Defect-free growth of epitaxial Si is confirmed in the temperature range 470–570 °C by transmission electron microscopy. High minority carrier generation lifetime (2.0 ms) is observed in the Si film grown at 570 °C with a rate of 0.35 μm/min. In situ H 2 AP-plasma cleaning of the substrate surface is effective for eliminating O and C concentration peaks at the film/substrate interface. Effects of plasma heating and ion bombardment of the growing-film surface have been discussed.

Electrical characterization of thin SOI wafers using lateral MOS transient capacitance measurements

A novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime ( τ g) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor. The lateral MOS capacitors were fabricated on three kinds of thin SOI wafers. The crystal quality difference among these three wafers was clearly shown by the τ g measurement results and discussed from a viewpoint of SOI fabrication. The series resistance influence on the capacitance measurement for this lateral MOS capacitor was discussed in detail. The validity of this method was confirmed by comparing the intensities of photoluminescence signals due to electron–hole droplet in the band-edge emission.

Influence of dislocations in strained Si∕relaxed SiGe layers on n+∕p-junctions in a metal-oxide-semiconductor field-effect transistor technology

We present an investigation of junction leakage in highly doped n+∕p-junctions, fabricated in strained silicon/relaxed SiGe substrates. The leakage is shown to scale linearly with the threading dislocation density of the virtual substrate, which allows to estimate minority carrier generation lifetimes in good agreement with literature values. Even the highest-defective substrates in this work give a junction leakage density below 100mA∕cm2, and are not expected to significantly increase the power consumption of metal-oxide-semiconductor field-effect transistor (MOSFET) technologies. Threading dislocations will increase the junction leakage by ∼1nA in a small number of transistors in MOSFET circuits, but are not expected to have a negative impact on yield.

Evaluation of Interface States Density and Minority Carrier Generation Lifetime for Strained Si/SiGe Wafers Using Transient Capacitance Method

Interface states density (Nss) and minority carrier generation lifetime (τg) were evaluated in detail for strained Si/SiGe wafers by deep-level transient spectroscopy and metal-oxide-semiconductor transient capacitance methods. Nss shows a nondependence on strained Si thickness (dSi) within a critical thickness and a clear dependence on Ge fraction (Ge%). τg shows a strong dependence on both dSi and Ge%. The reasons for these dependences are discussed in detail.

Electrical characterization of strained Si∕SiGe wafers using transient capacitance measurements

Interface states density (Nss) and minority carrier generation lifetime (τg) were evaluated for strained Si(St-Si)∕SiGe wafers using deep level transient spectroscopy and metal-oxide-semiconductor transient capacitance methods. Nss shows an independence on St-Si thickness (dSi) and an obvious dependence on Ge fraction (Ge%). τg shows a strong dependence on both dSi and Ge%. The reasons of these dependencies are discussed in detail.

Annealing Effect on Boron High-Energy-Ion-Implantation-Induced Defects in Si

In this work, we investigate the annealing effect on defects in Si induced by boron high-energy (1.5 MeV) ion implantation with respect to implantation dose (1.1×1013 and 5×1013 cm-2) as well as annealing scheme [rapid thermal annealing (RTA) and furnace annealing (FA)]. The higher dose implantation resulted in more serious degradation of the minority carrier generation lifetime in the implanted layers. Also, the degree of lifetime recovery by either RTA or FA was very limited with the higher dose implantation, presumably due to the presence of the implantation-induced dislocations. The degradation of the lifetime in the lower dose-implanted sample could be significantly recovered by the annealing process, particularly the RTA scheme; this is presumably because RTA has a better ability to reduce the implantation-induced interstitials.

Negative-bias-temperature-instability in metal–insulator–semiconductor structures

We have demonstrated that negative-bias-temperature-instability (NBTI) significantly decreases the minority carrier generation lifetime as well as modifying the dominant source supplying minority carriers to the inversion layer at the semiconductor–insulator interface. This was manifested by an NBTI-induced shift in the deep-level-transient-spectroscopy (DLTS) peak signal associated with the inversion layer formation at the semiconductor–insulator interface at temperatures above room temperature to a lower temperature. In addition, we have observed that the DLTS inversion layer-related peak signal gradually shifted back, close to its pre-NBTI temperature position after a substantial time at zero bias-voltage and room temperature conditions had elapsed since the NBTI experiment. We have tentatively ascribed this recovery to a post-NBTI reaction at the semiconductor–insulator interface between unpassivated positively charged silicon dangling bonds and negatively charged hydrogen ions.

Investigation of thermal effect on electrical properties of Si0.887Ge0.113 and Si0.887−yGe0.113Cy films

Thermal effects on the bulk and interface electrical properties of Si0.887Ge0.113 and Si0.887−yGe0.113Cy films annealed at an oxidizing or inert ambient were investigated. We found that while annealing the Si0.887−yGe0.113Cy films at an oxidizing ambient reduced the C content significantly, a significant amount of SiC precipitates was found in films annealed in an inert ambient. The high interface state value of the Al–SiO2–Si0.887Ge0.113 capacitor resulted in a low minority carrier generation lifetime and a frequency dispersion behavior at the depletion region of such a device. A good agreement in the interface state values was obtained from the capacitance versus voltage and the deep level transient spectroscopy measurements performed on the Al–SiO2–Si0.887Ge0.113 capacitors. For the capacitors fabricated on Si0.887−yGe0.113Cy substrates, the significant increase in the apparent substrate doping level was attributed to the SiC precipitates in the film caused by the high temperature oxidation process. The capacitance versus frequency measurements showed the influence of interface state and bulk defects on the frequency dependence at the depletion and inversion regions of capacitors fabricated on Si0.887−yGe0.113Cy substrates.

Irradiation effects of proton bombarded poly-Si/SiO 2/Si structure

Characteristics of poly-Si/SiO 2/Si structure have been studied under influence of proton irradiation at energies of 100, 200, 600 keV and 2 MeV and doses of 1 × 10 9−3 × 10 12 cm −2. Minority carrier generation lifetime was sensitive to doses as low as 1 × 10 9 cm −2. A method to extract the created defect profiles using C– V and C– t measurements in the ion bombarded MOS structures has been suggested. Effective charge changes in the MOS capacitor Si/SiO 2 interface and leakage currents have been investigated. Results can be used in studies of spacecraft microelectronics and lifetime control of devices.

Generation lifetime improvement on MOS capacitor by fast neutron enhanced intrinsic gettering technique

Minority-carrier generation lifetime of MOS capacitors was improved by performing a fast neutron enhanced intrinsic gettering (NEIG) technique on the Czochralski (CZ) silicon wafers on which the devices were fabricated. With NEIG, the minority-carrier generation lifetime was possibly to be elevated high to 822μs.It was shown that the NEIG method can be used to substitute for the conventional three-step H–L–H (H: high temperature annealing for a long time, L: low temperature annealing for a long time) intrinsic gettering method to have equivalent or better electrical properties but saving the processing time.

Investigation of electrically active defects in Si-based semiconductor structures

A group of several methods for detailed investigation of electrically active defects (EAD) and their properties in insulator-semiconductor (IS) and metal-insulator-semiconductor (MIS) structures has been developed. It consists of different ways of analyzing EAD including precision measurements of local electrophysical properties of IS structures, mapping of defects in IS structures by means of nematic liquid crystals (NLC), application of scanning electron microscopy (SEM) in electron beam induced current (EBIC) mode for localization of EAD in the semiconductor of MIS structures. Local electrophysical measurements are carried out by using dynamic unsteady-state current–voltage characteristics (DUCVC) and their modifications which have higher sensitivity to detection of generation processes in MIS structures as compared with ordinary capacitance–voltage characteristics. Depth distributions of bulk generation lifetime of minority carriers in semiconductors, obtained by the DUCVC method, reflect normalized EAD profiles near the IS interface. The NLC method is nondestructive and makes possible to analyze lateral distribution of defects with high local conductivity in insulating films. It was shown that in the case of thin SiO 2 films on silicon EAD at semiconductor surface are also revealed by the NLC method. As a result determination of EAD coordinates opens possibility for further detailed investigation of separate EAD properties by the DUCVC method using local mercury probe 5 μm in size. Special MIS gated p–n junctions have been used for mapping of EAD with high recombination velocity in semiconductor under the metal or polysilicon gates. Combination of the described methods was applied for investigation of local EAD properties of Si-based structures, which are used for fabrication of integrated circuits. The influence of gettering on EAD concentration in Si and SiO 2 has been investigated.

Bulk generation lifetime studies in semiconductor structures with nonuniform distribution of electrically active defects in silicon

A method for investigation of bulk generation lifetime of minority carriers τ g and their profiles in semiconductor of electron devices has been developed. It is based on combined application of dynamic unsteady-state current–voltage characteristics (DUCVC) and high-frequency capacitance–voltage characteristics (HFCVC) of metal–insulator–semiconductor (MIS) structures.The main advantage of DUCVC over other methods consists in higher sensitivity to registration of generation processes, possibility of direct determination of surface potential in MIS structures and experimental simplicity. Combined application of two kinds of stated characteristics eliminates doping concentration N d from τ g analysis in case of constant N d value in semiconductor. Thus the accuracy of τ g determination increases. If the doping concentration is constant and known, τ g is obtained only from DUCVC analysis. Bulk generation lifetime profiles have been investigated in Si–SiO 2 structures after formation of an internal getter near subsurface region of silicon. Effect of hydrogen annealings on formation of defect-free zone in silicon was investigated. Nonuniform distribution of electrically active defects (EAD) in silicon has been revealed.

Intrinsic Gettering in Nitrogen-Doped and Hydrogen-Annealed Czochralski-Grown Silicon Wafers

The properties of nitrogen-doped and hydrogen-annealed Czochralski-grown silicon (NHA-CZ-Si) wafers were investigated in this study. The quality of the subsurface was investigated by monitoring the generation lifetime of minority carriers, as measured by the capacitance-time measurements of a metal oxide silicon capacitor (MOS C-t). The intrinsic gettering (IG) ability was investigated by determining the nickel concentration on the surface and in the subsurface as measured by graphite furnace atomic absorption spectrometry (GFAAS) after the wafer was deliberately contaminated with nickel. From the results obtained, the generation lifetimes of these NHA-CZ-Si wafers were determined to be almost the same as, or a little longer than those of epitaxial wafers, and the IG ability was proportional to the total volume of oxygen precipitates [i.e., bulk micro defects (BMDs)], which was influenced by the oxygen and nitrogen concentrations in the wafers. Therefore, it is suggested that the subsurface of the NHA-CZ-Si wafers is of good quality and the IG capacity is controllable by the nitrogen and oxygen concentrations in the wafers.

Electrical Characterization of Copper Penetration Effects in the Gate Oxide of MOS Devices

ABSTRACTCopper penetration in thermal oxide was investigated using MOS capacitors by annealing at 450 °C and bias-temperature stress at 250 °C. Copper induces minority carrier generation lifetime decay and oxide leakage current increase. Degradation is enhanced by capacitor biasing, which confirms the role of Cu+ ions. The current-voltage characteristics are consistent with Poole-Frenkel model, showing that electron transport proceeds through traps created in the oxide bulk by copper. When a negative bias is applied, copper traps are removed from oxide near SiO2-Si interface and the leakage current is cancelled but the generation lifetime remains nil, copper contamination of silicon surface being not removed.None of these effects are observed when the copper gate is separated from oxide by a 10 nm TiN layer, proving that this material is an efficient barrier against copper diffusion at 450°C.