Minimum Interconnection Research Articles

Optimal configuration of hydrogen storage capacity of hybrid microgrid considering peak regulation and frequency modulation requirements

This study proposes an innovative hydrogen storage capacity optimization configuration method that considers multiple demand factors, addressing the issue that traditional methods for optimizing hydrogen storage capacity in hybrid microgrids cannot simultaneously balance economic efficiency and grid connection quality. This method breaks through the traditional optimization framework and adopts a double-layer optimization model, combining the peak shaving operation cost of the hybrid microgrid with the interactive power deviation and power fluctuation penalty terms of the interconnection line during the frequency regulation stage, achieving dual optimization of economy and grid connection quality. Through precise mathematical modeling and efficient optimization algorithms, we have successfully obtained the minimum operating cost corresponding to the minimum power fluctuation, the minimum interconnection line interactive power deviation penalty term, and the optimal hydrogen storage capacity configuration scheme. Identify two typical days through cluster analysis. Option 1 (considering peak shaving, frequency regulation, and hydrogen electrolysis) has the lowest net load and a total operating cost of 3.0331 million yuan, which is better than Option 2 (3.0973 million yuan) and Option 3 (5.0398 million yuan). This plan effectively reduces wind and solar power waste, shortens the operating time of thermal power units, and demonstrates the rationality and economy of optimizing hydrogen storage capacity configuration.

Approaches to Heterogeneous Integration for Millimeter-Wave Applications

Introduction. Enhanced performance of electronic systems can be achieved by heterogeneous integration of different semiconductor technologies. The benefits of heterogeneous integration become obvious when close connections between the devices are provided. The development of integration approaches, enabling functionality and improved performance, appears a relevant task for modern microwave microelectronics.Aim. Review of state-of-the-art and promising heterogeneous integration concepts and techniques in microwave microelectronics.Materials and methods. Eight integration approaches that ensure the connection of devices based on different semiconductor technologies for microwave frequencies are considered: monolithic heterogeneous integration, wafer bonding, micro-transfer printing, embedded chip assembly, print additive manufacturing, wire bonding, flip-chip, and hotvia. The integration approaches are analyzed in terms of their implementation specifics, advantages and disadvantages.Results. Monolithic heterogeneous integration and wafer bonding, as well as micro-transfer printing, despite the minimum interconnections, have a number of fundamental limitations. These limitations are related to the compatibility of various semiconductor technologies and the necessity of high technological capabilities. The technology of embedded chip assembly enables the variability of implementation techniques, which makes it possible to provide unique characteristics, e.g., due to the integration of magnetic materials. However, this approach is associated with a high complexity of integration technological processes. Flip-chip integration ensures minimal interconnect losses due to bump miniaturization. Hot-via, as a modification of flip-chip, provides for a better compatibility with microstrip type circuitry. Their further improvement and mass application largely depends on the development of technologies for the formation of low-pitch interconnections.Conclusion. The development of close integration approaches in microwave microelectronics is proceeding both in the monolithic direction, i.e., monolithic heterogeneous integration wafer bonding, as well as in the quasi-monolithic direction, i.e., micro-transfer printing, embedded chip assembly, print additive manufacturing, flip-chip, and hot-via. The conducted comparative analysis of the presented methods has practical application.

Development of a large-area, light-weight module using the MALTA monolithic pixel detector

The MALTA pixel chip is a 2 cm × 2 cm large monolithic pixel detector developed in the Tower 180 nm imaging process. The chip contains four CMOS transceiver blocks at its sides which allow chip-to-chip data transfer. The power pads are located mainly at the side edges on the chip which allows for chip-to-chip power transmission. The MALTA chip has been used to study module assembly using different interconnection techniques to transmit data and power from chip to chip and to minimise the overall material budget. Several 2-chip and 4-chip modules have been assembled using standard wire bonding, ACF (Anisotropic Conductive Films) and laser reflow interconnection techniques. These proceedings will summarise the experience with the different interconnection techniques and performance tests of MALTA modules with 2 and 4 chips tested in a cosmic muon telescope. They will also show first results on the effect of serial power tests on chip performance as well as the impact of the different interconnection techniques and the results of mechanical tests. Finally, a conceptual study for a flex based ultra-light weight monolithic pixel module based on the MALTA chip with minimum interconnections is presented.

Active Shielding of MWCNT Bundle Interconnects: An Efficient Approach to Cancellation of Crosstalk-Induced Functional Failures in Ternary Logic

This study presents an efficient geometry for active shielding of multiwalled carbon nanotube (MWCNT) bundle interconnects which cancels the crosstalk-induced functional failures in ternary logic. In this geometry, MWCNT bundles are used innovatively as shields on both sides of the signal transmission line to reduce the crosstalk effects while maintaining the minimum interconnect pitch. Simulations are performed using HSPICE for intermediate and global interconnects in ternary logic at 14-nm node. The results indicate that the crosstalk-induced functional failure in ternary logic is omitted by using the proposed structure. Moreover, according to the results, our proposed geometry reduces the crosstalk noise peak as compared to the widened MWCNT bundles, distanced MWCNT bundles and Cu interconnects on average by 41%, 44%, and 61% for the intermediate interconnects and 61%, 46%, and 74% for the global interconnects, respectively, without any considerable power consumption penalties.

Review Paper on Placement Algorithms

Placement is a step considered after floor planning in FPGA flow in ASIC. It defines the location of logic cells within functional blocks and to minimize the routing length. We adjust the logic cells in this way so that minimum interconnect length, area and density are used. In this paper we will discuss some of methods of placement of logic cells.

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

With the increased density of three-dimensional (3D) processor arrays, faults can potentially occur quite often due to power overheating during massively parallel computing. In order to achieve fault-tolerance under such a scenario, an effective way is to find an as large as possible logical fault-free subarray of $m^{\prime }\;\times\;$ $n^{\prime }\;\times\;$ $h^{\prime }$ from a faulty array of $m\;\times\;$ $n\;\times\;$ $h$ ( $m^{\prime }$ $\;\le\;$ $m,n^{\prime }$ $\;\le\;$ $n, h^{\prime }$ $\;\le\;$ $h$ ), such that an original application can still work on the $m^{\prime }\;\times\;$ $n^{\prime }\;\times\;$ $h^{\prime }$ subarray. This paper investigates the problem of constructing maximum fault-free subarrays with minimum interconnection length from 3D arrays with faults. First, we prove that constructing maximum logical array (MLA) is NP-complete. We propose a linear-time algorithm which is capable of producing an MLA for the problem with the constraint of selected indexes. Second, we prove that minimizing the interconnection length (inter-length) of the MLA is NP-hard. We propose an efficient heuristic which significantly reduces the inter-length by revising each logical plane of the MLA. This leads to the reduction of communication cost, capacitance and dynamic power dissipation. In addition, we propose a lower bound for the inter-length of the MLA to evaluate the proposed algorithms. Simulation results show that, the size of logical array can be improved up to 62.6 percent in average, and the inter-length redundancy can be reduced by 22.7 percent in average, compared to the state-of-the-art, for all cases considered.

Silicon-Embedded RF Micro-Inductors for Ultra-Compact RF Subsystems

Advances in 2.5D and 3D integration technologies are enabling ultra-compact multi-chip modules. In this abstract, we present the design, fabrication, and experimental characterization of RF inductors microfabricated inside deep silicon recesses. Because silicon is often used as a substrate of packaging material for 3D integration and microelectromechanical systems (MEMS), developing microfabrication technologies to embed passive components in the unused volume of the silicon package is a promising approach to realize ultra-compact RF subsystems. Inductors and capacitors are critical in dc-bias circuits for MMICs in order to suppress low-frequency oscillations. Because it is particularly important to have these passive components as close to the MMIC as possible with minimum interconnection parasitics, silicon-embedded passives are an attractive solution. Further, silicon-embedded passives can potentially reduce the overall volume of RF subsystems when compared to modules using discrete passives. Although inductors inside the volume of silicon wafers have previously been reported, they typically operated in the 1–200 MHz frequency range, mostly featuring inductors with wide (50–100 μm) conductors and wide (50–100 μm) interconductor gaps due to fabrication limitations. We first explored process limitations to fabricate structural and electrical features inside 75 to 100-μm-deep silicon cavities. The cavities were etched into the silicon using deep reactive ion etching. Inside these recesses, we demonstrated the fabrication of thin (0.2 μm) and thick (5 μm) gold patterns with 3 μm resolution using lift-off and electroplating processes, respectively. The lift-off process used an image reversal technique, and the plated gold conductors were fabricated through a 6.5-μm-thick photoresist mold. The feature sizes ranged from 3 to 50 μm. For photoresist exposure, an i-line Canon stepper was utilized, and configured specifically to focus at the bottom of the cavities, a key process requirement to achieve high-resolution features. These microfabrication results enabled the design of high-performance RF inductors, which will be discussed in the next section. In addition, we demonstrated the fabrication of 30-μm-deep 3-μm-diameter silicon-etched features inside these cavities, a stepping stone towards achieving high-capacitance-density integrated trench capacitors embedded inside silicon cavities. The silicon-embedded RF inductors were microfabricated on 500-μm-thick high-resistivity (ρ > 20,000 Ω.cm) silicon wafers. First, 75-μm-deep cavities were etched using DRIE. Various two-port coplanar waveguide (CPW) inductor designs were microfabricated. The inductor microfabrication relied on sputtered titanium/gold seed layers, thick AZ4620 photoresist molds, and three 5-μm-thick electroplated gold layers stacked on top of each other to define the inductor conductor and connections. By using a combination of three electroplated layers, high-power-handling low-loss inductors were fabricated. Measurements were performed on a RF probe station, with on-wafer calibration structures. The losses associated with the CPW launchers were de-embedded prior to inductor measurements, and inductor quality factor greater than 40 was measured on various inductors with inductance of approximately 1 nH, and self-resonant frequency at 30 GHz. These results were in agreement with models performed using SONNET simulation package, and are comparable with than that of inductors fabricated on planar silicon wafers.

Electrical behavior of Au–Ge eutectic solder under aging for solder bump application in high temperature Electronics

As deep earth oil exploration transits into deeper earth, it faces challenges in producing reliable microelectronics devices and sensors that will not degrade at high temperature, especially those related to packaging materials and assembly of the devices. It has been reported that the mechanical performance of a high temperature Au–Ge eutectic solder is able to fulfill the minimum interconnection properties specified by the oil and gas exploration industry. However, the impact of thermal aging to Au–Ge eutectic solder’s electrical property is not clear. In this work, it is observed that the bulk Au–Ge electrical resistivity decreased initially with thermal aging and then saturated. This effect is mainly contributed by the grain growth of Au, which results in a reduction in grain boundaries, as well as coarsening of the Ge phases. On the other hand, study on the microstructure and electrical resistance of Au–Ge solder bump joint after aging shows that the electrical resistance increased. The increase in resistance is contributed mainly by the NiGe and Ni5Ge3 intermetallic compounds growth, which also led to a degradation in the Ni(P) barrier layer.

A novel interconnect-optimal power model considering self-heating effect

Based on the distributed interconnect power model, a novel dynamic power model is presented in this paper, in which a non-uniform interconnection structure is adopted. This model takes into account the self-heating effect and is constrained by delay, bandwidth, area, minimum interconnect width and minimum interconnect space. The validity of the proposed model is verified by 90 nm and 65 nm complementary metal-oxide semiconductor technology. The results indicate that the proposed model can cause a power consumption reduction as high as 35%, and yet the delay, area, and bandwidth are not deteriorated, when compared with the conventional power model. The proposed optimal model can be used for designing large scale interconnect router and clock network in network-on-chip structure.

Advanced architecture optimisation and performance analysis of a reconfigurable grid ALU processor

In the billion transistor era only a few architectural approaches propose new paths to improve the execution of conventional sequential instruction streams. Many legacy applications could profit from processors that are able to speed-up the execution of sequential applications beyond the performance of current superscalar processors. The Grid arithmetic logic unit (ALU) Processor (GAP) accelerates conventional sequential instruction streams without the need for recompilation. The GAP comprises a processor front-end similar to that of a superscalar processor extended by a configuration unit and a two-dimensional array of functional units that forms the execution unit. Instruction sequences are mapped dynamically into the array by the configuration unit so that they form the dataflow graph of the sequence. This study shows a performance evaluation of the GAP architecture with different array dimensions as well as its performance using a simplified interconnection network. GAP outperforms an out-of-order superscalar processor by a maximum of factor 2 with a complete crossbar interconnect between two array rows. Reducing the interconnection network to the minimum shows a maximum performance drawback of 10% for only a particular configuration and a single benchmark. In general, the slowdown is less than 2% for the minimum interconnect (two buses) and about 0.02% if three interconnection buses are used.

Robust Design of High-Speed Interconnects Based on an MWCNT

A robust design of the propagation characteristics of interconnect structures based on multiwall carbon nanotubes (MWCNTs) is carried out. The study allows us to identify the minimum number of shells N of the MWCNT able to guarantee that the time delay at 50% outperforms the Cu-based solution for the upcoming technology nodes, taking into account the uncertainties affecting other geometrical and physical parameters of the device. Such an investigation is carried out in the most severe conditions for the MWCNTs-based device, i.e., for short and thin wire structures, starting from the minimum interconnect length for which the MWCNT outperforms the Cu-based solution. A worst case polynomial expression of the time delay as a function of the number of the shells of the MWCNT, obtained on the basis of the equivalent single conductor model of the nano-interconnect, is adopted for the optimization procedure. The minimum number of shells that lead to outperform the Cu-based solution is determined by the use of an approach relying on a particular application of the interval analysis to find the upper bound of the performance function. The quality of the results is checked by a Monte Carlo analysis.

Judicious generation of alternative water network designs with manual evolution strategy

This study is aimed to judiciously generate the desired alternative configurations of a given single-contaminant water-using system under the constraints of minimum freshwater usage, minimum match number and minimum total throughput. A generalized source-shift procedure is proposed for this purpose, which can be applied manually by evolution from a preliminary network which requires minimum freshwater usage. Systematic implementation guidelines are also provided to perform the evolution steps. In addition, the minimum interconnection number can be estimated in advance and the total number of promising alternative solutions can also be determined a priori. Six examples are presented in this paper to demonstrate the effectiveness and benefits of applying our method.

Effect of dummy vias on interconnect temperature variation

The number of the dummy via can significantly affect the interconnect average temperature. This paper explores the modeling of the interconnect average temperature in the presence of multiple dummy vias. The proposed model incorporates the multi-via effect into the effective thermal conductivity of the interlayer dielectric (ILD) to obtain accurate results. Using different ILDs, the multi-via effect is analyzed and discussed. Also, the extended applications of the multi-via effect are presented in this paper to obtain the minimum interconnect average temperature increase with a given via separation or number. This study suggests that the multi-via effect should be accounted for in integrated circuits design to optimize the performance and design accuracy of integrated circuits.

Evolution of Water-using Networks with Multiple Contaminants

A systematic procedure is outlined in this paper to evolve a preliminary water-using network into a simpler one while incurring the lowest penalty in freshwater usage. The minimum interconnection number is first targeted on the basis of graph theory and then, three effective evolution strategies are applied to achieve this goal. The proposed procedure can be easily realized with the help of Microsoft Office Excel. An example is presented to illustrate the evolution procedure and demonstrate its effectiveness.

Heuristic evolution strategies for simplifying water-using networks with multiple contaminants

In designing a realistic water-using network with more than one contaminant, it is often desirable to obtain a simple structure so as to achieve high levels of controllability, operability, and safety. Based on any given preliminary design, the proposed heuristic evolution procedure can be systematically applied to produce an improved network with fewer interconnections, less total throughput and near minimum freshwater usage. Specifically, the minimum interconnection number is first targeted on the basis of graph theory and, then, three basic evolution strategies, i.e., loop breakage, two-source shift and path relaxation, can be utilized to strive for the number target. The required calculations in this procedure can be easily realized with Microsoft Office Excel or a hand calculator. Two examples are presented in this paper to illustrate the implementation steps and to demonstrate the effectiveness of the proposed approach.

Performance analysis and comparison of a minimum interconnections direct storage model with traditional neural bidirectional memories

This study proposes an efficient and improved model of a direct storage bidirectional memory, improved bidirectional associative memory (IBAM), and emphasises the use of nanotechnology for efficient implementation of such large-scale neural network structures at a considerable lower cost reduced complexity, and less area required for implementation. This memory model directly stores the X and Y associated sets of M bipolar binary vectors in the form of (MxN(x)) and (MxN(y)) memory matrices, requires O(N) or about 30% of interconnections with weight strength ranging between +/-1, and is computationally very efficient as compared to sequential, intraconnected and other bidirectional associative memory (BAM) models of outer-product type that require O(N(2)) complex interconnections with weight strength ranging between +/-M. It is shown that it is functionally equivalent to and possesses all attributes of a BAM of outer-product type, and yet it is simple and robust in structure, very large scale integration (VLSI), optical and nanotechnology realisable, modular and expandable neural network bidirectional associative memory model in which the addition or deletion of a pair of vectors does not require changes in the strength of interconnections of the entire memory matrix. The analysis of retrieval process, signal-to-noise ratio, storage capacity and stability of the proposed model as well as of the traditional BAM has been carried out. Constraints on and characteristics of unipolar and bipolar binaries for improved storage and retrieval are discussed. The simulation results show that it has log(e) N times higher storage capacity, superior performance, faster convergence and retrieval time, when compared to traditional sequential and intraconnected bidirectional memories.

OPTIMIZING CIRCUIT PARTITIONING BY IMPLEMENTING DATA MINING AND VHDL TOOLS PERTINENT TO VLSI DESIGN

The relevance of VLSI in performance computing, telecommunications, and consumer electronics has been expanding progressively, and at a very hasty pace. In order to build complex digital logic circuits it is often essential to sub-divide multi–million transistors design into manageable pieces. Circuit partitioning is a general approach used to solve problems that are too large and complex to be handled at once. In partitioning, the problem is divided into small and manageable parts recursively, until the required complexity level is reached. In the area of VLSI, circuit complexity is rapidly multiplying, together with the reducing chip sizes; the integrated chips being produced today are highly sophisticated. There are many diverse problems that occur during the development phase of an IC that can be solved by using circuit partitioning which aims at obtaining the sub circuits with minimum interconnections between them. This paper aims at circuit partitioning using clustering technique by applying two clustering algorithms K-Means and PAM(Partitioning around mediods). These two algorithms were tested on a BCD to Seven Segment Code Converter circuit consisting of eight nodes and also were tested on a circuit consisting of 15 nodes. The two algorithms were implemented on VHDL. The tested results show that PAM yield better subcircuits than K-Means.

Temporal Partitioning Data Flow Graphs for Dynamically Reconfigurable Computing

FPGA-based configurable computing machines are evolving rapidly in large signal processing applications due to flexibility and high performance. In this paper, given a reconfigurable processing unit (RPU) with a logic capacity of A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RPU</sub> and a computational task represented by a data flow graph G = (V, E, W), we propose a network flow-based multiway task partitioning algorithm to minimize communication costs for temporal partitioning. The proposed algorithm obtains an optimal solution with minimum interconnection under area constraints. The optimal solution is a cut set. In our approach, two techniques are applied. In the initial partition, any feasible min-cut is produced by the proposed network flow-based algorithm, so a set of feasible min-cuts is obtained. From the feasible solutions, the scheduling technique selects an optimal global solution.

A bundle of woe [power markets

The aim is to give real choice for EU energy users, whether citizens or businesses, and to trigger the huge investments needed in energy. The single market is good not just for competitiveness, but also sustainability and security. The competition sector enquiry and the internal market communication show that further action is required to deliver these aims through a clearer separation of energy production from energy distribution. It also calls for stronger independent regulatory control, taking into account the European market, as well as national measures to deliver on the European Union's target of 10 per cent minimum interconnection levels, by identifying key bottlenecks and appointing coordinators.

Improved genetic algorithm for VLSI floorplan design with non-slicing structure

Floorplan design is an important engineering problem. This problem can be modeled as a combinatorial optimization problem, in which a given set of rectangles in floorplan must be arranged. The goal is to find the arrangement with minimum area and minimum interconnection. Floorplans can be classified into slicing structure and non-slicing structure problems. In both problem types, it is difficult to obtain a true optimal solution in a time that could be used in practice. We proposed the new immune algorithm for optimization of the slicing structure problem in the past. In this paper, we focus on and analyze the improved points considered to be especially effective, and propose a new genetic algorithm for the non-slicing structure problem. The proposed method is compared with existing methods using well-known benchmark problems.