Minimal Hardware Research Articles

The Use of Headless Screws in the Setting of an Acute Posterior Calcaneal Avulsion Fracture in the Pediatric Population: A Case Report

Background: Sever’s is the most common cause of heel pain in the pediatric population and increases the risk of calcaneal apophyseal avulsion fractures. This is an uncommon fracture that faces problems with tenuous soft tissue coverage and high shear forces at the fracture site. Multiple fixation techniques have been employed in addressing this injury, with no one method standing out as superior. Case Presentation: We present a case of a 13-year-old male with a calcaneal apophyseal avulsion fracture in which cannulated headless compression screws were used for fixation. This was found to provide adequate compression across the fracture with minimal hardware prominence. This also allowed for the injection of radiopaque solution through the cannulated screw to rule out subtalar intraarticular penetration. We believe this represents a novel method of addressing these injuries. Conclusion: Cannulated headless compression screws are a suitable fixation technique for pediatric apophyseal avulsion fractures that provide the added benefit of assessment of intra-articular penetration of the subtalar joint by the injection of radiopaque solution through the cannulated screw.

ALGORITHM OF RANDOM START PHASE CORRECTION AND FREQUENCY OFFSET IN THE COMMUNICATION SYSTEM WITH THE QUADRATURE MODULATION

The goal of the work is to find a solution, realization, and modelling of the algorithm for the compensation of a start random phase error of a quadrature signal, which began at the input of the receiver’s digital part. This algorithm also solves the problem of carrier frequency error offset. These errors have enough values for the lock-band of Costas PLL using minimum hardware resources. To complete this task, the realization and modelling algorithm problems of phase and frequency offset error corrections in Matlab Simulink IDE, arising from Costas PLL, were solved. This algorithm sets values errors for Costas PLL work stability. From the results of calculation and modelling obtained in the article, it follows that the developed model of the receiving path completely eliminates the probability of the error of a random initial phase and frequency offset in the receiver model of a QPSK signal, before the PLL loop is switched on, which significantly reduces the time of readiness for operation of this model.

VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity Processors

Modern-day graph workloads operate on huge graphs through pointer chasing which leads to high last-level cache (LLC) miss rates and limited memory-level parallelism (MLP). Simultaneous Multi-Threading (SMT) effectively hides the memory access latencies for multi-threaded graph workloads provided that sufficient threads are supported in hardware. Unfortunately, providing a sufficiently large number of physical threads incurs an unjustifiably high hardware cost for commodity SMT processors which typically implement only two physical hardware threads. Ideally, we would like to achieve aggressive-SMT performance when running graph workloads on modest commodity processors. In this paper, we propose Virtualized Multi-Threading (VMT), a low-overhead multi-threading paradigm for accelerating graph workloads on commodity processors. Unlike prior multi-threading paradigms, VMT virtualizes both the physical hardware threads and the architecture state: VMT maps a large number of logical software threads to a small number of physical hardware threads, while maintaining the architecture state of the logical threads in the processor's cache hierarchy. Implemented on top of a quad-core 2-way SMT processor, VMT achieves an average speedup of 1.74× for a set of representative graph workloads, while incurring minimal hardware cost (195 bytes per core to support up to 32 logical threads). VMT's low hardware cost paves the way for implementation in commodity processors.

Multiplication and Accumulation Co-Optimization for Low Complexity FIR Filter Implementation

In multiplierless finite impulse response (FIR) filters, the product accumulation block (PAB) could be the major contributor to hardware complexity, especially for high-order filters. In this paper, an optimization scheme where the constant multiplication block and the PAB are jointly optimized at the bit-level is proposed to minimize the hardware complexity. In the proposed joint optimization, the multiple constant multiplications (MCM) block is rearranged into several MCM sub-blocks. The products are summed locally before accumulation to reduce the word-length of the structural adders. It is shown that the symmetric property of linear phase FIR filters can be utilized in some cases to further reduce the complexity of the constant multiplications. Quantitative analyses are also presented to study the relationship between the optimum group size and the coefficient values as well as the filter orders. It is shown that there is no fixed optimum structure for filters with different coefficient word-lengths and filter orders, and each filter needs to be optimized specifically to achieve the minimum hardware complexity. Implementation results are presented to validate the effectiveness of the proposed method.

Globally Accessible Distributed Data Sharing (GADDS): a decentralized FAIR platform to facilitate data sharing in the life sciences.

MotivationTechnical advances have revolutionized the life sciences and researchers commonly face challenges associated with handling large amounts of heterogeneous digital data. The Findable, Accessible, Interoperable and Reusable (FAIR) principles provide a framework to support effective data management. However, implementing this framework is beyond the means of most researchers in terms of resources and expertise, requiring awareness of metadata, policies, community agreements and other factors such as vocabularies and ontologies.ResultsWe have developed the Globally Accessible Distributed Data Sharing (GADDS) platform to facilitate FAIR-like data-sharing in cross-disciplinary research collaborations. The platform consists of (i) a blockchain-based metadata quality control system, (ii) a private cloud-like storage system and (iii) a version control system. GADDS is built with containerized technologies, providing minimal hardware standards and easing scalability, and offers decentralized trust via transparency of metadata, facilitating data exchange and collaboration. As a use case, we provide an example implementation in engineered living material technology within the Hybrid Technology Hub at the University of Oslo.Availability and implementationDemo version available at https://github.com/pavelvazquez/GADDS.Supplementary information Supplementary data are available at Bioinformatics online.

In situ process quality monitoring and defect detection for direct metal laser melting

Quality control and quality assurance are challenges in direct metal laser melting (DMLM). Intermittent machine diagnostics and downstream part inspections catch problems after undue cost has been incurred processing defective parts. In this paper we demonstrate two methodologies for in-process fault detection and part quality prediction that leverage existing commercial DMLM systems with minimal hardware modification. Novel features were derived from the time series of common photodiode sensors along with standard machine control signals. In one methodology, a Bayesian approach attributes measurements to one of multiple process states as a means of classifying process deviations. In a second approach, a least squares regression model predicts severity of certain material defects.

Inclusive Improvisation: Exploring the Line between Listening and Playing Music

The field of Accessible Digital Musical Instruments (ADMIs) is growing rapidly, with instrument designers recognising that adaptations to existing Digital Musical Instruments (DMIs) can foster inclusive music making. ADMIs offer opportunities to engage with a wider range of sounds than acoustic instruments. Furthermore, gestural ADMIs free the music maker from relying on screen, keyboard, and mouse-based interfaces for engaging with these sounds. This brings greater opportunities for exploration, improvisation, empowerment, and flow through music making for people with disability and the communities of practice they are part of. This article argues that developing ADMIs from existing DMIs can speed up the process and allow for more immediate access for those with diverse needs. It presents three case studies of a gestural DMI, originally designed by the first author for his own creative practice, played by people with disability in diverse contexts. The article shows that system-based considerations that enabled an expert percussionist to achieve virtuoso performances with the instrument required minimal hardware and software changes to facilitate greater inclusivity. Understanding the needs of players and customising the system-based movement to sound mappings was of far greater importance in making the instrument accessible.

Design Synthesis of a Robotic Uniaxial Torque Device for Orthopedic Haptic Simulation

Abstract Robotic devices are commonly used in surgical simulators to provide tactile, or haptic, feedback. They can provide customized feedback that can be rapidly modified with minimal hardware changes in comparison to nonrobotic systems. This work describes the design, development, and evaluation of one such tool: a novel uniaxial torque haptic device for a surgical training simulator. The objective of the work was to design a single connection haptic device that could augment an existing six degree-of-freedom haptic device to mimic a Concorde Clear vacuum curette. Design and evaluations focused on the tool's ability to deliver adequate torque, imitate a surgical tool, and be integrated into the haptic device. Twenty-nine surgeons tested the tool in the simulator and evaluated it via a questionnaire. The device was found to deliver the 800 N⋅mm of torque necessary to mimic an orthopedic procedure. Surgeons found it accurately imitated surgical tools physical appearance and maneuverability, scoring them 3.9 ± 1.0 and 3.3 ± 1.2, respectively, on a 1–5 Likert scale. By virtue of the functionality necessary for testing and evaluation, the device could be connected to the haptic device for mechanical and electrical engagement. This device is a step forward in the field of augmentable haptic devices for surgical simulation. By changing the number of robotically controlled degrees-of-freedom of a haptic device, existing devices can be tuned to meet the demands of a particular simulator, which has the potential to improve surgeon training standards.

FAS-A Fully Actuated Segment for Tendon-Driven Continuum Robots.

We propose a segment design that combines two distinct characteristics of tendon-driven continuum robots, i.e. variable length and non-straight tendon routing, into a single segment by enabling rotation of its backbone. As a result, this segment can vary its helical tendon routing and has four degrees-of-freedom, while maintaining a small-scale design with an overall outer diameter of 7 mm thanks to an extrinsic actuation principle. In simulation and on prototypes, we observe improved motion capabilities, as evidenced by position redundancy and follow-the-leader deployment along spatially tortuous paths. To demonstrate the latter on a physical prototype, a simple, yet effective area-based error measure for follow-the-leader deployment is proposed to evaluate the performance. Furthermore, we derive a static model which is used to underpin the observed motion capabilities. In summary, our segment design extends previous designs with minimal hardware overhead, while either archiving similar accuracy in position errors and planar follow-the-leader deployment, or exhibiting superior motion capabilities due to position redundancy and spatial follow-the-leader deployment.

On‐Site Preparation of Natural Deep Eutectic Solvents Using Solar Energy

AbstractNatural Deep Eutectic Solvents (NADES) are currently one of the greenest solvents for both academic and industrial purposes. Despite their advantages with respect to traditional solvents, their synthesis typically requires access to power, limiting their applicability to address problems in remote locations. Addressing this shortcoming, this report describes the possibility to use a 3D‐printed solar concentrator for the on‐site preparation of NADES, approach that not only provides a simple way to adjust synthetic conditions but also represents the greenest method for their synthesis reported to date. To highlight the advantages of the approach, the preparation of twelve representative NADES was performed and benchmarked against one of the most traditional methods, involving heating and stirring. According to our results, most of the NADES tested could be prepared on‐site in <40 min and with minimal hardware requirements. Additionally, the NADES prepared were used for the extraction of chlorophyll from Vitis vinifera leaves, prior to its quantification using a smartphone and a 3D printed fluorometer. The greenness of the proposed method (calculated using the AGREE software) rendered a score of 0.86, the best reported to date.

BEAT: Blockchain-Enabled Accountable and Transparent Network Sharing in 6G

Infrastructure sharing is a widely discussed and implemented approach and is successfully adopted in telecommunications networks today. In practice, it is implemented through prior negotiated service level agreements (SLAs) between the parties involved. However, it is recognized that these agreements are difficult to negotiate, monitor, and enforce. For future 6G networks, resource and infrastructure sharing is expected to play an even greater role. It will be a crucial technique for reducing over-all infrastructure costs and increasing operational efficiencies for operators. More efficient SLA mechanisms are thus crucial to the success of future networks. In this work, we present BEAT, an automated, transparent, and accountable end-to-end architecture for network sharing based on blockchain and smart contracts. This work focuses on a particular type of blockchain, permissioned distributed ledger, due to its permissioned nature allowing for industry-compliant SLAs with stringent governance. Our architecture can be implemented with minimal hardware changes and with minimal overheads.

Passive Capacitor Voltage Balancing of SiC-Based Three-Level Dual-Active-Bridge Converter Using Hybrid NPC-Flying Capacitor Structure

Three-level (TL) dual-active-bridge (DAB) converter serves a critical role in the medium-voltage (MV) solid-state-transformers in which high voltage rating and bidirectional power flow are required. The regular neutral-point-clamping (NPC) topology is easily subjected to capacitor voltage unbalance due to nonideal operating conditions. In this article, a hybrid structure incorporating NPC and flying capacitor (FC) is presented to resolve the voltage unbalance issue. The key advantages include minimal additional hardware efforts and no need to resort to active control. The FC behaves as a buffer to leverage the upper and lower capacitor so that passive voltage balance between the two dc-link capacitors can be achieved on a switching cycle basis. Closed-form analysis further reveals the impact of FC value on voltage unbalance. Moreover, the appropriate modulation scheme, switching condition, and commutation loop are evaluated to provide detailed rule of thumb to the implementation of FC circuit. Analysis shows the FC also brings favorable switching loss performance and is friendly to employ upon fast switching of wide bandgap devices such as SiC. Finally, a 1.6 kV input, 400 V output, 8 kW scaled-down hybrid NPC-FC-based DAB converter is built to validate the above analysis.

Noise-robust phase retrieval by optics path modulation with adaptive feedback

We propose a compact computational imaging system with adaptive weighted feedback amplitude-phase retrieval (awfAPR) algorithm, in which the traditional axial linear scanning method is replaced by periodic optical path modulation (OPM) strategy. The introduced adaptive feedback scenario can significantly suppress noise contamination. Specifically, OPM is achieved by the rotation of gradient thicknesses of the transparent optical medium. Compared with multi-distance/height scanning (MDPR), all system components in the OPM system are fixed at discrete lateral positions. Besides, according to the auxiliary of corresponding auto-focusing criterion and sub-pixel registration algorithms, the OPM system is also self-calibration and independent of the accuracy of rotation and thickness parameter. Furthermore, experimental results show that the adaptive weighted feedback strategy remarkably improves the stability and robustness toward the noise. OPM has flexible adaptability to optical path modulation method. The proposed optical system configuration has minimal hardware requirements and is anticipated to expand dynamic real-time imaging.

Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model.

Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (±360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.

Ultrafast end-to-end protein structure prediction enables high-throughput exploration of uncharacterized proteins

Deep learning-based prediction of protein structure usually begins by constructing a multiple sequence alignment (MSA) containing homologs of the target protein. The most successful approaches combine large feature sets derived from MSAs, and considerable computational effort is spent deriving these input features. We present a method that greatly reduces the amount of preprocessing required for a target MSA, while producing main chain coordinates as a direct output of a deep neural network. The network makes use of just three recurrent networks and a stack of residual convolutional layers, making the predictor very fast to run, and easy to install and use. Our approach constructs a directly learned representation of the sequences in an MSA, starting from a one-hot encoding of the sequences. When supplemented with an approximate precision matrix, the learned representation can be used to produce structural models of comparable or greater accuracy as compared to our original DMPfold method, while requiring less than a second to produce a typical model. This level of accuracy and speed allows very large-scale three-dimensional modeling of proteins on minimal hardware, and we demonstrate this by producing models for over 1.3 million uncharacterized regions of proteins extracted from the BFD sequence clusters. After constructing an initial set of approximate models, we select a confident subset of over 30,000 models for further refinement and analysis, revealing putative novel protein folds. We also provide updated models for over 5,000 Pfam families studied in the original DMPfold paper.

A Spacecraft Attitude Determination and Control Algorithm for Solar Arrays Pointing Leveraging Sun Angle and Angular Rates Measurements

The capability to orient the solar arrays of a spacecraft toward the Sun is an ultimate asset for any attitude determination and control subsystem (ADCS). This ability should be maintained in any operative circumstance, either nominal or off-nominal, to avoid the loss of the entire space-borne system. The safe mode implementation should guarantee a positive power generation from the solar arrays, regardless of the health status of the satellite platform. This paper presents a solar array pointing algorithm, to be executed on-board, with a minimal set of sensors and actuators. In fact, the sensors are limited to the solar arrays, exploiting the current/voltage sensing capacity of the electrical power subsystem to measure the Sun angle with respect to the arrays normal, and to the angular rates sensors. The actuators are required to provide a torque only along two axes and, thus, a reduced actuation capacity is still manageable by the proposed algorithm. The paper describes the algorithm, both in the Sun direction determination and in the Sun pointing control capacity. The achieved performance is outlined, considering either an ideal system or a realistic one, being the latter affected by sensors and actuators limitations. The actuation by means of momentum exchange devices or magnetic torquers is discussed, with the purpose to prove the wide applicability range of the presented algorithm, which is capable to guarantee solar array orientation with a minimal hardware set.

Analysis of energy harvesting in SWIPT using bio-inspired algorithms

ABSTRACT In this paper, we consider a power splitting (PS)-based simultaneous wireless information and power transfer (SWIPT) system, which is having I and Q (in-phase and quadrature) imbalance hardware impairment. The prime objective of this paper is to maximize the harvested energy for a SWIPT PS system, satisfying a minimum signal to noise ratio (SNR) requirement for information signal processing in the presence of IQ imbalance hardware impairment. The paper uses four types of bio-inspired algorithms like Particle Swarm Optimisation, Artificial Bee Colony, Firefly Algorithm and Invasive Weed Optimisation to attain the maximum harvested energy considering parameters of PS ratio, amplitude and phase imbalances in a Rayleigh fading environment. The simulation results show that under ideal power conversion efficiency and minimum hardware impairments, a maximum SNR of 16.7 dB and harvested energy of 11 dB is achieved for a transmit power of 20 dB in SWIPT systems for IWO bio-inspired algorithms in the 32 QAM modulation scheme.

Nonlinear photonic dynamical systems for unconventional computing

Driven by the remarkable breakthroughs during the past decade, photonics neural networks have experienced a revival. Here, we provide a general overview of progress over the past decade, and sketch a roadmap of important future developments. We focus on photonic implementations of the reservoir computing machine learning paradigm, which offers a conceptually simple approach that is amenable to hardware implementations. In particular, we provide an overview of photonic reservoir computing implemented via either spatio temporal or delay dynamical systems. Going beyond reservoir computing, we discuss recent advances and future challenges of photonic implementations of deep neural networks, of the quest for learning methods that are hardware-friendly as well as realizing autonomous photonic neural networks, i.e. with minimal digital electronic auxiliary hardware.

SPEED: Separable Pyramidal Pooling EncodEr-Decoder for Real-Time Monocular Depth Estimation on Low-Resource Settings

The monocular depth estimation (MDE) is the task of estimating depth from a single frame. This information is an essential knowledge in many computer vision tasks such as scene understanding and visual odometry, which are key components in autonomous and robotic systems. Approaches based on the state of the art vision transformer architectures are extremely deep and complex not suitable for real-time inference operations on edge and autonomous systems equipped with low resources (i.e. robot indoor navigation and surveillance). This paper presents SPEED, a Separable Pyramidal pooling EncodEr-Decoder architecture designed to achieve real-time frequency performances on multiple hardware platforms. The proposed model is a fast-throughput deep architecture for MDE able to obtain depth estimations with high accuracy from low resolution images using minimum hardware resources (i.e. edge devices). Our encoder-decoder model exploits two depthwise separable pyramidal pooling layers, which allow to increase the inference frequency while reducing the overall computational complexity. The proposed method performs better than other fast-throughput architectures in terms of both accuracy and frame rates, achieving real-time performances over cloud CPU, TPU and the NVIDIA Jetson TX1 on two indoor benchmarks: the NYU Depth v2 and the DIML Kinect v2 datasets.

A Smart Memory Controller for System on Chip‐Based Devices

This research paper deals with a system‐on‐chip (SoC) architecture design where multiple processors are inbuilt with other blocks of memory and control logic developed by nanomaterials. The multiprocessing‐based SoC architecture is commonly used in the latest electronic devices such as smartphones, tablets, and smart wristwatches with large memory sizes. The data handing in these highly memory‐dense devices is a critical task, and it needs special attention for the smooth operation of the device. This research proposed a smart controller to exchange data between various processors and input‐output devices to tackle this challenge. A proposed controller block controls the data flow between memory and different SoC components and processors. A memory access controller (MAC) is presented in this research study to manage and accelerate data transmission speed and reduce the processors’ activity for SoC‐based devices. The proposed MAC will integrate into the SoC with multiprocessing units, including gaming processors, at minimum hardware overhead and low power consumption. It improves the memory accessing efficiency and reduces the processors’ activity of a system. As a result, the system’s performance and power consumption improve at an acceptable level compared with the other conventional methods. This research is aimed at enhancing the performance of any SoC‐based device where multiprocessing engines are inbuilt and flexible enough to serve various SoCs.