Wirelength Minimization Research Articles

Layer and Length-Deviation Limit Aware Interposer Routing for Bend and Wirelength Minimization

Layer and Length-Deviation Limit Aware Interposer Routing for Bend and Wirelength Minimization

Wire length optimization of VLSI circuits using IWO algorithm and its hybrid

PurposeAdvancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO).Design/methodology/approachThis paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark.FindingsThis paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits.Practical implicationsThis paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms.Originality/valueThis paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

Floor Planning of 3D IC Design Using Hybrid Multi-verse Optimizer

Several research works have been undergone in the 3D IC floor planning concepts due to its higher demand and technological improvement. Floor planning is a complex step when there is a more number of a component on each layer of IC. Even though several researches have been done in this area, the optimization process is still not satisfied with the use of traditional mechanisms. Consequently, there is a need for effective optimization procedure in IC design. Hence, in this proposed work, hybrid multi verse optimizer floor planning is utilized where the node coordinates and dimensions are adjusted to attain the optimized floor planning with minimal wire length and area using best universes.

Spatial clustering of orientation preference in primary visual cortex of the large rodent agouti.

SummaryAll rodents investigated so far possess orientation-selective neurons in the primary visual cortex (V1) but – in contrast to carnivores and primates – no evidence of periodic maps with pinwheel-like structures. Theoretical studies debating whether phylogeny or universal principles determine development of pinwheels point to V1 size as a critical constraint. Thus, we set out to study maps of agouti, a big diurnal rodent with a V1 size comparable to cats'. In electrophysiology, we detected interspersed orientation and direction-selective neurons with a bias for horizontal contours, corroborated by homogeneous activation in optical imaging. Compatible with spatial clustering at short distance, nearby neurons tended to exhibit similar orientation preference. Our results argue against V1 size as a key parameter in determining the presence of periodic orientation maps. They are consistent with a phylogenetic influence on the map layout and development, potentially reflecting distinct retinal traits or interspecies differences in cortical circuitry.

SAT-Based On-Track Bus Routing

In modern integrated circuit design, bus routing is a challenge because of complex design rules and wiring constraints. Despite extensive research, state-of-the-art in bus routing is not effective when nonuniform tracks, various obstacles, wire width constraints, and multiple spacing rules should be handled simultaneously. A new bus routing framework proposed in this article is based on maze routing and Boolean satisfiability. It produces high-quality results quickly and allows for additional optimizations, such as minimizing wire length on the critical paths. A number of challenging bus routing benchmarks appeared in 2018 ICCAD Contest. Experiments on these benchmarks not only show that the framework is faster than the winners of the competition and previous work but also produces better results, improving the overall cost by 12% while at the same time minimizing the number of spacing violations.

RETRACTED: A novel optimization approach for partitioning-based place and route in 3D integrated circuits

The 3D integrated circuits are enlarging the technology with lots of potentials which establish vertical interconnection between different dies or layers. In 3D-integrated circuit fabrication, congestion, and wirelength minimization are challenging processes. To overcome these problems, we proposed a novel optimization approach for useful partitioning, placement, and routing. Our proposed work consists of four significant stages, including partitioning, placement, routing, and fault diagnosis in through silicon via and spare through silicon via allocation. Firstly, the QuadTree partitioning method executed by the partitioning process. QuadTree method partitions the layer into four subdivisions and remains until it finds no space for partitioning. AND logic is proposed to overcome the congestion problem during placement. In the second stage, the functioning of the hybrid particle swarm optimization and simulated annealing algorithm proposed by the placement process. Particle swarm optimization computes fitness function for six constraints, specifically wirelength, area, power, cross talk, temperature, and delay. The simulated annealing places circuits in the specified area with the computed fitness function. In every 45°, Kruskal’s based octi-linear Steiner tree algorithm that establishes routes performs the routing by the third stage. In the last stage, fault detection in through silicon via and spare through silicon via allocation processes are executed using the support vector machine algorithm and dedicated switch. Support vector machine classifies the TSV into two, which includes regular and redundant through silicon via. The spare through silicon via allocation performed by using a dedicated switch. Finally, the proposed work evaluated based on metrics such as wire length, area, temperature, delay, and run time.

MFMW: Modified Floor planning with Minimum Wire length

Floorplanning is one of the most critical phases inVLSI circuit design. The module alignment has a substantial concentration on the minimization of chip area and total wirelength in slicing floorplan. At foremost, the disadvantages of dead space are investigated and an instinctive and profligate method is proposed to find the equitable part of component. Then, a tormenting for standardized expression is improved to produce new solution, and the proposed simulated annealing algorithm which improves design efficiency is opted for the best floorplan solution. The proposed MFMW method attains less area on the commonly used AMI33 and AMI 49 benchmark circuits.

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes

As very large-scale integration technology shrinks to fewer tracks per standard cell, e.g., from 10 to 7.5-track libraries (and lesser for 7 nm), there has been a rapid increase in the usage of multiple-row cells like two- and three-row flip-flops, buffers, etc., for design closure. Additionally, the usage of multibit flip-flops or flop trays to save power creates large cells that further complicate critical design tasks, such as placement. Detailed placement happens to be a key optimization transform, which is repeatedly invoked during the design closure flow to improve design parameters, such as wirelength, timing, and local wiring congestion. Advanced node designs, with hundreds of thousands of multiple-row cells, require a paradigm change for this critical design closure transform. The traditional approach of fixing multiple-row cells during detailed placement and only optimizing the locations of single-row standard cells can no longer obtain appreciable quality of results. It is imperative to have new techniques that can simultaneously optimize both multiple- and single-row height cell locations during detailed placement. In this paper, we propose a new density-aware detailed placer for heterogeneous-sized netlists. Our approach consists of a chain move scheme that generalizes the movement of heterogeneous-sized cells, a nested dynamic programming-based approach for ordered double-row placement and a network flow-based formulation to solve ordered multiple-row placement for wirelength and density optimization. Experimental results demonstrate the effectiveness of these techniques in wirelength minimization and density smoothing compared with the most recent detailed placers for designs with heterogeneous-sized cells.

MOBA: Multi Objective Bat Algorithm for Combinatorial Optimization in VLSI

It has to be conceded that the complexity of any integrated chip gets abated despite of the increased complexity. Notwithstanding, the perplexity of computing escalates exponentially. Thus computational optimization scores in the scene wherein several conflicting objectives has to be optimized without any compromise. Several years, scientists have solved any optimization problem by cogitating and considering it to be a Single Objective Optimization Problem (SOOP). However, mathematics has eulogized Multi Objective Optimization (MOO) methodologies to solve the conflicting tradeoffs. Besides, there is an instigation to converge our research to biologically inspired metaheuristics to solve optimization problems as it is evident from the anthologies and research archive that these heuristics perpetually doing well in solving optimization problems and that too in extension MOO problems. Researchers are captivated in the field to observe the perplexed processes of nature and mimic it solve optimization problems. In this research work, we have contemplated on the Multi Objective Bat Algorithm (MOBA) a biologically inspired metaheuristics and have successfully applied to solve the problem of floorplanning in VLSI design. The peculiar character of echolocation of microbats are being mimicked and applied to solve the problems in VLSI design. The intriguing attributes of Bats; how it strives to take up its prey, are fathomed out and been adopted in problem solving. The problem is considered as a MOO problem wherein equal importance were given to wirelength minimization and dead space minimization. The results are discussed and rivalled with several other bio-inspired algorithms and are portrayed. To comprehend, the MOBA worked well in VLSI floorplanning optimization wherein the problems were considered with a single objective and multi objective fashion.

Two Approaches for Timing-Driven Placement by Lagrangian Relaxation

In this paper, we propose Lagrangian relaxation (LR)-based algorithms to optimize both circuit performance and total wirelength at the global placement stage. We introduce a general timing-driven global placement problem formulation that is applicable to three different circuit design styles: 1) synchronous circuits; 2) synchronous circuits with sequential optimization techniques; and 3) asynchronous circuits. LR is applied to handle the timing constraints of the formulated problem. Based on how the cell spreading constraints are handled, two different approaches are proposed: one approach handles the spreading constraints inside the LR framework and transforms the timing-driven placement (TDP) problem into a series of weighted wirelength minimization problems, which can be solved by directly leveraging existing wirelength-driven placers. The other approach handles the spreading constraints outside the LR framework. Thus, only timing constraints need to be taken care of in the LR framework and better solutions can be expected. In both approaches, we simplified the LR subproblem using Karush–Kuhn–Tucker conditions. Our algorithms are implemented based on a state-of-the-art wirelength-driven quadratic placer. The experiments demonstrate that the proposed algorithms are able to achieve significant improvements on circuit performance compared with a commercial wirelength-driven placement flow and a commercial asynchronous TDP flow.

Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing

The placement of cells in Integrated Circuit Design Automation has a major influence on overall design cycle. The existing popular quadratic placement techniques suffer from overlaps, large placement effort and time. In order to lower the placement overhead and to avoid the overlaps with reduced wire length, we propose a grouping and merging based placement methodology that is simpler than existing placers and easier to integrate into timing-closure flows. As a proof of concept, the proposed methodology is extensively tested on standard benchmark circuits. The proposed methodology resulted in 5× placement time reduction, 13% reduction in wire-length and 11% reduction in area with zero overlap.

FLOOR PLANNING DESIGN USING k-NEAREST NEIGHBOUR BASED BIAS TRANSFERS LEARNING ALGORITHM

In VLSI chip the minimization of wire length is most significant, its play a very important role for various application. The aim of this work is to minimize the wire length through finding an optimum resolution for VLSI physical project mechanisms like dividing and floor-planning. In very large-scale integration circuit splitting, the issue of finding a smallest delay has prime significance. The very large-scale integration circuit floor planning, the issue of reducing silicon region is also a crucial issue. Decreasing the delay in dividing area here floor planning helps to reduce the wire-length. In our research Bias Transfer (BITER) is an Evolutionary Algorithm that suitable for transfer learning in agents in floor planning phases within its evolutionary cycle to obtain the minimum wire length and make resize then in needed instead of the MA uses the for exploration and uses the local search method for exploitation and its comparison between the GA and MA is to justify the effectiveness of the Bias Transfer-KNN Technique which reducing delay and dead space area at the time of in partitioning that simulated in MATLAB 2014Ra.

Fast thermal analysis for fixed-outline 3D floorplanning

Three dimensional integrated circuits (3D ICs) can alleviate the problem of interconnection, a critical problem in the nanoscale era, and are also promising for heterogeneous integration. However, the thermal challenge in industry is one of key obstacles to adopt the 3D ICs technology. Various thermal analysis models for 3D IC have been proposed in literature. However, the long simulation cycle makes runtime of thermal management inefficient during floorplanning phase. In this paper, we propose a fast thermal analysis method for fixed-outline 3D floorplanning. Before floorplanning, we simulate the thermal distribution of each block placed on different positions. Based on the simulated thermal profiles, bilinear interpolation is adopted to quickly estimate temperature during floorplanning. After the block planning, a heuristic method, which combines the shortest path and min-cost-max-flow, is presented for TSV allocation with minimization of chip temperature and wirelength. Compared with the superposition of thermal profiles method, the proposed thermal analysis method can reduce the peak temperature by 6.7% on average with short runtime for 3D fixed-outline floorplanning, which demonstrates the efficiency and effectiveness of the proposed thermal analysis method.

Difficult Channel Instance Generator for VLSI Physical Design Automation using Genetic Algorithm

Objectives: The wire length minimization of Channel routing problem is NP-hard. There are several heuristic algorithms available in the literature to get the feasible routing solutions using some limited instances. Here we want to generate all possible random channel instances based on Genetic Algorithm (GA). Methods/ Statistical Analysis: The present paper is described in three phases. In the first phase, we generate fixed size initial population based on some strategies and define the fitness value of each individual by the total number of vertical and horizontal constraints present in the channel. The best individual is obtained among the population based on height fitness value. In the second phase, we select two individuals based on Roulette Wheel Selection strategies and get two offspring's using single point crossover. We continue this process until the number of offspring's reached to the size of the population. To keep the population size fixed we apply reduction methods among the initial population along with all offspring are based on minimum fitness value. In the third phase, we randomly choose some channels for mutation and we find the best individuals among current population. This methodology will be continuing until and unless we reach the goal. Findings: The proposed method works efficiently for complex problems arise in VLSI physical design automation and it gives acceptable results in terms of different channel instances. Applications/Improvement: The newly designed method for different difficult channel instances generation techniques will help to judge any newly developed algorithm in the field of VLSI physical design automation.

Cortical Composition Hierarchy Driven by Spine Proportion Economical Maximization or Wire Volume Minimization.

The structure and quantitative composition of the cerebral cortex are interrelated with its computational capacity. Empirical data analyzed here indicate a certain hierarchy in local cortical composition. Specifically, neural wire, i.e., axons and dendrites take each about 1/3 of cortical space, spines and glia/astrocytes occupy each about (1/3)2, and capillaries around (1/3)4. Moreover, data analysis across species reveals that these fractions are roughly brain size independent, which suggests that they could be in some sense optimal and thus important for brain function. Is there any principle that sets them in this invariant way? This study first builds a model of local circuit in which neural wire, spines, astrocytes, and capillaries are mutually coupled elements and are treated within a single mathematical framework. Next, various forms of wire minimization rule (wire length, surface area, volume, or conduction delays) are analyzed, of which, only minimization of wire volume provides realistic results that are very close to the empirical cortical fractions. As an alternative, a new principle called “spine economy maximization” is proposed and investigated, which is associated with maximization of spine proportion in the cortex per spine size that yields equally good but more robust results. Additionally, a combination of wire cost and spine economy notions is considered as a meta-principle, and it is found that this proposition gives only marginally better results than either pure wire volume minimization or pure spine economy maximization, but only if spine economy component dominates. However, such a combined meta-principle yields much better results than the constraints related solely to minimization of wire length, wire surface area, and conduction delays. Interestingly, the type of spine size distribution also plays a role, and better agreement with the data is achieved for distributions with long tails. In sum, these results suggest that for the efficiency of local circuits wire volume may be more primary variable than wire length or temporal delays, and moreover, the new spine economy principle may be important for brain evolutionary design in a broader context.

Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits

Capacitance-ratio mismatch in a switched-capacitor circuit could significantly degrade circuit performance. In the nanometer era, the parasitic effects and lengths of interconnects both have significant impacts on the capacitance ratio. This paper presents the first routing work for the problem of coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. The router adopts a two-stage approach of topology generation followed by detailed routing to route unit capacitors such that the coupling-aware wire length ratio can match the desired capacitance ratio. Given a length ratio, in particular, the length-ratio-matching routing problem can be handled by transforming the problem into an easier classical wirelength minimization one. Experimental results show that our algorithm can solve the addressed problem with substantially smaller costs.

Efficient Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Geometric Reduction

Given a set of pin-vertices, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects all the pin-vertices possibly through Steiner points using vertical and horizontal segments with the minimal wirelength and without intersecting any obstacle. To deal with multiple routing layers and preferred routing orientations, we consider the multilayer obstacle-avoiding rectilinear Steiner minimal tree (ML-OARSMT) problem and the obstacle-avoiding preferred direction Steiner tree (OAPD-ST) problem. First, we prove that the multilayer case is theoretically different from the 2D one, and propose a reduction to transform a multilayer instance into a 3D instance. Based on the reduction, we apply computational geometry techniques to develop an efficient algorithm, utilizing existing OARSMT heuristics, for the ML-OARSMT problem and the OAPD-ST problem. Furthermore, we develop an advanced Steiner point selection to avoid inferior Steiner points and to improve the solution quality. Experimental results show that our algorithm provides a solution with excellent quality and has a significant speed-up compared to previously known results.

A Predictive Network Model of Cerebral Cortical Connectivity Based on a Distance Rule

Recent advances in neuroscience have engendered interest in large-scale brain networks. Using a consistent database of cortico-cortical connectivity, generated from hemisphere-wide, retrograde tracing experiments in the macaque, we analyzed interareal weights and distances to reveal an important organizational principle of brain connectivity. Using appropriate graph theoretical measures, we show that although very dense (66%), the interareal network has strong structural specificity. Connection weights exhibit a heavy-tailed lognormal distribution spanning five orders of magnitude and conform to a distance rule reflecting exponential decay with interareal separation. A single-parameter random graph model based on this rule predicts numerous features of the cortical network: (1) the existence of a network core and the distribution of cliques, (2) global and local binary properties, (3) global and local weight-based communication efficiencies modeled as network conductance, and (4) overall wire-length minimization. These findings underscore the importance of distance and weight-based heterogeneity in cortical architecture and processing.

Collaborative Multiobjective Global Routing

This paper presents a collaborative procedure for multiobjective global routing. Our procedure takes multiple global routing solutions, which are generated independently (e.g., by one router that runs in different modes concurrently or by different routers running in parallel), as input. It then performs multiobjective optimization based on Pareto algebra and quickly generates multiple global routing solutions with a tradeoff between the considered objectives. The user can control the number of generated solutions and the degree of exploring the tradeoff between them by constraining the maximum allowable degradation in each objective. This paper then considers the following three multiobjective case studies: 1) minimization of interconnect power and wirelength; 2) minimization of routing congestion and wirelength; and 3) minimization of wirelength with respect to the (finite-capacity) routing resources. The maximum allowable degradation in wirelength is specified in all cases. Our multiobjective procedure runs in only a few minutes for each of the International Symposium on Physical Design 2008 benchmarks, even the unroutable ones, which imposes a tolerable overhead in the design flow. In our simulations, we demonstrate the effectiveness of our procedure using five modern academic global routers.

Hebbian Learning of Recurrent Connections: A Geometrical Perspective

We show how a Hopfield network with modifiable recurrent connections undergoing slow Hebbian learning can extract the underlying geometry of an input space. First, we use a slow and fast analysis to derive an averaged system whose dynamics derives from an energy function and therefore always converges to equilibrium points. The equilibria reflect the correlation structure of the inputs, a global object extracted through local recurrent interactions only. Second, we use numerical methods to illustrate how learning extracts the hidden geometrical structure of the inputs. Indeed, multidimensional scaling methods make it possible to project the final connectivity matrix onto a Euclidean distance matrix in a high-dimensional space, with the neurons labeled by spatial position within this space. The resulting network structure turns out to be roughly convolutional. The residual of the projection defines the nonconvolutional part of the connectivity, which is minimized in the process. Finally, we show how restricting the dimension of the space where the neurons live gives rise to patterns similar to cortical maps. We motivate this using an energy efficiency argument based on wire length minimization. Finally, we show how this approach leads to the emergence of ocular dominance or orientation columns in primary visual cortex via the self-organization of recurrent rather than feedforward connections. In addition, we establish that the nonconvolutional (or long-range) connectivity is patchy and is co-aligned in the case of orientation learning.