FLOOR PLANNING DESIGN USING k-NEAREST NEIGHBOUR BASED BIAS TRANSFERS LEARNING ALGORITHM

Abstract

In VLSI chip the minimization of wire length is most significant, its play a very important role for various application. The aim of this work is to minimize the wire length through finding an optimum resolution for VLSI physical project mechanisms like dividing and floor-planning. In very large-scale integration circuit splitting, the issue of finding a smallest delay has prime significance. The very large-scale integration circuit floor planning, the issue of reducing silicon region is also a crucial issue. Decreasing the delay in dividing area here floor planning helps to reduce the wire-length. In our research Bias Transfer (BITER) is an Evolutionary Algorithm that suitable for transfer learning in agents in floor planning phases within its evolutionary cycle to obtain the minimum wire length and make resize then in needed instead of the MA uses the for exploration and uses the local search method for exploitation and its comparison between the GA and MA is to justify the effectiveness of the Bias Transfer-KNN Technique which reducing delay and dead space area at the time of in partitioning that simulated in MATLAB 2014Ra.