Three-dimensional Integrated-Circuits (3D ICs) based on Through-Silicon-Via (TSV) technology offer numerous advantages, including high density, enhanced bandwidth, and lower power consumption. However, the complex manufacturing process introduces various defects, posing a considerable challenge to the reliability of 3D integration using TSVs. To address this issue, the utilization of spare TSVs as a solution for enhancing yield and reliability is a viable approach. In this study, we present a high-performance repair solution that efficiently allocates spare TSVs while minimizing hardware costs, area, and delay overhead. We introduce a spare TSV allocation scheme that considers the white space constraint, effectively reducing the delay overhead caused by excessive wire lengths. Our proposed solution achieves a significantly higher repair rate for densely clustered TSV defects compared to existing approaches. Moreover, our method stands out by reducing control logic area overhead by 65% or more when compared to previous works. Additionally, it significantly reduces delay overhead compared to other TSV redundancy architectures.