MIM Capacitors Research Articles

Microbeam SEE Analysis of MIM Capacitors for GaN Amplifiers

Broad-beam and microbeam single-event effect tests were performed on metal–insulator–metal capacitors with three different thicknesses of silicon nitride (Si3N4) dielectric insulator: 250, 500, and 750 nm. The broad-beam tests indicated that the devices with the thicker, 500- and 750-nm dielectric did not have a greater breakdown voltage. The surrounding structures of the capacitor were suspected to be a possible cause. Microbeam techniques made it possible to localize the failure location for the 500- and 750-nm devices. The failure occurs in the air bridge structure connected to the top capacitor plate, which can therefore be considered as an edge effect, while for the 250-nm devices, the failure occurs in the body of the capacitor.

Tunable RF Phase Shifters Based on Vanadium Dioxide Metal Insulator Transition

This paper presents the design, fabrication, and electrical characterization of a reconfigurable RF capacitive shunt switch that exploits the electro-thermally triggered vanadium dioxide (VO2) insulator to metal phase transition. The RF switch is further exploited to build wide-band RF true-time delay tunable phase shifters. By triggering the VO2 switch insulator to metal transition (IMT), the total capacitance can be reconfigured from the series of two metal–insulator–metal (MIM) capacitors to a single MIM capacitor. The effect of bias voltage on losses and phase shift is investigated, explained, and compared to the state of the art in the field. We report thermal actuation of the devices by heating the devices above VO2 IMT temperature. By cascading multiple stages a maximum of 40° per dB loss close to 7 GHz were obtained.

Fully Integrated Inductor-Less Flipping-Capacitor Rectifier for Piezoelectric Energy Harvesting

This paper presents a fully integrated piezoelectric energy harvesting interface without external components. Instead of relying on bulky external inductors with high quality factor as in the conventional parallel-synchronized-switch harvesting-on-inductor (P-SSHI) approach, we propose a flipping-capacitor rectifier (FCR) topology to achieve voltage inversion of the piezoelectric energy harvester through a reconfigurable capacitor array. This fundamentally preserves a fully integrated solution without inductors while achieving a high-energy extraction capability. Measurement results from FCR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> using discrete components shows an output power enhancement of up to 3.4×, which is close to the theoretical prediction. We also fabricated a sevenphase FCR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> with four MIM capacitors and 21 switches using a 0.18-μm 1.8/3.3/6 V CMOS process, occupying an active area of ~1.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Additionally, we implemented an active rectifier based on a common-gate comparator with phase alignment to ensure high-speed operation while minimizing the diode voltage drop. A phase generate-and-combine circuit eliminates redundant switching activities. Systematic optimization of the three main energy loss mechanisms during the finite flip time: 1) phase offset; 2) incomplete charge transfer; and 3) reduced conduction time, is also introduced. Measurement results show that the output power enhancement can reach up to 4.83× at an excitation frequency of 110 kHz.

Negative VCC in MIM capacitors: modeling and experiments

After the advent of Cu and TiN metallization in high-speed and high-density radio frequency and analog/mixed-signal integrated circuits, new challenges have emerged in achieving low voltage coefficient of capacitance (VCC) in metal-insulation-metal capacitor (MIM) technology. While single layer high-k dielectric MIM capacitors fail to provide low VCC ( $$<100$$ ppm/V $$^{2}$$ ), stacked high-k/ $$\hbox {SiO}_{2}$$ dielectrics show a promising solution as the negative VCC of $$\hbox {SiO}_{2}$$ cancels the positive VCC of high-k materials. To understand the mechanism and origin of negative VCC, a unified analytical model of negative VCC with experimental validation is presented in this paper. This model would be a very useful tool to design high performance MIM capacitors with ultra-low VCC for radio frequency and analog/mixed-signal integrated circuits.

Discovering and reducing defects in MIM capacitors

Integrated circuit defectivity is becoming a top concern for Reliability Engineers and their customers. Device lifetimes and times to wearout are less important compared to the experience of an early or infant failure in the warranty period. Defects in circuit elements, such as capacitors, are as important as any other cause of device fallout. Historically, integrated capacitors have been a leading reason for early failure, so this work describes the detection, root cause analysis, and the mitigation of three types of capacitor defects.

Fabrication and modeling of multi-layer metal–insulator-metal capacitors* * Project supported by the Science and Engineering Research Board (No. ECR/2016/001156).

This paper presents the fabrication and modeling for capacitance–voltage characteristics of multi-layer metal–insulator–metal capacitors. It is observed that, due the applied electric field, the effective dielectric constant of the stack was increased due to the accumulation of charges at the interface of high-to-low conductance materials. It is observed that the Maxwell–Wagner polarization is dominant at low frequencies (<10 kHz). By introducing carrier tunneling probability of the dielectric stack, the model presented in this paper shows a good agreement with experimental results. The presented model indicates that the nonlinearity can be suppressed by choosing the similar permittivity dielectric materials for fabrication of multilayer metal insulator metal capacitors.

Direct Fabrication of Inkjet-Printed Dielectric Film for Metal–Insulator–Metal Capacitors

In this study, an inkjet-printed dielectric film that used a polymer-based SU-8 ink was fabricated for use in a metal–insulator–metal (MIM) capacitor. Thermal treatment of the inkjet-printed SU-8 polymer film affected its surface morphology, chemical structure, and surface wettability. A 20-min soft-bake at 60°C was applied to eliminate inkjet-printed bubbles and ripples. The ultraviolet-exposed SU-8 polymer film was crosslinked at temperatures between 120°C and 220°C and became disordered at 270°C, demonstrated using Fourier-transform infrared spectroscopy. A maximum SU-8 polymer film hard-bake temperature of 120°C was identified, and a printing process was subsequently employed because the appropriate water contact angle of the printed film was 79°. Under the appropriate inkjet printing conditions, the two-transmission-line method was used to extract the dielectric and electrical properties of the SU-8 polymer film, and the electrical behavior of the fabricated MIM capacitor was also characterized.

Modeling of field dependent Maxwell‐Wagner interfacial capacitance for bilayer metal‐insulator‐metal capacitors

AbstractIn this letter, we have presented the modeling of field dependent Maxwell‐Wagner interfacial capacitance for bilayer metal‐insulator‐metal (MIM) capacitors. The model was verified with measured capacitance‐voltage characteristics of fabricated bilayer Al2O3/TiO2 MIM capacitors. The model reveals the origin of voltage linearity of MIM capacitors at low frequencies (&lt;10 kHz). The proposed model for bilayer/multilayer MIM capacitors is very useful tool to design circuits for mixed signal, analog and digital circuits with low variation of capacitance for change in voltage.

Sol‐gel derived TiNb2O7 dielectric thin films for transparent electronic applications

AbstractTo reduce power consumption of transparent oxide‐semiconductor thin film transistors, a gate dielectric material with high dielectric constant and low leakage current density is favorable. According to previous study, the bulk TiNb2O7 with outstanding dielectric properties may have an interest in its thin‐film form. The optical, chemical states and surface morphology of sol‐gel derived TiNb2O7 (TNO) thin films are investigated the effect of postannealing temperature lower than 500°C, which is crucial to the glass transition temperature. All films possess a transmittance near 80% in the visible region. The existence of non‐lattice oxygen in the TNO film is proposed. The peak area ratio of non‐lattice oxygen plays an important role in the control of leakage current density of MIM capacitors. Also, the capacitance density and dissipation factor were affected by the indium tin oxide (ITO) sheet resistance at high frequencies. The sample after postannealing at 300°C and electrode‐annealing at 150°C possesses a high dielectric constant (&gt;30 at 1 MHz) and a low leakage current density (&lt;1 × 10−6 A/cm2 at 1 V), which makes it a very promising gate dielectric material for transparent oxide‐semiconductor thin film transistors.

Topographic Complexities and Solutions for High Density BEOL MIM Capacitors

As technology nodes continue scaling, it is more cost- effective to integrate all SoC building blocks onto a single chip. On-chip BEOL compatible Metal-Insulator-Metal (MIM) decoupling capacitors have attracted increasing interest. They are placed close to the power lines to reduce high frequency noise. Recently there has been great progress on the development of high density (>20fF/μm2) BEOL compatible MIM capacitors. However, no report has been published on the complexity of incorporating such MIM capacitors into the full integration scheme. It is known that multi-level Si structures combined with certain chip design can create topography issues, which will in turn cause a significantly narrowed process window for multiple processes. Addition of high density MIM capacitors will further generate complex effects on both MIM capacitor performance and Cu interconnections. It is imperative to have robust solution for high volume and foundry manufacturing. MIM capacitors are often integrated between the last two Cu layers, as illustrated in Fig. 1. Bottom and top electrodes are TiN, and High k is HfAlO. Etch processes are used to pattern the capacitors, followed by oxide deposition and a CMP process to planarize the patterned topographies. Fig. 2 (a) illustrates the natural topographies produced by MIM capacitor patterning processes. The step height post MIM patterning can be more than 100nm. Without proper polish, this natural topography cannot be completely planarized. Fig. 2 (b) illustrates the remaining natural topography with insufficient polishing. In addition, design-related pattern density non-uniformity causes localized topographic weak points. These weak points will add further complexity and reduce process window needed to accommodate both MIM capacitors and Cu interconnections. The related fail modes include shorted Cu lines above MIM capacitors, unlanded Cu interconnection vias, and even punch-through of MIM capacitors, as shown in Fig. 3 (a), (b), and (c), respectively. The oxide thickness post MIM polish has to be properly controlled to accommodate both the need to planarize MIM topographies and the need for MIM capacitor functioning. Fig. 4 (a) shows the polish rate change as a function of polish time. As polish time increases polish rate gradually decreases over a transition period, and then stabilizes at ~75% of the initial value, indicating the natural MIM topographies have been planarized. RMS roughness is reduced by more than 80% (see Fig. 4 (b)). Through sufficient and optimized MIM polish, MIM topographies as well as MIM capacitor performance are greatly improved. Fig. 5 demonstrates the process robustness with planarized MIM topographies and proper oxide thickness. All three types of vias are formed properly, that is, vias landing on MIM top electrode (Via I), on MIM bottom electrode (Via II), and on lower level Cu (Via III). Electrical characterization (Fig. 6) also shows that with an optimized oxide polish process, MIM degradation is fully recovered. High volume manufacture of MIM capacitors with capacitance density >20fF/μm2, leakage current density <100nA/cm2, and breakdown voltage > 5V is demonstrated in production. In summary, we have demonstrated high density MIM capacitors, fully integrated in an advanced BEOL process, and shown a thorough study of their topographies and the complex impacts. An optimized planarization process was developed to enable both MIM capacitors and Cu interconnections. The process robustness was demonstrated for such capacitors that deliver capacitance density above 20 fF/um2, leakage current density below 100 nA/cm2 at 1.45V, and breakdown voltage above 5V. The results greatly facilitated high volume and foundry manufacturing capability of such on-chip high density BEOL MIM capacitors. Figure 1

(Invited) Characteristics of RuO2/TiO2/Al2O3/TiO2/RuO2 Capacitors

Introduction The reduction of the leakage current density and development of a high dielectric constant (k) greater than 60 as insulator have emerged as the main challenge in dynamic random access memory (DRAM) fabrication. RuO2 is a promising material for the electrodes because of its higher work function (5.4eV) compared as currently used TiN (4.7 eV) [1, 2]. Ru or RuO2 formation strongly depends on fabrication condition. The incubation time and surface roughness of RuO2 film, deposited by atomic layer deposition (ALD) process, were also related to the substrate material. On the other hand, ZrO2/Al2O3/ZrO2 structure was currently employed as insulator because an amorphous Al2O3 layer can suppress to a leakage current path along the crystal grain boundaries of ZrO2 layer. Rutile TiO2 has been studied most intensively because of its remarkably high k of ~80. Furthermore, the crystal structure of RuO2 resembles that of rutile TiO2 [3]. However, TiO2 has a disadvantage of low band gap compared to ZrO2. To overcome this issue, we pay attention to Metal-insulator-metal (MIM) capacitor with RuO2 electrode and TiO2/Al2O3/TiO2 (TAT) insulator. The difference (1.53 eV) between conduction band offset of TiO2 and work function of RuO2 is about two times as large as that (0.83 eV) of TiO2 and TiN. In this paper, we investigated surface roughness of RuO2 film on several buffer layers, such as covalent SiO2, ionic Al2O3 and TiO2, by plasma-enhanced ALD (PE-ALD). We also examine the PE-ALD RuO2 film as a bottom electrode for MIM capacitors with TAT insulator. Experimental MIM capacitors with TAT insulator consisted of a PE-ALD-RuO2 bottom electrode (BE-RuO2), a first TiO2 layer, an Al2O3 layer, a second TiO2 layer, and Sp-RuO2 top electrodes (TE-RuO2), in that order. Si substrates with thermal SiO2, ALD-Al2O3, and ALD-TiO2 buffer layers were first prepared, and then BE-RuO2 deposited on the buffer layers by PE-ALD at 300°C using Ru(C2H5C5H4)2 as a precursor and plasma oxygen gas. A first TiO2 layer (10 nm) was deposited on BE-RuO2 by ALD and the first post-deposition anneal (PDA) was carried out at 600°C. Next, Al2O3 (0.5 ~ 5 nm) layer was deposited by ALD, and the second TiO2 (10 nm) layer was then deposited under the same ALD condition as the first TiO2 layer. The second PDA was performed at 600°C. Finally, the Top-RuO2 was deposited by reactive sputtering. Results and Discussion Figure 1 shows k value of TAT as a function of Al2O3 thickness of TAT for RuO2/TAT/RuO2 capacitors. The C-V characteristics of the capacitors were measured by sweeping the voltage from -1 V to 1 V at 100 kHz. The k value of TAT was estimated from the C-V data at 0V. The k value shows a reasonable degradation behavior as Al2O3 thickness increases from 1 to 5 nm in all capacitors. No significant difference appears among SiO2, Al2O3, and TiO2 buffer layers. Furthermore, the k values exhibited 41 ~ 47 for TAT with 1-nm-thick Al2O3. Next, we examine influence of surface roughness of a bottom electrode on leakage current property. TiN/TAT/TiN capacitors was prepared as a reference. The TiN electrode was deposited by sputtering (Sp-TiN). Figure 2 shows comparison of conductive-AFM data for PE-ALD-RuO2/TAT and Sp-TiN/TAT on Al2O3 buffer layer. The measured root mean square (RMS) roughness values for PE-ALD-RuO2 and RuO2/TAT were 0.9 and 1.1 nm, respectively. On the other hand, Sp-TiN and TiN/TAT both had a large surface roughness, with RMS values of 2.0 and 2.6 nm, respectively. Two leak spots were clearly observed on the TiN/TAT, while no spot on the RuO2/TAT under applied voltage of 8 V. This must be related to the difference of surface roughness between the RuO2 and TiN bottom electrodes. Conclusions The smooth surface roughness of PE-ALD-RuO2 film was obtained on ionic Al2O3 buffer layer. The RuO2/TAT/RuO2 capacitors exhibited relatively high k values of over 40. The leakage current property of capacitor is related to the surface roughness of a bottom electrode. Thus, the RuO2 bottom electrode deposited on the ionic Al2O3 buffer layer has the significant advantage for future DRAM Acknowledgements A part of this work was performed under the Cooperative Research Program of Institute for Joining and Welding Research Institute, Osaka University. Part of this research is supported by CREST, JST. The authors thank all staff members of the Nanofabrication Group in NIMS, for their support.

Novel RF MEMS capacitive switches with design flexibility for multi-frequency operation

RF MEMS capacitive shunt switches with a dielectric-on-metal (DOM) capacitor, which are widely used for microwave applications in the communication field, suffer from some serious drawbacks. A significant shift is observed in the resonant frequency of these switches due to the reduction in the down-state capacitance caused by the surface roughness of the dielectric layer. In order to achieve accurate down-state capacitance, a thin layer of floating metal is deposited on the dielectric layer converting the DOM switch to a metal-insulator metal (MIM) switch. The MIM switch opens up interesting possibilities in the design, such as achieving flexibility in the operating frequency of the switch. This paper reports a novel method to achieve design flexibility for multi-frequency operation in switches, by effectively utilizing the equipotential nature of the floating metal in the MIM capacitor. Unlike in a DOM switch, the resonant frequency can be varied by changing merely the length of the floating metal, without having to make any other structural modifications. This enables to have switches operating at different frequency on the same wafer. The beams of the switches are also designed in such a way as to provide stress resilience, thereby preventing buckling. This paper presents the design, simulation, fabrication and characterization of a switch that operates in the X-band. The fabricated switches show excellent stress resilience. The characterized switch demonstrates a reduction in the resonant frequency in proportion to an increase in the length of the floating metal, hence validating the design flexibility proposed in this paper.

Topographic Complexities and Solutions for High Density BEOL MIM Capacitors

The BEOL compatible on-chip MIM capacitors have natural topography post MIM processing. In foundry manufacturing, design-related non uniform pattern density combined with MIM processing can lead to localized topographic process weak points. These weak points add further complexity and reduce the process window available to accommodate both MIM capacitors and Cu interconnections. The related fail modes include punch-through of MIM capacitors, un-landed Cu interconnection vias, and shorted Cu lines above the MIM capacitors. These challenges and complexities are described and characterized in this paper, as well as experiments and solutions to overcome these challenges. Manufacturing capability of BEOL MIM capacitors with capacitance density >20fF/μm2, leakage current density <100nA/cm2, and breakdown voltage > 5V has been demonstrated.

A Technique for Enhancing Varactor’s Quality Factor in Millimeter-Wave Frequencies

Varactors are key devices in the design of voltage-controlled oscillators (VCOs), as their quality factor ( ${Q}$ -factor) at the millimeter-wave frequency range limits the overall LC tank ${Q}$ -factor. This brief presents a new circuit-level structure, called ${Q}$ -enhanced varactor (QEV), that is composed of two metal-insulator-metal capacitors (MIMCAPs) and a varactor. Depending on ${Q}$ -factors and the values of the MIMCAPs, the ${Q}$ -factor in QEV can be improved more than two times. The QEV parameters are analyzed and a design procedure for QEV is proposed. Also, a QEV with two times ${Q}$ -factor improvement is employed in the design of a 40-GHz LC-VCO, illustrating more than 6-dB enhancement in the oscillator figure of merit.

Reaching state-of-the art requirements for MIM capacitors with a single-layer anodic Al2O3 dielectric and imprinted electrodes

Metal-Insulator-Metal (MIM) capacitors with a high capacitance density and low non-linearity coefficient using a single-layer dielectric of barrier-type anodic alumina (Al2O3) and an imprinted bottom Al electrode are presented. Imprinting of the bottom electrode aimed at increasing the capacitor effective surface area by creating a three-dimensional MIM capacitor architecture. The bottom Al electrode was only partly nanopatterned so as to ensure low series resistance of the MIM capacitor. With a 3 nm thick anodic Al2O3 dielectric, the capacitor with the imprinted electrode showed a 280% increase in capacitance density compared to the flat electrode capacitor, reaching a value of 20.5 fF/μm2. On the other hand, with a 30 nm thick anodic Al2O3 layer, the capacitance density was 7.9 fF/μm2 and the non-linearity coefficient was as low as 196 ppm/V2. These values are very close to reaching all requirements of the last International Technology Roadmap for Semiconductors for MIM capacitors [ITRS, http://www.itrs2.net/2013-itrs.html for ITRS Roadmap (2013)], and they are achieved by a single-layer dielectric instead of the complicated dielectric stacks of the literature. The obtained results constitute a real progress compared to previously reported results by our group for MIM capacitors using imprinted electrodes.

Temperature accelerated discharging processes through the bulk of PECVD silicon nitride films for MEMS capacitive switches

The effect of temperature on discharging processes of PECVD silicon nitride films has been investigated in Metal-Insulator-Metal (MIM) capacitors and RF MEMS capacitive switches with the aid of Kelvin Probe method. The surface potential decay of MIM capacitors during discharge has been monitored using a Single-point Kelvin probe system at various temperatures (300K–400K) while the shift of bias at minimum up-state capacitance during discharge has been employed in MEMS capacitive switches in order to determine the discharge current through the bulk of the film at different temperatures. The results indicate that the discharging process through the bulk of silicon nitride films is thermally activated and the corresponding value of the discharging current increases with temperature, due to the increase of the film conductivity. Moreover, the value of minimum up-state capacitance of the switches is found to be significantly affected by temperature, by the mechanical properties of the moving armature as well as by the variance of charge density distribution. Finally, different thermally activated mechanisms have been observed in MIM capacitors and MEMS capacitive switches, due to different charging processes on these devices.

The Effect of Different Dielectric Materials in Designing High-Performance Metal-Insulator-Metal (MIM) Capacitors

&lt;p&gt;A Metal-Insulator-Metal (MIM) capacitor with high capacitance, high breakdown voltage, and low leakage current is aspired so that the device can be applied in many electronic applications. The most significant factors that affect the MIM capacitor’s performance is the design and the dielectric materials used. In this study, MIM capacitors are simulated using different dielectric materials and different number of dielectric layers from two layers up to seven layers. The effect of the different dielectric constants (&lt;em&gt;k&lt;/em&gt;) to the performance of the MIM capacitors is also studied, whereas this work investigates the effect of using low-&lt;em&gt;k&lt;/em&gt; and high-&lt;em&gt;k&lt;/em&gt; dielectric materials. The dielectric materials used in this study with high-&lt;em&gt;k&lt;/em&gt; are Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt; and HfO&lt;sub&gt;2&lt;/sub&gt;, while the low-&lt;em&gt;k&lt;/em&gt; dielectric materials are SiO&lt;sub&gt;2&lt;/sub&gt; and Si&lt;sub&gt;3&lt;/sub&gt;N&lt;sub&gt;4&lt;/sub&gt;. The results demonstrate that the dielectric materials with high-&lt;em&gt;k&lt;/em&gt; produce the highest capacitance. Results also show that metal-Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt; interfaces increase the performance of the MIM capacitors. By increasing the number of dielectric layers to seven stacks, the capacitance and breakdown voltage reach its highest value at 0.39 nF and 240 V, respectively.&lt;/p&gt;

Ferroelectric HfO2 thin film testing and whole wafer mapping with non‐contact corona‐Kelvin metrology

We present results of a non‐contact, real‐time feedback corona‐Kelvin characterization of the ferroelectric properties of Si:HfO2 thin films. Measurements were performed on free dielectric surfaces. The method uses corona charging pulses coupled with Kelvin probe‐measured surface voltage and gives non‐contact QV and CV characteristics. Analogous to voltage biasing of metal‐insulator‐metal (MIM) capacitors, large corona charge biasing is found to provide an effective means for poling of the ferroelectric films. Subsequent small increment corona charging is used to acquire hysteresis loops and determine the coercive field and permittivity characteristics. Negative and positive coercive fields of about ±1.2 MV/cm for the 3.5 mol% Si film and ±1.0 MV/cm for the 4.6 mol% Si film were determined from the hysteresis loops. These findings were in agreement with MIM capacitor measurements on sister wafers. Non‐ferroelectric behavior was also confirmed for the 11.3 mol% Si film. Another strength of the corona‐Kelvin method is the ability to perform full wafer mapping to assess spatial non‐uniformities of important dielectric properties. Results of this work indicate a radial symmetry of ferroelectric film properties, such as the permittivity at the coercive field, that are consistent with processing conditions during the crystallization anneal.

Poly-Si Planarization by ICP Plasma Etch at FinFET Technology

: The fin field effect transistors (FinFET) have been extensively explored for many years and recently mass production have been realized for its superior properties in solving short channel effects and size-down requirements. [1]In FinFET technology node, the topography started to turn worse due to the introduction of the three-dimensional (3D) fin structures. The control became one of the most important issues in FEoL. In poly-gate loop, the lithography window and poly silicon etch profile will be limited by the surface topography and thus affect the device performance as well as the yield improvement. To improve the poly-silicon topography after the CMP process becomes very important.In this paper, we report the poly-silicon planarization with the introduction of the matrix-temperature controller, named as Hydra, which is equipped in one commercial inductive coupled plasma (ICP) etch tool. The 3sigma of poly-silicon thickness within improved 80% and the uniformity is very close to current planar technology node, as shown in Figure 1. The temperature dependence is 21.7A/℃. The planarization results show better performance than gas cluster ion beam (GCIB) method as reported. [2] For more common use, an advanced process control is also proposed to overcome the difference of incoming after CMP process. The CMP process always shows a major radical thickness map, which can be compensated by tuning radical etch rate map by changing process parameters. The Hydra based etch planarization technology can also be extend to other process as ILD etch back with suitable etch process. This technology will be very power in the future 3D transistors for planarization.This work was partially sponsored by Program of Shanghai Technology Chief Scientist (B type). The authors would like to thank Mr. Kui Wang, Mr. Jiangang Liu, and Dr. Yushan Chi from Lam research for the support of constructive discussion. Reference: [1] C. Auth et al., “A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors,” in VLSI Symp. Tech. Dig., pp. 131–132, 2012, [2] T. Kagalwala et al., “Integrated metrology's role in Gas Cluster Ion Beam etch”, 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), pp. 72-77, 2015 Figure 1

Spatial analysis of failure sites in large area MIM capacitors using wavelets

The spatial distribution of failure sites in large area (104–105μm2) metal-insulator-metal (MIM) capacitors with high-K dielectric (HfO2) is investigated using angular wavelets. The failure sites are the consequence of constant or ramped electrical stress applied on the capacitors. Because of the important local thermal effects that take place during stress, the failure sites become visible as a point pattern on the top metal electrode. In case of less damaged devices, the results obtained with the wavelet variance method are consistent with an isotropic distribution of breakdown spots as expected for a Poisson point process (complete spatial randomness). On the contrary, for severely damaged devices, the method shows signs of preferred directions of degradation related to the voltage probe location. In this case, the anisotropy is confirmed by alternative spatial statistics methods such as the angular point-to-event distribution and the pair correlation function.