Millimeter-wave Amplifier Design Research Articles

Analysis and Design of a Voltage–Current Transformer Feedback Neutralization Network With an Arbitrarily Chosen Coupling-Factor

One of the transformer neutralization conditions derived theoretically in previous publications is to make the coupling factor, k, of the transformer as close to one as possible, which is not easy to realize over millimeter-wave frequency range. To seek a method for neutralizing the transistor gate-drain capacitance to cope with the imperfect reverse isolation with the transformer coupling factor not necessarily being close to one, a voltage-current transformer feedback network is adopted in this paper. A phase noninverting transformer is added between gate and drain nodes of a transistor to form a voltage-current feedback. The neutralization condition of this network is derived. The effect of this network on the gain is predicted theoretically. The noise behavior of this network is also analyzed and compared theoretically with other transformer feedback structures reported in the millimeter-wave amplifier design. A Q-band three-stage amplifier using this network is designed to demonstrate the feasibility of this network. This amplifier is implemented in 90-nm low-power bulk CMOS technology. Measurement results show that this amplifier has the peak gain of 18.3 dB at 46 GHz and the reverse isolation better than 40 dB over the operation frequency range while consuming 20 mW at a supply voltage of 1.2 V, which verifies the unilateralization effect by using this network.

New Performance Indicators of Metal–Oxide–Semiconductor Field-Effect Transistors for High-Frequency Power-Conscious Design

With the progress of complementary metal–oxide–semiconductor (CMOS) process technology, it is possible to apply CMOS devices to millimeter-wave amplifier design. However, the power consumption of the system becomes higher in proportion to its target frequency. Moreover, CMOS devices are biased at a point where the device achieves the highest gain and consumes much power. In order to reduce the power consumption without any compromise, we introduce two types of indicator. One works towards achieving the highest gain with the lowest power consumption. The other works towards achieving the highest linearity with consideration of the power consumption. In this work, we have shown the effectiveness of those indicators by applying measured data of the fabricated metal–oxide–semiconductor field-effect transistors (MOSFETs) to cascade common-source amplifiers.

Scalable Small-Signal Modeling of RF CMOS FET Based on 3-D EM-Based Extraction of Parasitic Effects and Its Application to Millimeter-Wave Amplifier Design

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> An accurate scalable small-signal RF CMOS model applicable to high frequencies is developed using 3-D electromagnetic (EM)-based extraction of parasitic elements. Due to multimetal layers, vertical interconnects, substrate loss and substrate-contact rings, the extrinsic parasitic network of CMOS field-effect transistor (FET) is more complicated than GaAs FETs and does not follow simple scaling rules. In this work, we have employed 3-D EM simulation to derive the scaling rules of the CMOS FETs. After de-embedding the effects of the pads and the interconnect lines using a pair of dummy patterns with different reference planes, the layout-dependent extrinsic network parameters are extracted using 3-D full-wave EM simulations. Based on the extracted parameters, new scaling rules are proposed for the extrinsic networks for 0.13 and 0.18 <formula formulatype="inline"><tex Notation="TeX">$\mu{\hbox{m}}$</tex></formula> CMOS processes. A complete scalable RF CMOS model is constructed by combining the scalable extrinsic network with the intrinsic CMOS network, and has been validated by comparing the predicted and measured <formula formulatype="inline"><tex Notation="TeX">$S$</tex></formula>-parameters of the scaled devices from a family of 0.18 and 0.13 <formula formulatype="inline"><tex Notation="TeX">$\mu{\hbox{m}}$</tex> </formula> CMOS FETs up to 50 and 75 GHz, respectively. In order to validate the scalable models for circuit applications, 30 and 60 GHz small-signal amplifiers have been designed using optimum size devices predicted from the scalable models. The measured results of the circuits are in good agreement with the simulation, validating the proposed modeling methods. </para>