Miller Compensation Research Articles

Low-voltage Low-power Bulk-driven CMOS Op-Amp Using Negative Miller Compensation for ECG

Two bulk-driven CMOS (Complementary Metal Oxide Semiconductor) operational amplifier (op-amp) designs for electrocardiogram (ECG) application are presented and compared in this paper. Both op-amps are based on two-stage amplification, where bulk-driven differential input is the first stage, while additional DC gain is the second stage. Different compensation techniques were integrated in each op-amp design. Standard Miller compensation was used for the first op-amp parallel with the second stage. The novelty of the second op-amp is that it utilizes negative Miller compensation between the bulk-driven input node and the output node of the first stag, while standard Miller compensation was used in the second stage. The purpose of this work was to compare DC gain, phase margin (PM) and unit gain frequency (UGF) obtained through different simulated compensation strategies and test results. The op-amps were simulated using 0.25 μm CMOS technology. The simulation results are presented using the standard model libraries from Tanner EDA tools, operating on a single rail +0.8V power supply.

A transient-enhanced low-dropout regulator with dynamic current boost technique voltage buffer

In this paper, a dynamic current boost technique voltage buffer is presented to enhance the large signal response of low dropout regulators (LDOs). The proposed buffer consists of AC coupling networks and active RC network. Without consuming excess power, this LDO achieves substantial improvement in load transient response. Meanwhile, an enhanced recycling-folded-cascode (RFC) amplifier is employed due to its higher gain, bandwidth and slew rate. In order to ensure the stability of full load, this design adopts simple Miller compensation with a nulling resistor without external equivalent series resistance. Moreover, this paper makes a detailed analysis of LDO in theory and the extensive experimental data verified it. The proposed LDO is successfully fabricated in SMIC 0.18μm CMOS process. The input voltage is 1.8–2.2V and the maximum load current is 200 mA. The experiment results indicate that the undershoot is 84 mV and there is no overshoot when the load current is varied from 0 to 200 mA within 100 ns under the load of 1μF load capacitor.

Three‐stage CMOSamplifier: Frequency compensated using fully differential block

AbstractThe advancement of CMOS technology limits designers' options for multi‐stage configurations as a promising alternative to cascade structures. The main issue of designing multi‐stage amplifiers is frequency compensation since cascade structures are volatile. An efficient three‐stage amplifier, which is frequency compensated using a fully differential block, is proposed in this work. The differential block enhances the Miller effect to reduce the size of compensation capacitors, and this leads to less die occupation. The compensation network shares the differential block between two Miller loops while two Miller capacitors at the outputs of the differential block cause pole‐zero cancelation to increase operating frequency range. The proposed structure is modeled by a linear transfer function and simulated via HSPICE software using CMOS library. Simulation results indicate excellent performance and acceptable robustness against parameter mismatches and probable fabrication errors. According to the simulations, the proposed amplifier has a DC gain of , a gain‐bandwidth product of , a phase margin of , and a power dissipation of . The high performance of the proposed three‐stage amplifier with an enhanced figure of merit makes it a perfect alternative to the amplifiers based on the conventional reverse nested Miller compensation.

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.

Analysis of Output Ripple Shape and Amplitude in Chopper Instrumentation Amplifier

In this brief, we analyzed the output ripple in a capacitively-coupled chopper-based instrumentation amplifier (CCIA). Our analysis found that the shape and amplitude of the output ripple of the CCIA are determined by five design parameters, namely amplifier offset, transconductance, chopping frequency, Miller compensation capacitance, and the nulling resistor. With different design specifications, the CCIA ripple appears in four different shapes, including triangular ripple, RC-settling ripple, square ripple, and step-change ripple. These findings are verified by the silicon results. As the cause of each ripple shape varies, this analysis serves as a guideline for designing practical chopper-based amplifiers and their corresponding ripple reduction techniques.

Area Optimisation of Two Stage Miller Compensated Op-Amp in 65 nm Using Hybrid PSO

Analog circuit design can be formulated as a nonlinear constrained optimisation problem that can be solved using any suitable optimisation algorithms. Different optimisation techniques have been reported to reduce the design time of analog circuits. A hybrid particle swarm optimisation algorithm with linearly decreasing inertia weight for the optimisation of analog circuit design is proposed in this study. The proposed method is used to design a two-stage operational amplifier circuit with Miller compensation. The results show that the proposed optimisation method can substantially reduce the design time needed for analog circuits.

A Low-Power Sigma-Delta Modulator for Healthcare and Medical Diagnostic Applications

This paper presents a switched-capacitor Sigma-Delta modulator designed in 90-nm CMOS technology, operating at 1.2-V supply voltage. The modulator targets healthcare and medical diagnostic applications where the readout of small-bandwidth signals is required. The design of the proposed A/D converter was optimized to achieve the minimum power consumption and area. A remarkable performance improvement is obtained through the integration of a low-noise amplifier with modified Miller compensation and rail-to-rail output stage. The manuscript also presents a set of design equations, from the small-signal analysis of the amplifier, for an easy design of the modulator in different technology nodes. The Sigma-Delta converter achieves a measured 96-dB dynamic range, over a 250-Hz signal bandwidth, with an oversampling ratio of 500. The power consumption is <inline-formula> <tex-math notation="LaTeX">$30~\mu \text{W}$ </tex-math></inline-formula>, with a silicon area of 0.39 mm².

A Low‐Voltage Hybrid CMOS‐Memristor‐Based Wideband Class‐AB Amplifier for Portable Electronic Device Applications

This paper presents a low‐voltage high‐gain wideband three‐stage true‐class‐AB amplifier. This is realized in the 0.18 μm CMOS process. The three‐stage class‐AB amplifier is proposed based on a compensation topology called nested Miller compensation along with a memristor to get pole‐zero cancellation, which arises beyond the unity gain frequency. The circuit is implemented without the need for extra components as transistors, resistors, and capacitors, thus saving the complexity of the circuit and power consumption. The circuit is designed to operate with a supply voltage of ±1 V along with a bias current of 175 μA. The simulation results indicate that this proposed amplifier is capable of driving wide range of resistive and capacitive loads, furthermore capable of maintaining a phase margin of more than 60°. The total compensation capacitor is 2 pF, which is much lesser as compared to pseudo‐ and true‐class AB amplifier, which implies a reduction in area. Simulation results show that the unity gain frequency of the proposed class‐AB amplifier is 136.7 MHz, which is much higher as compared to the counterpart topologies. The major advantage associated with this work is a very high bandwidth attained without affecting the gain of the amplifier.

A Low-Power Wide-Load-Range Output-Capacitorless Low-Dropout Voltage Regulator With Indirect-Direct Nested Miller Compensation

This paper presents the design of an output-capacitorless low-dropout voltage regulator (OCL-LDO) capable of driving a wide range of load capacitance and supplying a wide range of load current while maintaining excellent load and line regulations, thanks to the combined indirect-direct nested Miller compensation which ensures stability and maintains a high loop gain over the whole range of load condition. Fabricated in a 0.18-&#x03BC;m CMOS process and consuming 14 &#x03BC;A of quiescent current, the OCL-LDO, while supplying the load current between 0 mA to 100 mA, is capable of driving the load capacitance in the range of 0-1 nF; with a minimum load current of 1 mA, however, the OCL-LDO can drive up to 10 nF of load capacitance. Over such wide load-current and load-capacitance ranges, the OCL-LDO achieves DC load and line regulations of 0.025 mV/mA and 0.5 mV/V, respectively.

A Low-Voltage, Ultra-Low-Power, High-Gain Operational Amplifier Design for Portable Wearable Devices

Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW.

Improved reversed nested miller frequency compensation techniques using flipped and folded flipped voltage follower with resistor for three stage amplifier

This paper presents three circuits to improve frequency compensation in three stage amplifier for large capacitive load of 100 pF. The first proposed circuit introduces Flipped Voltage Follower (FVF) in inner loop of Reversed Nested Miller Compensation (RNMC) to combat RHP zero whereas both second and third proposed circuits employ A Folded Flipped Voltage Follower (FFVF). The third proposed circuit uses an additional resistor in the outer compensation loop for double pole-zero cancellation. Further feed forward path has been used in all proposed circuits to improve the large signal response. The functionality is verified using TSMC 0.18 µm CMOS technology parameters in Tanner tool. The simulation results show maximum gain-bandwidth product (GBW) of 30 MHz, minimum phase margin (PM) of 60° and slew rate (SR) of 10 V/µS, and minimum common mode rejection ratio (CMRR) of 37.2 dB at unity gain frequency. The input-referred noise of the proposed circuits varies from 16.6 nV/Hz to 18.2 nV/Hzat unity gain frequency. Corner analysis is also included to show the robustness of the circuits.

A 1.8‐V 240‐MHz 2.19‐mW Four‐Stage CMOS OTA with a Segmenting Frequency Compensation Technique

A four-stage Operational transconductance amplifier (OTA) used in an infrared temperature sensor adopting the proposed Feed-forward Gm-stage and segmenting nested Miller compensation technique is presented. The purpose of the proposed segment compensation is primarily to make more amplifier stages concatenated. The circuit linked several transconductance stages to form a segment, and linked several segments to form a large multistage amplifier. For example, a two-stage amplifier linked with a three-stage amplifier can realize a five-stage amplifier, two three-stage amplifiers linked can realize a six-stage amplifier. A four-stage amplifier in the form of 2+2 (two stages and two stages) was used as an example to verify this compensation method. The proposed OTA is designed in the 180nm complementary metal oxide semiconductor process. It consists of two parts which ensure the stability and improve the bandwidth performance. The first part is a feed-forward transconductance stage, and the second part is the two-segment transconductance stages with the Miller compensation techniques employed within and between the two segments. Based on the small-signal model, stability analysis and theoretical derivation are performed in theory. On condition of a 2-pF load capacitance, a direct current gain of 109dB and a gain-bandwidth of 240MHz with a phase margin of 50° can be achieved. The proposed design consumes 2.19mW in a 1.8-V supply voltage. The transient simulation indicates that the settling time of the output is 19ns with the settling error being 1%, and the slew rate is 114V/μs.

High-Speed CMOS Three-Stage Amplifier Based on Feedback Attenuation

This paper presents a new and simple frequency compensation scheme for multistage CMOS operational transconductance amplifiers (OTAs). In this work, by applying a differential block frequency compensation (DBFC) technique to a compensation network of three-stage OTA, the dominant pole is drastically improved independent from the DC gain path. The DBFC introduces amplified signal directly to the second-stage output through the compensation capacitor. The signal injection increases operational frequency range while just a single and small value capacitor is used as the Miller capacitor, which leads to considering the proposed configuration as a low die area occupation and high-speed amplifier. The simulation results show with the same capacitive load and power dissipation the gain bandwidth (GBW) frequency can be improved considerably compared to conventional nested Miller compensation. The presented circuit is simulated in a 0.18[Formula: see text][Formula: see text]m CMOS technology with a 1.8[Formula: see text]V supply voltage. According to the results, the proposed circuit shows 102[Formula: see text]dB, 105[Formula: see text]MHz, and 343[Formula: see text][Formula: see text]W as the DC gain, GBW, and power consumption, respectively.

A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Sizing of multi-stage Op Amps by combining design equations with the gm/ID method

Analog integrated circuit design has as integral parts both analytical reasoning and numerical validation in the process from topology construction to sizing. Given a circuit topology, different circuit sizing results can be obtained from different processes of sizing inference. Sizing methods by simulation-based numerical searching have been a continuously studied subject. However, almost all approaches in this category require an overwhelming number of circuit simulations to arrive at an optimized sizing result. On the other hand, many published manual sizing methods by using the conventional device equations also require repeated SPICE simulations to correct the equation-based sizing results. This paper proposes a systematic gm/ID-based initial sizing method specifically customized for designing multiple-stage operational amplifiers (Op Amps). A main feature of the proposal is to use circuit-level design equations as constraints on the gm/ID table lookup method to substantially reduce the uncertainty in the sizing calculations. As a result, a significant amount of SPICE based correction work can be reduced to complete an initial sizing. The proposed sizing procedure includes a few regular sizing rules customized to the configuration of multi-stage Op Amps. We validate the proposed sizing method by application to several multi-stage Op Amp examples with a capacitive load or Miller compensation. Simulations have justified that the produced initial sizing results can achieve most of the prespecified design targets.

Improved Frequency Compensation Technique for Three-Stage Amplifiers

Improved frequency compensation is proposed for a three-stage amplifier with reduced total capacitance, improved slew rate, and reduced settling time. The proposed compensation uses an auxiliary feedback to increase the total effective compensation capacitance without loading the output node. The proposed compensation scheme is validated in simulation by implementing a three-stage amplifier driving 10 pF load capacitor in a 0.18 μm CMOS process. A detailed comparison of the compensation with a conventional nested Miller compensation is also presented. The simulation results showed a reduction in total compensation capacitance and improvement in slew rate compared to conventional nested Miller compensation and the other reported techniques in the literature.

An output capacitor‐less low‐dropout regulator with wide load capacitance and current ranges

SummaryThis paper presents an output capacitor‐less low‐dropout regulator (LDO) with wide load capacitance and current ranges. A new Miller compensation technique called multipath double‐nested Miller compensation with Q‐reduction circuit is introduced to extend the ranges of the load capacitance and current. Besides, a multiple small‐gain stages technology is applied to improve the loop gain of the LDO, achieving better management accuracy. The proposed LDO was fabricated in a 130‐nm CMOS process. The measured maximum load capacitance can be extended to 4.7 nF, and the maximum load current is 80 mA. Moreover, the measured line regulation and load regulation are 4 mV/V and 0.154 mV/mA, respectively.

An Enhanced Gain-Bandwidth Class-AB Miller op-amp With 23,800 MHz·pF/mW FOM, 11-16 Current Efficiency and Wide Range of Resistive and Capacitive Loads Driving Capability

A compact power-efficient class-AB Miller op-amp is introduced. It uses a simple auxiliary circuit that enhances the op-amp’s gain-bandwidth product and helps to drive a wide range of capacitive and resistive loads with high static and dynamic current efficiency. Simple Miller compensation is used to obtain stability over a wide range of loading conditions. The op-amp’s simulation and experimental results in strong inversion with $15\mu \text{A}$ bias current and in sub-threshold with 250nA bias current are shown. Its performance is measured in terms of dynamic and static current efficiency figures of merit FOMCEDyn and FOMCEStat. and using the conventional small-signal figure of merit FOMSS. Experimental results of op-amps fabricated in a 130nm CMOS technology are shown that validate the proposed approach.

A Dynamic Compensated and 95% High-Efficiency Supply Buffer in RGB Virtual Pixel MicroLED Display for Reducing Ghosting by 73% and Achieving Four Times Screen Resolution

This article proposed micro light emitting diode (microLED) virtual pixel array design and driver. The proposed virtual pixel array effectively increases the pixels per inch and reduces parasitic capacitance for alleviating ghosting effects. The push-pull supply buffer in the proposed driver is compensated by the dynamic Miller compensation technique to achieve fast transient response and reduce the ghosting by 50%-73%. Four times screen resolution can be obtained compared to conventional designs. A 95% high-efficiency microLED driver has the lowest 45 μW power consumption. The proposed supply buffer can drive microLEDs in 51-inch display panel, which is composed of 214 small 96 × 64 microLED panels for automotive display.

A 0.3-V 8.72-nW OTA with Bulk-Driven Low-Impedance Compensation for Ultra-Low Power Applications

A bulk-driven low-impedance compensation technique is proposed for ultra-low supply voltage amplifiers. By using the low resistance node of the current mirror of input, the efficiency of Miller compensation capacitor is greatly improved. By using this compensation method, a rail-to-rail input & output bulk-driven fully differential operational amplifier is also presented in the paper. The effectiveness of the circuit has been verified in a 65 nm CMOS process, the proposed three-stage amplifier has over 70.69 dB gain, 19.95 kHz gain-bandwidth product, and 69.7° phase margin while consuming only 8.72 nW power, and occupying die area of 0.00082 mm2 from a 0.3 V supply while driving a 100pF load.