Abstract

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Highlights

  • In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as Internet of Things (IoT) or biomedical devices

  • We present a novel OTA topology based on a body-driven input stage with a dual path to improve common-mode rejection ratio (CMRR) that exploits body-driven current mirror load for differential-to-single-ended conversion at the output

  • The small-signal FOMs (25) and (27) measure the efficiency of the OTA in providing high-frequency performance, since they measure the gain–bandwidth product, which is normalized to the load capacitance, for a given power consumption

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Summary

Introduction

The development of ultra-low-power (ULP) and ultra-low-voltage (ULV) integrated circuits is driven by applications such as the Internet of Things (IoT) [1,2,3,4] and implanted biomedical devices [5,6,7,8]. When targeting supply voltages lower than 0.4 V, the adoption of the topologies and design strategies reported above is no longer possible, and pseudo-differential or inverter-based architectures are often used [25,26,27,28,29,30,31,32]. At these supply voltages, gate-driven amplifiers are not adequate for ensuring a rail-to-rail input common-mode range (ICMR).

Proposed Topology
Differential Gain Frequency Response
Common-Mode Gain
Noise Analysis
Large-Signal Analysis
Sizing
Circuit Simulations
Robustness to Mismatch and PVT Variations
Results and Comparison with the Literature
Conclusions
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