Miller Compensation Technique Research Articles

A low dropout regulator design with 20.4 μA quiescent current and high power supply rejection

This paper presents a novel low dropout (LDO) regulator distinguished by its high power supply rejection (PSR) and low quiescent current. A capacitive feed-forward ripple cancellation (CFFRC) technique is introduced to effectively cancel power supply noise while simultaneously minimizing quiescent current. Additionally, the design incorporates feed-forward capacitors and back-to-back pseudo-resistors biasing to achieve reduced power consumption. Furthermore, the integration of negative feedback super source follower and Miller compensation techniques enhances the stability of the LDO. Fabricated using 180 nm CMOS technology, the LDO exhibits a quiescent current consumption of 20.4 μA. Experimental results demonstrate a maximal improvement of −41.55 dB in PSR compared to an LDO lacking these enhancements, with a maximum load current capability of 120 mA.

Multi-zero pole dynamically compensated LDO with low quiescent current

This paper presents an LDO design tailored to the various power domains of CPUs. In contemporary CPU designs, different functional modules typically necessitate distinct voltage levels, thus requiring a flexible and adjustable power management approach. An LDO with an internally compensated super source follower (SSF) and a multi-zero-pole compensated loop stability is proposed. The SSF is used to reduce the output impedance of the LDO, enhancing its carry-under-load capability. The loop is then transformed into a multi-zero-pole system through Miller compensation, feed-forward compensation, and zero-pole tracking compensation techniques, enabling the LDO to achieve stability and reliability under different loads. The LDO proposed in this study was designed using a 110 nm CMOS process. The LDO can operate within a temperature range of −40–150 °C, with a low quiescent current of 57 μA. The power supply rejection ratio of the circuit is −22 dB at 1 MHz. When the load current jumps from 5 mA to 300 mA within 40 μs, the output voltage experiences an undershoot of 271 mV, an overshoot of 174 mV, and a maximum adjustment time of 100 μs. The load regulation is 0.00267 mV/mA, and the line regulation is 1 mV/V.

Ultra-Low Power Programmable Bandwidth Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply for Biomedical Applications

This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm2. With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µVrms, a closed-loop gain (AV) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results.

An NMOS transistor-based high-gain operational amplifier designed in 0.25-micron CMOS technology

This project describes in detail the process of designing and simulating at first a one stage folded cascode operational amplifier using 0.25 um CMOS Technology with the self-biasing scheme for the NMOS differential input stage is discussed here. The design of the required circuits is done using the LTspice simulator. We will see that the simulation results approximately matches with the desired and theoretically calculated performance values. We are changing width values to bring all the transistors of the circuit in saturation. Then two Stage Folded Cascode Operational Amplifier with Miller compensation technique for the NMOS input. The operational amplifiers circuit is designed with 0.25 µm CMOS Technology using LTspice software. The applied methodology to implement the circuit design for a given specification has clearly described including all the design equation has been presented. All the parameter like DC Gain and Phase Margin (PM) are presented and discussed. Finally, we have got after performance analysis that designed circuit based on NMOS input provide a 96 DC Gain.

Improved reversed nested miller frequency compensation techniques using flipped and folded flipped voltage follower with resistor for three stage amplifier

This paper presents three circuits to improve frequency compensation in three stage amplifier for large capacitive load of 100 pF. The first proposed circuit introduces Flipped Voltage Follower (FVF) in inner loop of Reversed Nested Miller Compensation (RNMC) to combat RHP zero whereas both second and third proposed circuits employ A Folded Flipped Voltage Follower (FFVF). The third proposed circuit uses an additional resistor in the outer compensation loop for double pole-zero cancellation. Further feed forward path has been used in all proposed circuits to improve the large signal response. The functionality is verified using TSMC 0.18 µm CMOS technology parameters in Tanner tool. The simulation results show maximum gain-bandwidth product (GBW) of 30 MHz, minimum phase margin (PM) of 60° and slew rate (SR) of 10 V/µS, and minimum common mode rejection ratio (CMRR) of 37.2 dB at unity gain frequency. The input-referred noise of the proposed circuits varies from 16.6 nV/Hz to 18.2 nV/Hzat unity gain frequency. Corner analysis is also included to show the robustness of the circuits.

A 1.8‐V 240‐MHz 2.19‐mW Four‐Stage CMOS OTA with a Segmenting Frequency Compensation Technique

A four-stage Operational transconductance amplifier (OTA) used in an infrared temperature sensor adopting the proposed Feed-forward Gm-stage and segmenting nested Miller compensation technique is presented. The purpose of the proposed segment compensation is primarily to make more amplifier stages concatenated. The circuit linked several transconductance stages to form a segment, and linked several segments to form a large multistage amplifier. For example, a two-stage amplifier linked with a three-stage amplifier can realize a five-stage amplifier, two three-stage amplifiers linked can realize a six-stage amplifier. A four-stage amplifier in the form of 2+2 (two stages and two stages) was used as an example to verify this compensation method. The proposed OTA is designed in the 180nm complementary metal oxide semiconductor process. It consists of two parts which ensure the stability and improve the bandwidth performance. The first part is a feed-forward transconductance stage, and the second part is the two-segment transconductance stages with the Miller compensation techniques employed within and between the two segments. Based on the small-signal model, stability analysis and theoretical derivation are performed in theory. On condition of a 2-pF load capacitance, a direct current gain of 109dB and a gain-bandwidth of 240MHz with a phase margin of 50° can be achieved. The proposed design consumes 2.19mW in a 1.8-V supply voltage. The transient simulation indicates that the settling time of the output is 19ns with the settling error being 1%, and the slew rate is 114V/μs.

An output capacitor‐less low‐dropout regulator with wide load capacitance and current ranges

SummaryThis paper presents an output capacitor‐less low‐dropout regulator (LDO) with wide load capacitance and current ranges. A new Miller compensation technique called multipath double‐nested Miller compensation with Q‐reduction circuit is introduced to extend the ranges of the load capacitance and current. Besides, a multiple small‐gain stages technology is applied to improve the loop gain of the LDO, achieving better management accuracy. The proposed LDO was fabricated in a 130‐nm CMOS process. The measured maximum load capacitance can be extended to 4.7 nF, and the maximum load current is 80 mA. Moreover, the measured line regulation and load regulation are 4 mV/V and 0.154 mV/mA, respectively.

A Dynamic Compensated and 95% High-Efficiency Supply Buffer in RGB Virtual Pixel MicroLED Display for Reducing Ghosting by 73% and Achieving Four Times Screen Resolution

This article proposed micro light emitting diode (microLED) virtual pixel array design and driver. The proposed virtual pixel array effectively increases the pixels per inch and reduces parasitic capacitance for alleviating ghosting effects. The push-pull supply buffer in the proposed driver is compensated by the dynamic Miller compensation technique to achieve fast transient response and reduce the ghosting by 50%-73%. Four times screen resolution can be obtained compared to conventional designs. A 95% high-efficiency microLED driver has the lowest 45 μW power consumption. The proposed supply buffer can drive microLEDs in 51-inch display panel, which is composed of 214 small 96 × 64 microLED panels for automotive display.

A reconfigurable high ultimate rejection inductorless band‐pass filter by the use of N‐path passive mixers

SummaryIn this paper, a band‐pass filter with a tunable bandwidth and the center frequency is introduced, which employs N‐path and N × M‐path passive mixer structures, for multiband multistandard wireless receivers. The center frequency of the proposed filter is tunable from 0.1 to 1 GHz, while its bandwidth is also adjustable from 6% to 34% of the center frequency at 100 MHz. The passband ripple is reduced by applying a Miller compensation technique, resulting in a worst‐case ripple of only 1.6 dB over the entire tuning range. An additional eight‐path filter is also utilized at the input of the circuit, which highly improves the out‐of‐band rejection of the filter as well as its out‐of‐band linearity. The noise figure and the input return loss are, respectively, better than 5 and 10 dB, and depending on the desired center frequency, the total power consumption of the proposed filter varies from 41 to 70 mW.

Implementation of an Ultra Low Power Process-Insensitive Two Stage Complementary Metal Oxide Semiconductor Operational Amplifier with Enhanced Direct Current Gain at 45 nm Technology Node

This paper presents an ultra low power process-insensitive two stage CMOS OP-AMP employing bulk-biasing technique realised in a standard 45 nm CMOS technology. Bulk-Biasing technique has been employed to augment the DC gain of two stage CMOS OP-AMP without having any impact on its power dissipation and output swing. In this work, high gain-bandwidth product (GBW) with appropriate phase margin is achieved through pseudo-cascode compensation approach which overcomes the drawbacks of Miller compensation technique also. Furthermore, the effect of width scaling on performance metrics of proposed OP-AMP has been analysed. The designed OP-AMP exhibits enhanced DC gain of 94.2 dB, gain-bandwidth product (GBW) of 460 MHz and adequate phase margin of 80°; with fast settling response. Also, the proposed OP-AMP has power dissipation of 27 μW and leakage current of 6.4 pA only. The design and optimisation of proposed OP-AMP is carried out at a power supply of 0.7 V under room temperature in Cadence Virtuoso tool.

Nested Miller Compensation Based Op-Amp Design for Piezoelectric Actuators

This study introduces the design of a practical three-stage operational amplifier (op-amp) using nested Miller compensation, particularly for piezoelectric actuators. Driving a piezoelectric actuator represents a challenge in amplifier design due to its large capacitive nature. A stable piezo driver needs to be free of oscillations and phase lag. Direct feedback compensation using a conventional Miller capacitor is an effective method as long as the capacitance of the load is considerably close to the value of the Miller capacitor. However, using a large capacitor causes a decrease in the slew rate and gain bandwidth. To avoid this, our design focused on the utilization of nested Miller compensation technique. A prototype of the design working at 100V peak to peak voltage (Vpp) is implemented using commercial off-the-shelf (COTS) components. The measurements show the successful driving capability and step-response of the op-amp design. In the design, Widlar current source is also utilized for thermal stability and short circuit protection. According to simulation results, the proposed op-amp has a slew rate of 0.5 V/μs, an open loop gain of 90dB with 3MHz Gain Bandwidth Product (GBP) and phase margin of 77°, and a common mode rejection ratio (CMRR) of 62dB.

A Two-Module Linear Regulator with 3.9–10 V Input, 2.5 V Output, and 500 mA Load

A linear regulator with an input range of 3.9–10 V, 2.5 V output, and a maximal 500 mA load for use with battery systems was developed and presented here. The linear regulator featured two modules of a preregulator and a linear regulator core circuit, offering minimized power dissipation and high-level stability. The preregulator delivered an internal power voltage of 3 V and supplied internal circuits including the second module (the linear regulator core). The preregulator fitted with an active, low-pass filter provided a low-noise reference voltage to the linear regulator core circuit. To ensure operational stability for the linear regulator, error amplifiers incorporating the Miller compensation technique and featuring a large slewing rate were employed in the two modules. The circuit was successfully implemented in a 0.25 µm, 5 V complementary metal-oxide semiconductor (CMOS) process featuring 20 V drain-extended MOS (DMOS)/bipolar high-voltage devices. The total silicon area, including all pads, was approximately 1.67 mm2. To reduce chip area, bipolar rather than DMOS transistors served as the power transistors. Measured results demonstrated that the designed linear regulator was able to operate at an input voltage ranging from 3.9 to 10 V and offer a maximum 500 mA load current with fixed 2.5 V output voltage.

Design and Analysis of Three-Stage Amplifier for Driving pF-to-nF Capacitive Load Based on Local Q-Factor Control and Cascode Miller Compensation Techniques

This paper presents a new frequency compensation approach for three-stage amplifiers driving a pF-to-nF capacitive load. Thanks to the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively, and the physical size of the compensation capacitors is also reduced. A local Q-factor control (LQC) loop is introduced to alter the Q-factor adaptively when loading capacitance CL varies significantly. This LQC loop decides how much damping current should be injected into the corresponding parasitic node to control the Q-factor of the complex-pole pair, which affects the frequency peak at the gain plot and the settling time of the proposed amplifier in the closed-loop step response. Additionally, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Simulated in 0.13-µm CMOS technology, the amplifier is verified to handle a 4-pF-to-1.5-nF (375× drivability) capacitive load with at least 0.88-MHz gain-bandwidth (GBW) product and 42.3° phase margin (PM), while consuming 24.0-µW quiescent power at 1.0-V nominal supply voltage.

Performance enhancement of advanced recycling folded cascode operational transconductance amplifier using an unbalanced biased input stage

This paper presents a technique to enhance an overall performance of advanced recycling folded cascode operational transconductance amplifier (RFC OTA). It adopts an input stage comprising a cross coupled MOS differential pair biased by a constant DC current source in addition to an adjustable floating voltage source. The proposed modification shows a substantial improvement in transconductance leading to boost dc gain, gain-bandwidth and slew rate of conventional FC-OTA. The structure is designed and implemented in 0.18 μm CMOS technology. In addition to transconductance enhancement, a remarkable improvement in a phase margin is achieved using a Miller compensation technique to ensure the stability of OTA. The simulation results demonstrate the performance of the proposed OTA with 72 dB gain and unity gain bandwidth of 128 MHz for a capacitive load of 10 pF. The modified RFC OTA shows 550% improvement in gain bandwidth product (GBW) and 20 dB hike in the gain compared to the conventional FC-OTA, which has 19.85 MHz GBW and 51.9 dB respectively. The Miller compensated OTA shows 36% improvement in a phase margin compared to non-compensated OTA with a slight reduction of 6% in GBW.

Improved reversed nested miller frequency compensation technique based on current comparator for three-stage amplifiers

This paper attempts to propose a newly modified method to improve the frequency compensation of three-stage operational trans-conductance amplifiers. In the topology of the new frequency compensation, a current comparator is placed on the feedback path, while the common node of Miller compensation capacitors, the feedforward path, is removed by eliminating the right-half plane zero. This tremendously improves the phase margin, stability, and gain band width product. Compared with other available frequency compensation methods, the newly proposed method manages to improve the figure of merits and lower power consumption while significantly decreasing the dimensions of capacitors in the compensation network. The superiority of the new method over other conventional methods for reversed nested Miller compensation has been examined by a three stage amplifier that has been designed and simulated through a 180 nm standard library CMOS. The results indicate that the new amplifier has achieved a power consumption of 285 µW, gain band width product of 14 MHz, and phase margin of 86° with 100 pF capacitance load at the supply voltage of 1.8 V.

Fast-transient capacitor-less low-dropout regulator with input current-differencing and dynamic current-boosting

Transient response improvement of a capacitor-less low-dropout regulator with input current-differencing is presented in this paper. The Miller compensation technique with series resistance is used to establish the stability and reduce the on-chip capacitor. As a result, the on-chip compensation capacitor of the proposed LDO is reduced to 4 pF which makes it suitable for portable SoC applications. The dynamic current-boosting technique is simultaneously applied to both the input current and the gate of the pass transistor to improve the line and load transient responses of the proposed LDO. The output voltage is regulated at 1 V with a dropout voltage of about 100 mV. The proposed circuit is simulated in TSMC 0.18 μm CMOS technology and its quiescent current is 42 μA. The simulation results of both the line and load transient responses show considerable improvement in the over/undershoot and the settling time of the proposed LDO as well as better transient performance compared to the similar previous works. The output voltage over/undershoot amplitudes of the proposed LDO are obtained 46/100 mV with the settling time of less than 2 μs for the load current changes from 0.1 to 100 mA with 1 µs rise/fall times.

A transconductance-enhancement cascode Miller compensation for low-power multistage amplifiers

A transconductance-enhancement cascode Miller compensation technique is proposed for low supply-power, large or very large capacitive load multistage amplifiers. By using the transconductance-enhancement operational amplifiers and the local impedance attenuation network, both the gain bandwidth and setting time are thus significantly improved. The effectiveness of the method has been verified in a 0.18 μm CMOS process, the proposed three-stage amplifier has over 100 dB gain, 6.5 MHz gain-bandwidth product, and 0.83 V/μs slew rate while consuming 23 μW power from a 1.2 V supply while driving a 560 pF load.

A three-stage class AB operational amplifier with enhanced slew rate for switched-capacitor circuits

In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.

Analysis and Design of a Two Stage CMOS OPAMP with 180nm using Miller Compensation Technique

Analysis and Design of a Two Stage CMOS OPAMP with 180nm using Miller Compensation Technique

A Low Power Low Noise Chopper-Stabilized Tow-stage Operational Amplifier for Portable Bio-potential Acquisition Systems Using 90 nm Technology

This paper presents a high performance chopper-Stabilized Two-stage operational amplifier for biomedical applications. This Two-stage is designed for low noise, low power, high PSRR and high CMRR. The Miller compensation technique (Cc) is used with a nulling active resistance (Rz) implemented using Transmission gate (TG) transistors for stable operation in feedback mode. Chopper stabilization technique has been widely used in amplifiers for flicker (1/f) noise and offsets reduction purposes using the principles of modulation and demodulation. Thus, the functionality and performance of modulation and demodulation circuits determines the realization and attainment of chopper stabilization. The operational amplifier was manufactured in a SPECTRE using GPDK 90nm CMOS technology with threshold voltages of a 0.17 V and - 0.14 V achieve a low power 2.6uW,