Microvertex Detector Research Articles

Characterization of the radiation tolerant ToASt ASIC for the readout of the PANDA MVD strip detector

The ToASt ASIC is a 64-channel integrated circuit developed for the readout of the Silicon strip detector project designed to be placed in the Micro-Vertex Detector of the PANDA experiment. ToASt is implemented in a commercial 110 nm CMOS technology and can provide information on the position, time, and deposited energy of the particle passing through the detector. Its time resolution is given by its 160 MHz master clock.The ASIC has been developed in the framework of the European FAIRnet project.The chip has been characterized electrically both standalone and coupled with sensors, with focus on its noise performances. It has also been tested for radiation tolerance, both in terms of Total Ionizing Dose and Single Event Upset.In particular, this work aims to guarantee that the studied ASICs can sustain the levels of ionizing radiation expected in the PANDA experiment and to study the noise characteristics for the two polarities of the ASIC.

The data acquisition system for the PANDA Micro-Vertex Detector

The PANDA (antiProton ANnihilation at DArmstadt) experiment will study the strong interaction in annihilation reactions between an antiproton beam and a stationary cluster jet target. The PANDA detector will be composed of several sub-detectors designed for tracking, particle identification and calorimetry. The Micro-Vertex Detector (MVD) is the innermost part of the tracking system surrounding the interaction region, which is designed for precise vertex and tracking detection. It consists of silicon pixel and double-sided microstrip detectors. For the readout of the microstrip sensors an ASIC called ToASt (Torino Asic for Strip readout) is being developed in 0.11 μm CMOS technology at INFN Turin. The ASIC takes advantage of both Time-over-Threshold and Time-of-Arrival methods to accurately measure the event's energy and timestamp. To sustain the acquisition of the microstrip sensors a MDC (Module Data Concentrator) ASIC is under development at KIT. Up to eight ToASt front-ends' data streams are multiplexed, read out and processed by one MDC. The data of several MDCs are collected and processed by the off-detector readout card MMB (MVD Multiplexer Board), also under development at KIT. The processed data is then transferred via 100 GbE optical links to the computing nodes. The ToASt chips have been integrated with the FPGA implementation of the MDC to form the first fully functional detector module. Beam tests have been performed at the COSY facility in Jülich. This paper focuses on the design of MDC ASIC and MMB board, the integration with the ToASt and presents preliminary beam test results.

A high time resolution and high dynamic range ASIC for the micro-vertex detector in the PANDA experiment

A monolithic pixel sensor test chip for the PANDA micro-vertex detector has been implemented in a 180 nm HVCMOS technology on a high resistivity substrate. The sensor should have very high time resolution (1 ns sigma) and high dynamic range (up to 1000). The pixel electronics contains a charge sensitive amplifier, a feedback circuit and two comparators. One comparator receives the fast signal and enables accurate time measurement. The other comparator receives the low pass filtered signal and is used for precise amplitude measurement. This publication presents several novel features of the PANDA ASIC, its characterization and several measurement results.

Tolerance of the MIMOSIS-1 CMOS Monolithic Active Pixel Sensor to ionizing radiation

MIMOSIS is a CMOS Monolithic Active Pixel Sensor (CPS) developed to equip the Micro Vertex Detector (MVD) of the Compressed Baryonic Matter (CBM) experiment at FAIR/GSI. The sensor will combine a spatial resolution of -5 µm with a time resolution of 5 µs and provide a peak hit rate capability of ∼80 MHz/cm2. To fulfil its task, MIMOSIS will have to withstand ionising radiation doses of ∼5 MRad and fluences of ∼7 × 1013 neq/cm2 per year of operation.The paper summarises major requirements of the CBM-MVD and compares them to the detection performances of the first full scale prototype, called MIMOSIS-1, recently evaluated in the laboratory and with particle beams. The tolerance of the sensor to the expected ionising radiation load was evaluated; the paper describes the measurements performed and their outcome.

A 64 channels ASIC for the readout of the silicon strip detectors of the PANDA micro-vertex detector

The ToASt ASIC is a 64 channel integrated circuit designed for the readout of the double-sided silicon strip sensors that will equip the micro-vertex detector of the PANDA experiment. The ToASt ASIC operates with a 160 MHz clock, which defines also the time resolution. A common time stamp is distributed to all channels to provide a common time reference for time of arrival and time over threshold measurements. Two 160 Mb/s serial lines provide the interface to the data concentrator. ToASt is implemented in a commercial 110 nm CMOS technology with triplicated logic to protect against single event upsets.

Heavy Flavor and Quarkonia Physics at sPHENIX

The sPHENIX detector, being constructed at BNL’s Relativistic Heavy Ion Collider (RHIC), will begin measuring a plethora of Heavy Flavor and Quarkonia observables with unprecedented statistics and kinematic reach at RHIC energies starting in 2023. This includes the largest recorded sample of b-flavored hadron decays from Heavy Ion collisions at RHIC, allowing for precise probes of the QGP using charm and beauty quarks. These measurements are enabled by the excellent vertexing of the MAPS-based micro-VerTeX detector (MVTX), timing of the INTermediate silicon strip Tracker (INTT), precision tracking by the Time Projection Chamber (TPC), and the ElectroMagnetic and Hadronic Calorimetry systems (EMCal and HCal, respectively), the latter of which is deployed for the first time at RHIC. The sPHENIX collaboration has created the reconstruction software stack as well as realistic data simulations, which allow for testing and optimization of the software and physics selections.

Observations on MIMOSIS-0, the first dedicated CPS prototype for the CBM MVD

The Micro Vertex Detector (MVD) of the future Compressed Baryonic Matter (CBM) experiment at FAIR will have to provide a spatial precision of ∼5μm in combination with a material budget of 0.3%–0.5%X0 for a full detector station. Simultaneously, it will have to handle the rate and radiation load of operating the fixed target experiment at an average collision rate of 100kHz (4–10AGeV Au+Au collisions) or 10MHz (up to 28GeV p-A collisions). The harsh requirements call for a dedicated detector technology, which is the next generation CMOS Monolithic Active Pixel Sensor MIMOSIS. We report about the requirements for the sensor, introduce the design approach being followed to cope with it and show first test results from a first sensor prototype called MIMOSIS-0 .

Status of the vertex detector program of the CBM experiment at FAIR

The Compressed Baryonic Matter Experiment (CBM) is one of the core experiments of the future FAIR facility (Darmstadt/Germany). The fixed-target experiment will explore the phase diagram of strongly interacting matter in the regime of high net baryon densities with numerous rare probes. The Micro Vertex Detector (MVD) will determine the secondary decay vertex of open charm particles with $\sim 50~\rm \mu m$ precision, contribute to the background rejection in dielectron spectroscopy, and help to reconstruct neutral decay products of strange particles by means of missing mass identification. The MVD comprises four stations with 0.3 and $0.5\%~x/X_0$, which are placed between $5$ and $20~\rm cm$ downstream the target and inside vacuum. It will host highly-granular, next-generation Monolithic Active Pixel Sensors, with a spatial precision of $5\rm~\mu m$, a time resolution of $5 ~\rm \mu s$, and a peak rate capability of $\sim 700~\rm kHz/mm^2$. Moreover, a tolerance to $3\cdot10^{13}~\rm n_{eq}/cm^{2}$ and $\gtrsim 3~\rm Mrad$ are required. In this document, we summarize the status of sensor development, station prototyping, and the detector slow control.

The PANDA Strip ASIC: PASTA

PASTA is the 64 channel front-end chip, designed in a 110 nm CMOS technology to read out the strip sensors of the Micro Vertex Detector (MVD) of the PANDA experiment. This chip provides high resolution timestamp and deposited charge information by means of the time-over-threshold technique. Its working principle is based on a predecessor, the TOFPET ASIC, that was designed for medical applications. A general restructuring of the architecture was needed, in order to meet the specific requirements imposed by the physics programme of PANDA, especially in terms of radiation tolerance, spatial constraints, and readout in absence of a first level hardware trigger. The first revision of PASTA is currently under evaluation at the Forschungszentrum Jülich, where a data acquisition system dedicated to the MVD prototypes has been developed. This paper describes the main aspect of the chip design, gives an overview of the data acquisition system used for the verification, and shows the first results regarding the performance of PASTA.

First results of the front-end ASIC for the strip detector of the PANDA MVD

PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. PASTA (PAnda STrip ASIC) is the readout chip for the strip part of the MVD. The chip is designed to provide high resolution timestamp and charge information with the Time over Threshold (ToT) technique. Its architecture is based on Time to Digital Converters with analog interpolators, with a time bin width of 50 ps. The chip implements Single Event Upset (SEU) protection techniques for its digital parts. A first full-size prototype with 64 channels was produced in a commercial 110 nm CMOS technology and the first characterizations of the prototype were performed.

Overview of the Micro Vertex Detector for the [formula omitted]ANDA experiment

The P¯ANDA experiment is devoted to study interactions between cooled antiproton beams and a fixed target (the interaction rate is of about 107 events/s), hydrogen or heavier nuclei. The innermost tracker of P¯ANDA is the Micro Vertex Detector (MVD), specially designed to ensure the secondary vertex resolution for the discrimination of short-lived charmonium states. Hybrid epitaxial silicon pixels and double-sided silicon microstrips will equip four barrels, arranged around the interaction point, and six forward disks. The experiment features a triggerless architecture with a master clock of 160MHz, therefore the MVD has to run with a continuous data transmission where the hits need precise timestamps. The energy loss of the particles in the sensor will be measured as well. The challenging request of a triggerless readout suggested to develop custom readout chips for both pixel (ToPix) and microstrip (PASTA) devices. To validate components and the triggerless readout architecture, prototypes have been built and tested. After an overview of the MVD, the technological aspects and performances of some prototypes will be reported.

Vacuum-compatible, ultra-low material budget Micro-Vertex Detector of the compressed baryonic matter experiment at FAIR

The Compressed Baryonic Matter (CBM) Experiment is one of the core experiments of the future FAIR facility near Darmstadt (Germany). The fixed-target experiment will explore the phase diagram of strongly interacting matter in the regime of high net baryon densities with numerous probes, among them open charm mesons. The Micro Vertex Detector (MVD) will provide the secondary vertex resolution of ∼50μm along the beam axis, contribute to the background rejection in dielectron spectroscopy, and to the reconstruction of weak decays. The detector comprises four stations placed at 5, 10, 15, and 20cm downstream the target and inside the target vacuum. The stations will be populated with highly granular CMOS Monolithic Active Pixel Sensors, which will feature a spatial resolution of <5μm, a non-ionizing radiation tolerance of >1013neq/cm2, an ionizing radiation tolerance of ∼3Mrad, and a readout speed of a few 10μs/frame. This work introduces the MVD-PRESTO project, which aims at integrating a precursor of the second station of the CBM-MVD meeting the following requirements: material budget of x/X0<0.5%, vacuum compatibility, double-sided sensor integration on a Thermal Pyrolytic Graphite (TPG) carrier, and heat evacuation of about 350mW/cm2/sensor with a temperature gradient of a few K/cm.

A time-based front-end ASIC for the silicon micro strip sensors of the P̄ANDA Micro Vertex Detector

The P̄ANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (P̄ANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

Prototyping the read-out chain of the CBM Microvertex Detector

The Compressed Baryonic Matter (CBM) Experiment at the future FAIR (Darmstadt/Germany) will study the phase diagram of hadronic matter in the regime of highest net-baryon densities. The fixed target experiment will explore the nuclear fireballs created in violent heavy ion reactions with a rich number of probes. To reconstruct the decay topologies of open-charm particles as well as to track low-momentum particles, an ultra-light and precise Microvertex Detector (MVD) is required. The necessary performance in terms of spatial resolution, material budget and rate capability will be reached by equipping the MVD with highly granular, radiation-hard CMOS Monolithic Active Pixel Sensors (CPS) developped at IPHC Strasbourg, which are operated in the target vacuum of the experiment. This contribution introduces the concept of the MVD and puts a focus on the latest results obtained from the R&D of the electronics and read-out chain of the device. Moreover, we briefly introduce the PRESTO project, which realises a prototype of a full size quadrant of an MVD detector station.

The STAR Heavy Flavor Tracker PXL detector readout electronics

The Heavy Flavor Tracker (HFT) is a recently installed micro-vertex detector upgrade to the STAR experiment at RHIC, consisting of three subsystems with various technologies of silicon sensors arranged in 4 concentric cylinders. The two innermost layers of the HFT close to the beam pipe, the Pixel (“PXL”) subsystem, employ CMOS Monolithic Active Pixel Sensor (MAPS) technology that integrate the sensor, front-end electronics, and zero-suppression circuitry in one silicon die. This paper presents selected characteristics of the PXL detector part of the HFT and the hardware, firmware and software associated with the readout system for this detector.

The readout chain for the P̄ANDA MVD strip detector

The P̄ANDA (antiProton ANnihilation at DArmstadt) experiment will study the strong interaction in annihilation reactions between an antiproton beam and a stationary gas jet target. The detector will comprise different sub-detectors for tracking, particle identification and calorimetry. The Micro-Vertex Detector (MVD) as the innermost part of the tracking system will allow precise tracking and detection of secondary vertices. For the readout of the double-sided silicon strip sensors a custom-made ASIC is being developed, employing the Time-over-Threshold (ToT) technique for digitization and utilize time-to-digital converters (TDC) to provide a high-precision time stamp of the hit. A custom-made Module Data Concentrator ASIC (MDC) will multiplex the data of all front-ends of one sensor towards the CERN-developed GBT chip set (GigaBit Transceiver). The MicroTCA-based MVD Multiplexer Board (MMB) at the off-detector site will receive and concentrate the data from the GBT links and transfer it to FPGA-based compute nodes for global event building.

A MAPS Based Micro-Vertex Detector for the STAR Experiment

For the 2014 heavy ion run of RHIC a new micro-vertex detector called the Heavy Flavor Tracker (HFT) was installed in the STAR experiment. The HFT consists of three detector subsystems with various silicon technologies arranged in 4 approximately concentric cylinders close to the STAR interaction point designed to improve the STAR detector's vertex resolution and extend its measurement capabilities in the heavy flavor domain. The two innermost HFT layers are placed at radii of 2.8 cm and 8 cm from the beam line. These layers are constructed with 400 high resolution sensors based on CMOS Monolithic Active Pixel Sensor (MAPS) technology arranged in 10-sensor ladders mounted on 10 thin carbon fiber sectors to cover a total silicon area of 0.16 m2. Each sensor of this PiXeL (“PXL”) sub-detector combines a pixel array of 928 rows and 960 columns with a 20.7μm pixel pitch together with front-end electronics and zero-suppression circuitry in one silicon die providing a sensitive area of ∼3.8 cm2. This sensor architecture features 185.6μs readout time and 170 mW/cm2 power dissipation. This low power dissipation allows the PXL detector to be air-cooled, and with the sensors thinned down to 50μm results in a global material budget of only 0.4% radiation length per layer. A novel mechanical approach to detector insertion allows us to effectively install and integrate the PXL sub-detector within a 12 hour period during an on-going multi-month data taking period. The detector requirements, architecture and design, as well as the performance after installation, are presented in this paper.

A data parallel digitizer for a time-based simulation of CMOS Monolithic Active Pixel Sensors with FairRoot

CMOS Monolithic Active Pixel Sensors (MAPS) demonstrated excellent performances in the field of charged particle tracking. They feature an excellent single point resolution of few μm, a light material budget of 0.05% Xo in combination with a good radiation tolerance and time resolution. This makes the sensors a valuable technology for micro vertex detectors (MVD) of various experiments in heavy ion and particle physics like STAR and CBM. State of the art MAPS are equipped with a rolling shutter readout. Therefore, the data of one individual event is typically found in more than one data train generated by the sensor. This paper presents a concept to introduce this feature in both simulation and data analysis, taking profit of the sensor topology of the MVD. This topology allows to use for massive parallel data streaming and handling strategies within the FairRoot framework.

The ψ(4040) at the future experiment

The experiment will be carried out at the future FAIR facility, it will be a fixed target experiment, where antiproton beams, of unprecedented quality and intensity, will be used to study interactions on protons and on nuclei. will be an excellent tool to investigate those final states which include short-lived particles. Since different charmonium states can be accessed in direct formation with all the available quantum numbers in p̄p annihilations, the charmonium spectroscopy is one of the main goal of the experiment.The experiment represents a unique possibility to improve both statistics and precision of existing data and to further explore the physics in the charm quark sector. Indeed, an energy scan with high precision over the full charm spectrum is still missing and it will not be delivered by future experiments currently planned as upgrade of the existing facilities. A detailed description of the possibility to reconstruct the ψ(4040) → D*+D*− at , together with the study of the huge hadronic background suppression will be presented. The importance of the Micro-Vertex Detector for the reconstruction of D mesons decay will be showed.

Readout Hardware and Firmware Architecture of the HFT PXL Detector at STAR

The “Heavy Flavor Tracker” (HFT) is an approved micro-vertex detector upgrade to the STAR experiment at RHIC, consisting of three subsystems with various technologies of silicon sensors arranged in 4 concentric cylinders, to be installed in STAR by 2014. This new vertex detector will improve the track-pointing resolution in STAR to a distance of closest approach (DCA) of ~ 30 μm in order to allow for a direct and full topological reconstruction of heavy quark meson decays and a better determination of the heavy quark meson spectra. The two innermost layers of the HFT close to the beam pipe, the Pixel (“PXL”) subsystem, employ CMOS monolithic active pixel sensor (MAPS) technology that integrates the sensor, front-end electronics, and zero-suppression circuitry in one silicon wafer. The PXL layers of the HFT will consist of 400 MAPS sensors arranged in 40 ladders (10 ladders at a radius of 2.5 cm and 30 ladders at 8 cm from the beam), each containing 10 of these sensors. This paper will present selected design characteristics of the PXL detector part of the HFT and the hardware and firmware architecture of the proposed readout system for this detector, as well as its integration into the existing STAR framework. A prototype of this readout system has recently been used at CERN to take data from a telescope consisting of 7 sensors arranged in parallel planes and shown to be fully functional.