Microprocessor Package Research Articles

Compact Thermal Model of The Microprocessor Package and Heat Transfer Path Identification for Computer Systems

Compact Thermal Model of The Microprocessor Package and Heat Transfer Path Identification for Computer Systems

A Hertzian contact based model to estimate thermal resistance of thermal interface material for high-performance microprocessors

Thermal interface material (TIM) is applied at the interface between the high-performance microprocessors and heat sink to create a robust heat transfer path. Thermally speaking, TIM is typically characterized by a TIM tester and results are reported in terms of thermal impedance with bond line thickness (BLT) and/or averaged contact pressure. However, the characterization data collected from a TIM tester often cannot represent TIM’s behavior under usage conditions for high-performance microprocessors. The primary reason being the discrepancy in the contact conditions between TIM tester and microprocessor application, mainly including warpage of the microprocessor package and heat sink. In this paper, a Hertzian contact model is proposed to bridge this gap by incorporating in-situ warpage of the microprocessor package and heat sink in usage into the consideration. By applying the model, the thermal resistance of TIM under usage conditions for high performance microprocessors can be estimated from laboratory characterization data. A validation experiment is also presented, and good correlation has been obtained between the prediction and measurement.

Impact of Mechanical Property Degradation and Intermetallic Compound Formation on Electromigration-Oriented Failure of a Flip-Chip Solder Joint

Due to the increased complexity and optimization in microprocessor packaging from 2D to 3D packages, the size of solder joints is being reduced significantly. This trend currently leads to an increased amount of current density across flip-chip solder joints as well as microbumps and causes electromigration-oriented void formation and subsequent failure of the solder joints. It has been observed from literature that solder material undergoes microstructure evolution and subsequent degradation of mechanical properties under isothermal aging conditions. The current study is based on the effects of material property degradation due to thermal aging of flip-chip Sn-Ag-Cu (SAC) solder joints on electromigration-oriented failure. Finite element analysis has been used to analyze the diffusion characteristics of a SAC solder joint under isothermal aging conditions of 100°C for a period of 1–20 days, and electromigration simulation has been performed at two different temperatures of 100°C and 125°C for 100 h at an input current range of 0.01–0.05 A. The effect of intermetallic compound (IMC) layer thickness is analyzed to reveal the impact on electromigration-oriented failure in isothermally 60 days long aged solder bumps. Results have revealed that resistance to electromigration-oriented failure is higher in the case of aged components compared to unaged components along with the increment of time to failure with IMC formation in the SAC solder joint.

Proposal of The New Compact Thermal Model Based on One-Dimensional Thermal Network for Microprocessor Packages

Proposal of The New Compact Thermal Model Based on One-Dimensional Thermal Network for Microprocessor Packages

New Compact Thermal Model Development and Temperature Prediction for Microprocessor Packages

New Compact Thermal Model Development and Temperature Prediction for Microprocessor Packages

Mechanical Reliability of Embedded Array Capacitors in Ultrahigh-Performance Microprocessors

Increasing power delivery and performance requirements for next-generation Intel microprocessors has led to the need for a high-capacitance low-inductance decoupling option very close to the die. An embedded array capacitor (EAC) is a large array capacitor embedded in the high-density interconnect (HDI) substrate core and provides a low-inductance path to the die. This paper describes technology development challenges encountered while enabling EACs on Intel's advanced microprocessors. Various package interfaces resulting from the EAC embedding showed very high stress and propensity to delaminate. These defects were addressed by tailoring suitable materials and process modifications during the manufacturing process. Expansion of the embedding material in the HDI substrate resulted in high C4 area warpage. This led to issues such as solder bump bridging, underfill voids, and reliability fails. The technology development challenges and the solution paths described in this paper are very useful to industry in understanding the integration of advanced decoupling options in ultrahigh-performance microprocessor packages.

Characterization of Compressive Die Stresses in CBGA Microprocessor Packaging Due to Component Assembly and Heat Sink Clamping

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general “rule of thumb,” approximately two-thirds (∼66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to − 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping.

A Hierarchical Simulation Flow for Return-Loss Optimization of Microprocessor Package Vertical Interconnects

Design of package- and board-level interconnects utilizing full-wave electromagnetic solvers, is becoming increasingly important owing to increased frequencies of operation, miniaturization, and reduced time to market. Thus, parameterization, optimization, and statistical analysis tools are becoming an invaluable part of a designer's armory. Leveraging a previously developed fast full-wave electromagnetic solver, this paper addresses the development of a framework for package interconnect design. Parametric sweeps are conducted to show the existence of optimal designs and to select the best routing strategies. Having applied the popular response surface methodology for optimization and having outlined its limitations for higher-dimensional problems, a general optimization scheme is proposed and illustrated on a differential package interconnect line. The proposed methodology features a dimensionality reduction scheme and a reusable, multidimensional look-up table preceding the global optimization phase, which is facilitated by a smooth interpolation scheme based on splines. The second phase features a custom local optimizer incorporating all the variables without any dimension reduction. This methodology has been applied to automated synthesis of a differential package line resulting in a significant improvement of the return loss performance. A statistical analysis methodology, based on utilizing the gradient, has been presented to arrive at the spread in the differential return loss, occurring due to manufacturing tolerances, around the designed response.

Multiband Electromagnetic-Bandgap Structures for Applications in Small Form-Factor Multichip Module Packages

The design and implementation of package-level electromagnetic-bandgap (EBG) structures is presented. By using spiral-based inductance-enhanced electromagnetic-bandgap structures (IE-EBGs), the relative periodicity for achieving bandgap at extremely low frequencies is substantially reduced in comparison to traditional EBGs. Using both full-wave electromagnetic simulation and experimental characterization, it is demonstrated that this type of structure can exhibit multiple bandgaps, which are individually tunable through variation of the inductance per unit area and/or the unit cell periodicity. Sample structures with dimensions compatible with today's microprocessor packaging technology are designed and fabricated in a multilayer organic flip-chip ball-grid array package substrate. These package-embedded IE-EBGs have unit cell dimensions less than 750 mum and exhibit the first forbidden bandgaps for electromagnetic wave propagation below 10 GHz, which is a frequency band of interest for commercial wireless communication systems.

Investigation of the Impact of Power Granularity on Chip Thermal Modeling Using White Noise Analysis

In this paper, we investigate the impact of the granularity of the power distribution for accurately predicting semiconductor chip temperature fields. Specifically, we calculate the transfer functions between power distributions and resulting temperature maps for various microprocessor packages and cooling conditions, which establish a minimum granularity required for accurate thermal analysis. The purpose of this paper is twofold: First, we like to provide some general guidelines for the impact of different power granularities on the global chip temperatures and second we intend to spike a broader discussion about to which extent small heating effects can affect chip temperatures for circuits under full operation. As such this work is not only beneficial for package and cooling solution engineering but is also important to circuit designers and computer architects in their battle against hotspots in microprocessors.

The evolution of build-up package technology and its design challenges

This paper reviews sequential build-up (SBU) laminate substrate development from its beginning in 1988 and reports on developments in this technology for IBM applications since its adoption in 2000. These laminated substrates are nonuniform structures composed of three elements: a core, build-up layers, and finishing layers. Each element has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology very suitable for high-performance designs. This paper focuses on the challenges encountered by IBM during the design, manufacture, and reliability testing phases of development of SBU substrates as solutions for application-specific integrated circuit (ASIC) and microprocessor packaging applications.

Multi-Physics Simulation of a Microprocessor Package Under Water Cooling

Simulation tools today are well developed and make it possible to study more than one physical phenomena in the engineering processes. In this paper, a multi-physics simulation was performed to investigate the thermal, hydraulic and stress behavior of a flip-chip microprocessor package and a water-cooling thermal system. The distribution of the temperature, velocity, pressures, and stress inside the integrated circuit (IC) package and the water jacket was predicted and analyzed. The thermal resistance, Rjw, was defined and calculated to evaluate the overall thermal performance. The difference between the numerically predicted Rjw and the experimental result is within 10%. Thermal and hydraulic parametric studies were performed on the parameters such as the water flow rate, the die size, the channel height, and the base thickness of the water jacket. The impact of heater was also investigated to optimize the heater efficiency under different thermal contact between the IC package and the thermal head. Stress simulation was performed on the heater plate and the IC package subject to the temperature profile. The thermal stress and deformation were found to be at safe level under the given conditions. The results show that the use of multi-physics simulation and analysis can provide a deeper insight of complex processes, as well as to investigate the key parameters for system optimization. The numerical approach can reduce the risk and uncertainties at design stage as well as improve the system performance at the production stage.

Critical Aspects of High-Performance Microprocessor Packaging

AbstractHistorically, the primary function of microprocessor packaging has been to facilitate electrical connectivity of the complex and intricate silicon microprocessor chips to the printed circuit board while providing protection to the chips from the external environment. However, as microprocessor performance continues to follow Moore's law, the package has evolved from a simple protective enclosure to a key enabler of performance. The art and science of semiconductor packaging has advanced radically over the past few decades as faster and more powerful microprocessors with tens of millions of transistors continue to be available, which require more signal and power input/output connections as well as greater power-dissipation capabilities. Key drivers for the development of packaging technologies include power delivery, thermal management, and interconnect scaling, in which the space transformation from fine-featured silicon interconnects to the relatively coarse features seen on motherboards has to be enabled by the package. These drivers, under constant market-driven cost pressure, have led to increased demands on new materials and new package architectures to enable silicon performance. Significant advances have already been made in the areas of heat dissipation, power delivery, high-speed signaling, and high-density interconnects. It is expected that the future evolution of microprocessors will be increasingly challenging in these areas. This article focuses on providing a broad perspective view of the evolution of microprocessor packaging and discusses future challenges.

Design and performance evaluation of microprocessor packaging capacitors using integrated capacitor-via-plane model

As clock speeds increase into the gigahertz regime and rise times decrease into the picosecond regime, the interaction between capacitors and power/ground planes of a package, interposer, or board on which they are mounted becomes vitally important to the performance of a power delivery system. To include the interaction, this paper provides an integrated model for a discrete capacitor mounted on pads over vias connected to power/ground planes with degassing holes. The mutual inductance between capacitor pads, vias, and power/ground planes are completely modeled. Through optimized via and capacitor pads placement designs, our modeling results show that the mutual inductance drastically changes the total loop inductance as compared to the self-inductance of the capacitor. To validate the integrated modeling method, a test package is built. A measurement technique is introduced to evaluate the total loop inductance of the test package with various capacitor form factors and types. The predicted results match well with the measured data. This paper discusses further the usage of the three-dimensional (3-D) integrated model for actual implementation of decoupling capacitors on packages in order to ensure the effectiveness of the capacitors. The first decoupling capacitor placement design on package that we will discuss is the Plastic Pin Grid Array (PPGA) package for Intel's CPU. Through the three-dimensional (3-D) integrated modeling, the inductance value of the power delivery system with and without capacitors are extracted. It was found that due to the pin-out constraint of CPU PPGA products, as well as unfavorable PPGA package design rules, decoupling capacitors placed in PPGA packages are not effective due to high loop inductance. The second package that we will discuss is the Flip Chip Pin Grid Array (FC-PGA) package, which is for Intel's future CPU packaging. It is found that the decoupling capacitor placement on the FC-PGA highly improves the performance of the power delivery system. For the same amount of cost, the total loop inductance for FCPGA package decoupling capacitors is found to be 1/9th the total loop inductance for the PPGA package.

MicroStandards - P961 working group formed

In response to a project authorization request submitted by the Microprocessor Standards Committee, the IEEE Standards Board has authorized a project (P961) to study the need for a microprocessor bus standard based on the STD bus. The STD bus is an eight-bit microprocessor busing and packaging scheme currently supported by over 40 card manufacturers. It makes use of a preassigned 56-pin bus connector on a 4.5-inch (l14.3-mm) by 6.5-inch (l65.1-mm) card. The small card is intended to support a modular-by-function approach to designing with microprocessors. The P961 working group is being formed to assemble the first draft standard. A specification managed and maintained by the STD Manufacturers Group is being considered as the core document. This specification, which defines the physical and logical req uirements, will be combined with basic memory and I/O timing as a basis for the first draft.

A microprocessor environmental controller for quadriplegics

An environmental controller has been designed using consumer available components. Its flexibility, versatility, and reduced cost, are a direct result of using an isometric joystick, a microprocessor and software package in a configuration that lends itself very readily to change.