Micron Pitch Research Articles

Assembly of Large Flip Chip Die in Ceramic Packages

Hermetic packaging is required to ensure the reliability of processors and application specific integrated circuit (ASIC) chips that are used in strategic systems, whose operating lifetimes typically exceed thirty years. Performance requirements for emerging system applications are dictating the need for one thousand or more I/O, which precludes the use of wire bonded devices. These packaging requirements can be met by flip chip bonding die onto multilayer, high temperature cofired ceramic substrates. The hermetic environment is provided by a Kovar metal ring that is brazed onto the ceramic and sealed in the final assembly step, by welding on a metal cover. Several process and design requirements must be met to achieve high reliability flip chip assemblies. Reflowed devices must be free of flux residues because they are corrosive, provide a path for ion diffusion, are a source of moisture and degrade the adhesion of underfill to chip and substrate. Removal of flux residues by cleaning is problematic because the gap between chip and substrate is very small relative to chip area. A better approach is to bond chips without flux, as we do, by reflowing them in a formic acid environment. An important reliability requirement for strategic hardware is the ability to sustain many cycles over extended temperature ranges. Temperature cycles induce plastic deformation in the solder connections as a result of stresses generated by the mismatch in thermal expansion coefficients of the chip and package. These stresses can be reduced significantly by underfilling the bonded chip with a filled adhesive. Choice of material as well as process execution impact the effectiveness of underfill enhancement of reliability. Optimization of both the physical design and composition of the solder connections is essential to producing reliable flip chip assemblies. We make extensive use of finite element analyses (FEA) in which we track the accumulation of plastic strain energy in the solder connections as they are subjected to temperature cycle induced stresses. Good correlations between the energy accumulated per cycle and the number of cycles to failure can be achieved if accurate state models of the solder are used. We have a catalog of Anand models for the solder compositions that we use in our FEA simulations. One of the more challenging aspects of designing high performance flip chip packages is matching the size and pitch of the bond pads on the ceramic with those on the chip. Current devices use 90 micron diameter pads on 200 micron pitch, but newer designs are migrating towards 80 micron diameter pads on 180 micron pitch. It challenging to maintain tight tolerances on pad geometries in these higher density packages and to route all the additional signals. Thermal management is also an important component of the package design. Thermal vias and thermally conductive underfills are used to remove heat from the front side of the chip. On the backside of the chip, the gap between chip and cover is minimized and filled with a high thermal conductivity interface material. High fidelity FEA modeling is necessary to ensure that the chip can be adequately cooled in its hermetic environment. This paper discusses the impact of these design and assembly factors on the reliability of high performance, hermetically packaged flip chip assemblies.

(Invited) Bottom-up Gold Filling for Manufacture of X-Ray Gratings: Mechanism and Implications

Over the past four years a process for extreme superconformal deposition of gold has been demonstrated and explored for void-free filling of recessed features on patterned substrates for application in X-ray imaging. Uniform and complete void-free filling was detailed on 100 mm silicon wafers patterned with micrometer pitch vias of aspect ratio (height/diameter) 23 and trenches of aspect ratio (height/width) exceeding 60 as well as trenches more than 300 μm deep and fractal patterns of spatially varying depth. This talk discusses a proposed mechanism and model for the observed behavior. Simulations capture key features of the experimental processes, including not only the bottom-up filling itself but also an extended incubation period of conformal deposition that precedes its start as well as self-passivation of the active deposition that accompanies the completion of filling. Feature filling results with relevant electrochemistry are discussed in the context of predicted behavior for different deposition conditions. Cross-sectioned 60 μm deep trenches Au filled at fixed potentials, the associated current transients, a Au filled grating and a simulation of filling in 50 μm deep trenches are all shown in the figure. Figure 1

Toward 100,000-Pixel Microcalorimeter Arrays Using Multi-absorber Transition-Edge Sensors

We report on the development of multi-absorber transition edge sensors (TESs), referred to as hydras. A hydra consists of multiple x-ray absorbers each with a different thermal conductance to a TES. Position information is encoded in the pulse shape. With some trade-off in performance, hydras enable very large format arrays without the prohibitive increase in bias and read-out components associated with arrays of individual TESs. Hydras are under development for the next generation of space telescope such as Lynx. Lynx is a NASA concept under study that will combine a < 1 arcsecond angular resolution optic with 100,000-pixel microcalorimeter array with energy resolution of deltaE_FWHM ~ 3 eV in the soft x-ray energy range. We present first results from hydras with 25-pixels for Lynx. Designs with absorbers on a 25 micron and 50 micron pitch are studied. Arrays incorporate, for the first time, microstrip buried wiring layers of suitable pitch and density required to readout a full-scale Lynx array. The resolution from the coadded energy histogram including all 25-pixels was deltaE_FWHM = 1.66+/-0.02 eV and 3.34+/-0.06 eV at an energy of 1.5 keV for the 25 micron and 50 micron absorber designs respectively. Position discrimination is demonstrated from parameterization of the rise-time.

Relative positioning method for near-field beam spot array with optical microscope image of lithographic patterns using linear regression

A method for simply analyzing the relation between spot positions of near-field beam sources with micrometer pitch is proposed using an optical microscope. Based on the locations of spots in an optical microscopy image of lithographic patterns, the effective relative position is derived using simple linear regression. Numerical analysis is performed to introduce the concept and to evaluate the methodology with random noise. The accuracy and uncertainty of the proposed method are discussed. To confirm the method’s feasibility, the experiments are conducted using fabricated probe array, and the experimental and numerical results are compared on the basis of uncertainty. An arbitrary pattern is recorded with respect to relative coordinates obtained based on the effective positions. We suggest a simple strategy for controlling beam spot array locations for pattern design in near-field lithography with less than 5-nm uncertainty.

3D High Density: technology, roadmap and applications

After many years of packaging evolution as main industrial driver for 3D integration, even denser integration scheme have gained recently more interest. Slowdown of Moore's law while maintaining the need of high performance and/or low power from one hand, and a combination of performance / form factor from the other, lead research to innovation and alternative solutions. Additionally, difficulty of associating in a same 2D wafer heterogeneous processes (ie: combining Cmos device with “exotic” material, with low temperature dielectric) also gives an opportunity for a high density 3D approach rather than a 2D one. As an example, back-side illuminated imagers (BSI Imagers) players have recently released such 3D density (pitch in the range of 5 to 10 micron) [1] � From now, thinking about a 3D industrial integration within the range of few microns pitch is not anymore a dream. This specific application may raise some interest for other products such as memory denser stacking, partitioning of a large SoC � The objective of the paper is to describe 2 complementary technologies developed at CEA-Leti which address such high density of 3D integration: Hybrid Bonding in the range of few �ms; Coolcube in the range of few 100e of nms. We will first take some time to describe both technologies and recent CEA-Leti's results. The positioning of each technologies in terms of pitch and performance will be given. 1 - 3D parallel integration: hybrid bonding Hybrid bonding integration scheme has been first developed on a wafer scale approach. A test vehicle, with several BEOL layers and connected by the implementation of hybrid bonding, has been designed. Morphological and electrical data will be given leading to the conclusion that the process is very reliable and robust [1], [2]. Contact resistance per contact pads has been measured at few mOhms, which is relatively low compared to tens or even hundreds of mOhms for more classical interconnection technologies (copper pillar, bump, Cu-Cu thermos-compression). Nevertheless, for cost reason, as well as for multi dies stacking, the need for Die-To-Wafer approach remains true, while keeping a high density of interconnect [3]. The process flow as well as test vehicle designed for this approach will be described. Major challenges including handling of the dies after sawing and till the bonding itself will be addressed in the paper: wafer handler, wafer preparation and pick &amp; place. Deep characterization is proposed. 2 - 3D sequential integration: CoolCube An alternative approach to conventional planar integration for future nodes is the monolithic 3D integration (3DVLSI). Monolithic offers the possibility to stack devices with a lithographic alignment precision enabling 3D contacts introduction at the device level (up to 100 million vias per mm� with 14nm ground rules). 3DVLSI can by routed either at gate or transistor levels. The partitioning at the gate level allows IC performance gain without resorting to scaling thanks to wire length reduction. Partitioning at the transistor level by stacking n-FET over p-FET (or the opposite) enables the independent optimization of both types of transistors (customized implementation of performance boosters: channel material / substrate orientation / channel and Raised Sources and Drains strain, etc. [4–5]) with reduced process complexity compared to a planar co-integration. The ultimate example of high performance CMOS at low process cost is the stacking of III–V nFETs above SiGe pFETs [6–7]. These high mobility transistors are well suited for 3DVLSI because their process temperatures are intrinsically low. 3DVLSI, with its high contact density, can also be seen as a powerful solution for heterogeneous co-integrations requiring high 3D vias densities such as NEMS with CMOS for gas sensing applications [8–9] or highly miniaturized imagers [10]. 3- Comparison and roadmap This paper will also provide features that give some applications' meaning for the development of both technologies in parallel. Particularly, both technologies will be compared in terms of possible pitch reachable. Main comparison features rely on advanced interconnection: dimension &amp; pitch resistance, parasite. A thermal simulation comparison study will also be included.

Performance of the INTPIX6 SOI pixel detector

Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e−. The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e−. The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

Compressive spectral testbed imaging system based on thin-film color-patterned filter arrays.

Compressive spectral imaging systems can reliably capture multispectral data using far fewer measurements than traditional scanning techniques. In this paper, a thin-film patterned filter array-based compressive spectral imager is demonstrated, including its optical design and implementation. The use of a patterned filter array entails a single-step three-dimensional spatial-spectral coding on the input data cube, which provides higher flexibility on the selection of voxels being multiplexed on the sensor. The patterned filter array is designed and fabricated with micrometer pitch size thin films, referred to as pixelated filters, with three different wavelengths. The performance of the system is evaluated in terms of references measured by a commercially available spectrometer and the visual quality of the reconstructed images. Different distributions of the pixelated filters, including random and optimized structures, are explored.

Design, fabrication and testing of surface micromachined CMUTs for surface and interface waves

Interdigital CMUTs weredesigned and fabricated in transmit/receive pairs. Each transmitter or receiverhas 20 double-phase finger pairs with 146 micrometer pitch and 3 millimeter aperture.The wave transmission distance between the receiver and transmitter is 9millimeters. Devices were fabricated on the highly doped silicon wafers by thesurface micromachining technology using silicon nitride as the structuralmaterial and chromium as the sacrificial material. Interface (Scholte type)waves were transmitted and received at 100 V bias and 10 V pp 10 MHz 20 periodharmonic burst excitation. The wave propagation velocity in water andisopropanol were measured by the time-of-flight and spectral analysis methods.The last gave 1376 m/s and 1157 m/s phase velocity of the Scholte waves for water andisopropanol, correspondingly. At the same time, CMUT structural resonance inimmersion was 8.9 MHz for water and 9.3 MHz for isopropanol. This led to theconclusion about better informativity of the Scholte type waves. DOI: http://dx.doi.org/10.5755/j01.eie.22.5.7123

Quantum electromechanics on silicon nitride nanomembranes.

Radiation pressure has recently been used to effectively couple the quantum motion of mechanical elements to the fields of optical or microwave light. Integration of all three degrees of freedom—mechanical, optical and microwave—would enable a quantum interconnect between microwave and optical quantum systems. We present a platform based on silicon nitride nanomembranes for integrating superconducting microwave circuits with planar acoustic and optical devices such as phononic and photonic crystals. Using planar capacitors with vacuum gaps of 60 nm and spiral inductor coils of micron pitch we realize microwave resonant circuits with large electromechanical coupling to planar acoustic structures of nanoscale dimensions and femtoFarad motional capacitance. Using this enhanced coupling, we demonstrate microwave backaction cooling of the 4.48 MHz mechanical resonance of a nanobeam to an occupancy as low as 0.32. These results indicate the viability of silicon nitride nanomembranes as an all-in-one substrate for quantum electro-opto-mechanical experiments.

A Study of a Mini-Drift GEM Tracking Detector

A GEM tracking detector with an extended drift region has been studied as part of an effort to develop new tracking detectors for future experiments at RHIC and for the Electron Ion Collider that is being planned for BNL or JLAB. The detector consists of a triple GEM stack with a small drift region that was operated in a mini TPC type configuration. Both the position and arrival time of the charge deposited in the drift region were measured on the readout plane which allowed the reconstruction of a short vector for the track traversing the chamber. The resulting position and angle information from the vector could then be used to improve the position resolution of the detector for larger angle tracks, which deteriorates rapidly with increasing angle for conventional GEM tracking detectors using only charge centroid information. Two types of readout planes were studied. One was a COMPASS style readout plane with 400 micron pitch XY strips and the other consisted of 2x10mm2 chevron pads. The detector was studied in test beams at Fermilab and CERN, along with additional measurements in the lab, in order to determine its position and angular resolution for incident track angles up to 45 degrees. Several algorithms were studied for reconstructing the vector using the position and timing information in order to optimize the position and angular resolution of the detector for the different readout planes. Applications for large angle tracking detectors at RHIC and EIC are also discussed.

See-through integral imaging display using a resolution and fill factor-enhanced lens-array holographic optical element.

We report on the development of a high-resolution see-through integral imaging system with a resolution and fill factor-enhanced lens-array holographic optical element (HOE). We propose a procedure for fabricating of a lens pitch controllable lens-array HOE. By controlling the recording plane and performing repetitive recordings process, the lens pitch of the lens-array HOE could be substantially reduced, with a high fill factor and the same numerical aperture compared to the reference lens-array. We demonstrated the feasibility by fabricating a lens-array HOE with a 500 micrometer pitch. Since the pixel pitch of the projected image can be easily controlled in projection type integral imaging, the small lens pitch enhances the quality of the displayed 3D image very effectively. The enhancement of visibility of the 3D images is verified in experimental results.

The visible and near infrared module of EChO

The Visible and Near Infrared (VNIR) is one of the modules of EChO, the Exoplanets Characterization Observatory proposed to ESA for an M-class mission. EChO is aimed to observe planets while transiting by their suns. Then the instrument had to be designed to assure a high efficiency over the whole spectral range. In fact, it has to be able to observe stars with an apparent magnitude Mv= 9-12 and to see contrasts of the order of 10-4 - 10-5 necessary to reveal the characteristics of the atmospheres of the exoplanets under investigation. VNIR is a spectrometer in a cross-dispersed configuration, covering the 0.4-2.5 micron spectral range with a resolving power of about 330 and a field of view of 2 arcsec. It is functionally split into two channels respectively working in the 0.4-1 and 1.0-2.5 micron spectral ranges. Such a solution is imposed by the fact the light at short wavelengths has to be shared with the EChO Fine Guiding System (FGS) devoted to the pointing of the stars under observation. The spectrometer makes use of a HgCdTe detector of 512 by 512 pixels, 18 micron pitch and working at a temperature of 45K as the entire VNIR optical bench. The instrument has been interfaced to the telescope optics by two optical fibers, one per channel, to assure an easier coupling and an easier colocation of the instrument inside the EChO optical bench.

Fabrication and Characterization of Cu-Plated Fine Pitch Patterns on Flexible Polyimide

The thin flexible Polyimides (PI) films have desirable properties for use in the electrical and electronics industry because their good thermal stability, high flexibility, low dielectric constants, excellent mechanical strength, low loss tangent, low relative permittivity and electrical insulating properties. In order to determine the process window of the surface metallization of PI, the fine traces with 50 micron pitch (25micron line /space) built on a flexible 50 micron thick PI film using wet fabrication process are reported in this paper. The thick copper (Cu) film was obtained from the Cu plating process using evaporated thin film of Cu as the adhesion layer. The fabricated fanout fine patterns are further investigated using scanning electron microscope (SEM), energy-dispersive spectrometry (EDS) and X-ray spectrometry technologies. The experiment is conducted to study the effect of the process parameters on the Cu film surface properties. The results obtained in this work can be applied to the fabrication of flexible microelectronic devices.

Substrateless micrometric metal mesh for mid-infrared plasmonic sensors

We report on the fabrication and optical properties of thin metal films periodically patterned with square hole arrays of 2 micron pitch, which behave as substrateless plasmonic devices at mid-infrared frequencies. Large (3×3 mm2) meshes were fabricated by metallizing a patterned silicon nitride membrane. The mid-infrared spectra display resonant absorption lines with a Q-factor up to 22 in both transmission and reflection, due to the interaction of the radiation with surface plasmon modes on both faces of the film, allowed by substrate removal. The devices can be used to fabricate surface plasmon-based chemical sensors employing mid-infrared radiation.

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.

Maskless Fabrication for Micropad Interconnection using Electroless NiB Deposition and Application to "Chemical" Flip-Chip Bonding

Deposition behavior of localized electroless NiB deposition for pad-to-pad connection was investigated. Localized deposition occurred mainly on the area between facing pads, and anisotropic deposition toward each facing pad was obtained. Thus, this connection, "preferential bridge connection", is no need of photolithographic technique. These results indicated that this process is one of the maskless fabrication processes. Moreover, chemical flip-chip bonding containing preferential bridge interconnection was demonstrated. The chip-to-substrate interconnection with 30 micrometer pitch was successfully achieved.

Textured substrate based organic solar cell for higher absorption and improved performance

AbstractThe performance of polymer-based photovoltaic devices is limited by several factors like high band-gap and low charge-carrier mobility, to name a few. Thicker active-layers have high optical absorption but the transport of carriers in them is inefficient. Thus the optimal thickness of the active-layers has to be determined carefully. This conflict can be resolved using a three-dimensional (3D) microscale textured grating shaped solar cell geometry. The solar cells in this study were fabricated on photoresist gratings to give them 3D texture required for enhanced light absorption. Introduction of texturing has a significant effect on over all power conversion efficiency of the devices. Grating based solar cell having 2 micron pitch showed improved power conversion efficiency over the flat solar cell. In addition to favorable guiding of optical modes, the improvement in efficiency is accomplished by homogenous coverage of the spin-coated active layer, which is a challenging process for non-flat surfaces. Uniform thickness in this study was facilitated by the sufficiently high pitch and low height of the underlying photoresist gratings.

High Performance and Subambient Silicon Microchannel Cooling

Abstract High performance single-phase Si microchannel coolers have been designed and characterized in single chip modules in a laboratory environment using either water at 22°C or a fluorinated fluid at temperatures between 20 and −40°C as the coolant. Compared to our previous work, key performance improvements were achieved through reduced channel pitch (from 75 to 60 microns), thinned channel bases (from 425 to 200 microns of Si), improved thermal interface materials, and a thinned thermal test chip (from 725 to 400 microns of Si). With multiple heat exchanger zones and 60 micron pitch microchannels with a water flow rate of 1.25lpm, an average unit thermal resistance of 15.9Cmm2∕W between the chip surface and the inlet cooling water was demonstrated for a Si microchannel cooler attached to a chip with Ag epoxy. Replacing the Ag epoxy layer with an In solder layer reduced the unit thermal resistance to 12.0Cmm2∕W. Using a fluorinated fluid with an inlet temperature of −30°C and 60 micron pitch microchannels with an Ag epoxy thermal interface layer, the average unit thermal resistance was 25.6Cmm2∕W. This fell to 22.6Cmm2∕W with an In thermal interface layer. Cooling &amp;gt;500W∕cm2 was demonstrated with water. Using a fluorinated fluid with an inlet temperature of −30°C, a chip with a power density of 270W∕cm2 was cooled to an average chip surface temperature of 35°C. Results using both water and a fluorinated fluid are presented for a range of Si microchannel designs with a channel pitch from 60 to 100 microns.

Beaming effect of optical near-field in multiple metallic slits with nanometric linewidth and micrometer pitch

The beaming effect and interference patterns on the exit surface of multiple nano metallic slits with micrometer pitch were observed by scanning near-field optical microscopy. The near-field light intensity for multiple slits had a longer propagation tail and a smaller diverging angle as compared to that in a single slit. From finite-difference time-domain calculations, we verify that these fringe patterns come from the interference effect of longitudinal electric field, which is propagating along the surface. The beaming light in the slit openings is also attributed to the addition of longitudinal fields.

Comparison between a position sensitive germanium detector and a taper optics CCD “FRELON” camera for diffraction enhanced imaging

Diffraction Enhanced Imaging (DEI) can significantly improve the expressiveness of radiology. The contrast mechanism of DEI, in addition to absorption contrast, exploits the differences in X-ray refraction properties, which are sensed by a perfect crystal placed between the sample and the detector. DEI needs a monochromatic collimated X-ray source, which is available for instance from synchrotrons. The X-ray beam is laminar and the sample is vertically scanned for projection imaging or is rotated for CT. Detectors should match the beam characteristics and should also accomplish the other two main requirements for DEI mammography: high spatial resolution and high Detective Quantum Efficiency (DQE) in a large energy range (20–60 keV). The first permit to exploit the edge contrast enhancement obtained with the DEI technique, for example the improved visualization of microcalcifications in mammographic imaging. The second allows minimizing the dose needed for a radiograph without sacrificing spatial resolution. Apart from this, a dynamic range as good as possible is required (typically from 14 to 16 bits) as well as a high readout speed, which is particularly important for CT. These specifications are difficult to be all condensed in a single detector. At the medical beamline of the ESRF two devices have been utilized for DEI radiography: a linear germanium detector (432 pixels, 350 microns pitch), which had been developed for angiography and cerebral CT and a 2048×2048 CCD camera with taper optics which has been built at the ESRF. The first detector shows an excellent DQE at zero frequency in a large energy range (∼90% from 20 keV up to 50 keV) but limited spatial resolution. In the latter a better compromise for DEI in the 20–30 keV range has been realized: a pixel size of 47 μm and a DQE(0) from 0.5 to 0.6 has been achieved. The performances of the two detectors will be presented here in detail and discussed.