Microelectronic Interconnects Research Articles

<i>In Situ</i> Soldering Process Technique by Synchrotron X-Ray Imaging

This paper demonstrates the development of an experimental technique of in-situ observation for soldering of Sn-0.7wt%Cu lead-free solder on a Cu substrate which was achieved for the first time by synchrotron X-ray imaging. Reactions between liquid solder and Cu substrate during a soldering process were able to be recorded in real-time. Individual stages of the soldering process consisted of flux activation in removal of Cu oxide, solder melting and contact with the Cu substrate (wetting) and intermetallic compound (IMC) and void formation between the solder and Cu substrate. The technique development which includes experimental setup with calculated optimum beam energy in the range of 20 – 30 keV appears to result in a clear observation of real-time X-ray imaging of the soldering process. This technique provides a key method to understand the mechanism of formation of micro-electronic inter-connects for future electronic packaging applications.

Effect of Grain Boundary Misorientation on Electromigration in Lead-Free Solder Joints

Reduction in microelectronic interconnect size gives rise to solder bumps consisting of few grains, approaching a single- or bicrystal grain morphology in C4 bumps. Single grain anisotropy, individual grain orientation, presence of easy diffusion paths along grain boundaries, and the increased current density in these small solder bumps aggravate electromigration. This reduces the reliability of the entire microelectronic system. This paper focuses on electromigration behavior in Pb-free solder, specifically the Sn-0.7 wt.%Cu alloy. We discuss the effects of texture, grain orientation, and grain boundary misorientation angle on electromigration (EM) and intermetallic compound formation in EM-tested C4 bumps. The detailed electron backscatter diffraction (EBSD) analysis used in this study reveals the greater influence of grain boundary misorientation on solder bump electromigration compared with the effect associated with individual grain orientation.

ToF‐SIMS spectra multivariate analyses for the chemical characterization of microelectronic low‐k materials

Ultra‐low‐k thin films are largely used as a dielectric in microelectronic interconnections; the most advanced ones are based on a porous organosilicate SiOCH skeleton where the porosity is obtained by removing a sacrificial porogen. During integrated circuits fabrication, low‐k materials are exposed to various processes (e.g. lithography, etching, and cleaning), which modify the physical and chemical properties of these layers. A depth‐resolved chemical characterization is therefore required to understand these changes and improve the fabrication process. In this work, an industrial porous low‐k material, exposed to typical integration processes (specifically plasma etching, wet cleaning, and surface restoration) is studied. Results show that the treatments made on the samples produce small changes in the data collected by time‐of‐flight secondary ion mass spectrometry. These slight modifications have been interpreted and de‐convoluted using principal component analysis. Principal component analysis was applied to a large set of ions from mass spectra relative to a specific depth zone, i.e. the top surface, in order to characterize the near‐surface composition changing between the samples. This investigation led us to find a reduced set of ions discriminating the slight chemical differences between samples. Copyright © 2014 John Wiley & Sons, Ltd.

Modelization of structural changes in ultra low k materials during ultraviolet cure

As of 45 nm node, ultralow k (ULK) materials (εr < 2.55) are widely used in microelectronic interconnects to reduce signal propagation delay. In order to get such low dielectric constant, most of these ULK are obtained using subtractive method: after co-deposition of matrix and porogen a UV cure process is used to remove labile species (porogen). During this process, porosity is created and films are densified as shrinkage increases. This paper presents an in-depth study of the UV cure process. Two kinetic models are presented to describe shrinkage rate: the nth order and the autocatalytic model. These models also used to describe photo-polymerization shrinkage-strain of dental composite, gives predictions that are in good agreement with experimental data. We find that nth-order model is best suited to describe ULK transformations during UV cure process. CHx bonds loss and carbon content can also be modeled using same kinetic model. In order to be able to build the model, initial SiOCH-CxHy film has to be over-cured to determine the maximum conversion that film can reach when submitted to extra-long cure times. Results show that such SiOCH materials have to be cured more than 250 times their nominal cure time to reach maximum shrinkage (∼50%) and a complete loss of carbon, making them looking like SiO2. When structural changes are observed at different temperature, activation energy of reactions can be determined. In this way, shrinkage reaction has an activation energy close to 1000–1100 kJ/mol and CHx bonds or carbon loss reactions have activation energy in the range of 250–400 kJ/mol, which is pretty close to C-H binding energy.

Laser printing of conformal and multi-level 3D interconnects

A crucial challenge in three-dimensional multi-chip assemblies is to establish electrical connections between discrete devices. Here, we apply laser printing of congruent voxels of silver nanopaste for the fabrication of conformal and 3D multi-level interconnects. By controlling laser fluence, various 3D electrodes including freestanding tabs and side contacts over vertical walls can be directly printed without the need for sacrificial layers, chemical etching or electroplating. The electrical characteristics of the printed interconnects are similar to those currently in use by the semiconductor industry. These results are a promising step forward in the generation of customized interconnects for 3D microelectronics.

Deposition of Cu–Mn alloy film from supercritical carbon dioxide for advanced interconnects

Cu–Mn alloy films for microelectronic interconnects were deposited by H2 reduction of bis(2,2,6,6-tetramethyl-3,5-heptanedionato)-copper(II) [Cu(tmhd)2] and bis(penta-methylcyclopentadienyl)-manganese [Mn(pmcp)2] in supercritical carbon dioxide (scCO2). 20-nm thick and continuous Cu–Mn films with a smooth surface were deposited at the temperature of 210 °C. Manganese was found to be segregated to film surface and its content on the surface increased with increasing Mn precursor concentration in scCO2. Mn addition by supercritical fluid deposition could improve surface quality of the Cu film. And electrical resistivity of the Cu–Mn films increased with the Mn contents in the film.

Compliance analysis of multi-path fan-shaped interconnects

Compliant microelectronic interconnects are potential replacements for solder balls which accommodate this differential displacement by mechanically decoupling the die from the substrate or the substrate from the board and aim to improve overall reliability and life of the microelectronic system. Multi-path, fan-shaped compliant interconnect is being pursued at Georgia Tech as an alternate die-to-substrate or substrate-to-board interconnect. This multi-path fan-shaped interconnect has arcuate structures as well as vertical posts to provide in-plane and out-of-plane compliance, respectively. In this paper, we present the compliance values for the proposed interconnects using analytical formulations and finite-element simulations and compare these values using experimental data. The analytical formulations can be used for optimization of the geometry, because we can know the contribution of the parameters to the compliant values from the potential energy terms. Finite-element simulations can take elastic–plastic into consideration, while the analytical formulation cannot. They also help to validate our results because they were developed independently. It is seen that the scaled-up polymer interconnects will have a compliance of 0.1–0.15mm/N in the out-of-plane direction and 0.05–0.15mm/N in the in-plane directions. Also, it is seen that the results from finite-element simulations using 3D solid elements as well as beam elements agree against each other, and also against analytical models and experimental measurements.

Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

This paper presents an enlarged study about the 50-% propagation-time assessment of cascaded transmission lines (TLs). First and foremost, the accurate modeling and measurement technique of signal integrity (SI) for high-rate microelectronic interconnection is recalled. This model is based on the reduced transfer function extracted from the electromagnetic (EM) behavior of the interconnect line RLCG-parameters. So, the transfer function established takes into account both the frequency dispersion effects and the different propagation modes. In addition, the transfer function includes also the load and source impedance effects. Then, the SI analysis is proposed for high-speed digital signals through the developed model. To validate the model understudy, a prototype of microstrip interconnection with w = 500 µm and length d = 33 mm was designed, simulated, fabricated and tested. Then, comparisons between the frequency and time domain results from the model and from measurements are performed. As expected, good agreement between the S-parameters form measurements and the model proposed is obtained from DC to 8 GHz. Furthermore, a de-embedding method enabling to cancel out the connectors and the probe effects are also presented. In addition, an innovative time-domain characterization is proposed in order to validate the concept with a 2.38 Gbit/s-input data signal. Afterwards, the 50-% propagation-time assessment problem is clearly exposed. Consequently an extracting theory of this propagation-time with first order RC-circuits is presented. Finally, to show the relevance of this calculation, propagation-time simulations and an application to signal integrity issues are offered.

Ultrasonic Effects in the Thermosonic Flip Chip Bonding Process

Thermosonic flip chip (TSFC) bonding is a developing area in array microelectronic interconnection technology, and ultrasonic vibration plays an important role in TSFC bonding. To understand the ultrasonic effects at the bonding interface, a lab bonder is constructed, TSFC bonding is realized, and some ultrasonic effects (plastic deformation of the bumps on the bond pads, atom diffusion, and increased dislocation density) are observed. A dynamic finite element model of TSFC bonding is developed to analyze the stress and strain distribution at the bonding interface. The results of our study show that ultrasonic vibration causes a large cycled stress of about 288 MPa at the bonding interface, which: 1) increases dislocation density, forms dislocation nets, and provides fast diffusion channels, and 2) increases the stress gradient, provides the driver force for atom diffusion, and increases the atom diffusion flux. The large cycled stress plays a key role in forming a 25-nm diffusion layer and a good bonding strength in 100 ms at the TSFC bonding interface.

Electrophoretic Deposition of Carbon Nanotubes for Interconnections in Microelectronics

ABSTRACTCarbon nanotubes (CNTs) have been considered as a promising interconnect material to replace the solder bump used in the flip chip package because of their special electrical, mechanical and thermal properties, which may promote both the performance and reliability of the flip chip packaging. In this paper, electrophoretic deposition (EPD) of CNTs on substrates has been demonstrated for the interconnect application. EPD is a simple, low cost and high throughput process that is capable to produce densely packed film with good homogeneity at low temperature. By altering the electric fields and deposition time during the EPD process, the thickness of the CNTs film could be controlled. In this study, multi-walled carbon nanotubes (MWCNTs) were successfully coated on the various substrates using the EPD method. A highly uniform CNTs microstructure film with thickness over 5 µm was achieved. In addition, the selective depositions of CNTs on the pre-defined bond pads to form CNTs bumps were also accomplished. By employing typical flip-chip bonding technique, high density CNTs bumps were aligned to form a test chip/host substrate interconnects. The electrical conductivity of the CNTs interconnects was carried out using four-point probe measurement. Reliable electrical contacts with linear relationship in the current-voltage (I-V) characteristic suggesting ohmic behaviour were attained. The overall resistances extracted were also relatively low. These superior electrical properties have demonstrated that the CNTs bumps deposited using EPD method is a viable way to serve as an alternative to current metal solder interconnects material such as Sn-Pb alloys. Hence, it offers a promising interconnect application in the quest for device miniaturization in microelectronic industry.

Microelectronic interconnect modeling with a periodical lumped RLC-network

A modeling of high-speed microelectronic interconnections based on periodical resistor-inductor-capacitor (RLC) cells is presented in this paper. A theoretical investigation enabling one to determine the interconnect structure transfer function is established. The proposed theory is based on the use of the ABCD matrix product of elementary cells, constituting the whole interconnect structure. After extracting the constituting lumped elements R, L, and C, which model the considered interconnection, examples of the numerical validations were proposed, both in the frequency and time domains. It was demonstrated that by considering a structure comprised of 10 elementary segments in cascade, S-parameters and time-domain results were perfectly well correlated with the microstrip interconnection electromagnetic/circuit cosimulations performed with SPICE. It was verified that by considering input square wave data with several Gigasymbols/s rates, the introduced method enables the achieving of relative errors lower than 1% when the number of used cells is higher than 10. In addition, the sensitivity of the model in the function of the interconnect line length is investigated. The proposed model permits one to accurately predict the behavior of radio frequency/microelectronic interconnection responses for different signal integrity parameters of the interconnection line load values.

Corrosion of Si-O based porous low-k dielectrics

The corrosion behavior of low-k dielectric films used in today's microelectronic interconnects is reported. We study the dielectric constant, k, range 2.7 to 2.05, with all materials based on a Si-O-Si network. A corrosion mechanism based upon the reaction of water molecules with strained crack-tip bonds is used to model crack velocity vs. applied strain energy release rate curves and to extract key atomistic parameters for each dielectric. It is found that bond strength is invariant and bond density varies linearly with k. The data indicate that no new mechanism plays a part in the corrosion of these Si-O-Si based films with dielectric constants down to ∼2.

An experimental method to determine the resistance of a vertically aligned carbon nanotube forest in contact with a conductive layer

High density vertically aligned carbon nanotube (VACNT) forests are considered as a promising conductive material for many applications (interconnects in microelectronics or contact material layer in sliding contact applications). It is thus crucial to characterize the electrical resistance of these forests, especially in contact with the inherent top/bottom conductive substrates. This paper aims to develop an original method to determine the contribution of the different terms in this electrical resistance, which is measured with a tipless atomic force microscope used in high accuracy “force mode.” VACNT stacks with different heights on AlCu substrate with or without Au/Pd top coating are studied. The electrical contact area between the probe tip and the forest is considered to be equivalent to the classical electrical contact area between a tip and a rough surface. With this assumption, the scattering resistance of a mono-wall CNT is 14.6 kΩ μm−1, the top/bottom contact resistance is, respectively, 265 kΩ/385 kΩ. The bottom resistance divided in half is obtained by an interface substrate/CNT catalyst treatment. The same assumption leads to an effective compressive modulus of 175 MPa. These results are consistent with the values published by other authors. The proposed method is effective to optimise the CNT interface contact resistance before integration in a more complex functional structure.

A simple and versatile micro contact printing method for generating carbon nanotubes patterns on various substrates

We present an optimized process for generating at low cost, patterns of carbon nanotubes (CNTs) on a large variety of substrates through a simple micro contact printing method. This method meets the requirements for the integration of CNTs into microdevices, for applications in microelectronics (interconnects), flexible electronics (printed conductive electrodes) and biodevices (biosensors and biosystems for regenerative medicine). We have optimized a new method for inking PolyDiMethylSiloxane (PDMS) stamps with CNTs that turned out to improve significantly the quality of the printed features over large surfaces. This inking step is performed by adapting a spray-coating process leading to a dense and homogeneous coating of the stamp with a thin layer of CNTs. The printing step is performed using a solvent mediation, allowing us to pattern this thin layer of CNTs onto various substrates by contact through a thin film of liquid. We demonstrate that this soft and rapid methodology can lead to the realization of CNTs patterns with versatile geometries onto various substrates at the micron scale. Examples of applications for CNTs interconnects and flexible electronics are rapidly shown.

Cu Corrosion during Post-CMP Clean - Cause and Prevention

Copper dual damascene is becoming the standard process for sub-quarter micron microelectronic interconnects. Photo-induced anodic corrosion could occur on a copper p-n junction sctructure during PCMP cleaning process and the prevention of such corrosion is critical for reducing defects and improving overall yield of copper integration. The electron/hole pairs are photo-generated in the p-n junction inducing potential difference. p+ diffused region has a built-in potential of 0.2~0.5 volts against n+ diffused region. Therefore, copper oxidation and etching happen on the p-side and copper re-deposition and growth are shown on the n-side. Tafel curve measurements can be used to provide accelerated corrosion rate data at certain voltage biases that can be charateristic of copper anodic corrosion. From the PCMP cleaning chemistry perspective, increasing copper inhibitor concentration and/or decreasing copper chelator levels are found to protect copper from anodic corrosion at voltage bias. In addition, using additional additives in the PCMP process can further reduce copper anodic corrosion in a PCMP environment.

Interconnect Joule Heating under Transient Currents using the Transmission Line Matrix Method

The quality and reliability of interconnects in microelectronics is a major challenge considering the increasing level of integration and high current densities. This work studied the problem of transient Joule heating in interconnects in a two-dimensional (2D) inhomogeneous domain using the transmission line matrix (TLM) method. Computational efficiency of the TLM method and its ability to accept non-uniform 2D and 3D mesh and variable time step makes it a good candidate for multi-scale analysis of Joule heating in on-chip interconnects. The TLM method was implemented with link-resistor (LR) and link-line (LL) formulations, and the results were compared with a finite element (FE) model. The overall behavior of the TLM models were in good agreement with the FE model while, near the heat source, the transient TLM solutions developed slower than the FE solution. The steady-state results of the TLM and FE models were identical. The two TLM formulations yielded slightly different transient results, with the LL result growing slower, particularly at the source boundary and becoming unstable at short time-steps. It was concluded that the LR formulation is more accurate for transient thermal analysis.

BEHAVIORAL MODEL OF SYMMETRICAL MULTI-LEVEL T-TREE INTERCONNECTS

An accurate and behavioral modeling method of symmet- rical T-tree interconnect network is successfully investigated in this paper. The T-tree network topology understudy is consisted of ele- mentary lumped L-cells formed by series impedance and parallel ad- mittance. It is demonstrated how the input-output signal paths of this single input multiple output (SIMO) tree network can be reduced to single input single output (SISO) network composed of L-cells in cascade. The literal expressions of the currents, the input impedances and the voltage transfer function of the T-tree electrical interconnect via elementary transfer matrix products are determined. Thus, the exact expression of the multi-level behavioral T-tree transfer function is established. The routine algorithm developed was implemented in Matlab programs. As application of the developed modeling method, the analysis of T-tree topology comprised of difierent and identical RLC-cells is conducted. To demonstrate the relevance of the model established, lumped RLC T-tree networks with difierent levels for the microelectronic interconnect application are designed and simulated. The work ∞ow illustrating the guideline for the application of the rou- tine algorithm summarizing the modeling method is proposed. Then, 3D-microstrip T-tree interconnects with width 0.1m and length 3mm printed on FR4-substrate were considered. As results, a very good agreement between the results from the reduced behavioral model pro- posed and SPICE-computations is found both in frequency- and time- domains by considering arbitrary binary sequence \01001100 with 2Gsym/s rate. The model proposed in this paper presents signiflcant beneflts in terms of ∞exibility and very less computation times. It can be used during the design process of the PCB and the microelectronic circuits for the signal integrity prediction. In the continuation of this

Fast estimation of RL-loaded microelectronic interconnections delay for the signal integrity prediction

This article presents a modelling method of the signal delays induced by microelectronic interconnections regarding RL impedance load. The method proposed is based on the RLC model of the transmission lines (TL) extracted from the equivalent S parameters. Formulation for estimating the interconnection propagation delay is established according to the behaviour of the TL unit step responses. The second order model is validated with a microstrip interconnect prototype with simulations and measurements in frequency and time domains. The developed propagation delay model was validated with SPICE computations. For that, a transient simulation was performed by considering input signals corresponding to high-speed data of some Gbits/s. Then, accurate results were found for interconnections with different lengths in order of millimetre and also by varying the load values. It was shown that the computed 50% propagation delays present of relative errors about 5%. Copyright © 2011 John Wiley & Sons, Ltd.

Methods for enhanced control over the density and electrical properties of SWNT networks

The formation of manufacturable electronic materials that incorporate single-walled carbon nanotubes (SWNTs) will most likely involve the use of networks of these molecular wires, due to the enhanced current drive and reproducibility of such films. Therefore, control over the density of SWNTs during the deposition of 2-D networks is of critical importance for the development of numerous enhanced electronic materials. Room temperature deposition methods are of particular interest as they allow separation, purification, and/or chemical modification of SWNTs before deposition. This article reports three iterative liquid-deposition techniques that allow control over the properties of three distinct types of SWNT networks. First, density control was obtained for 2-D networks of unbundled, high-aspect ratio SWNTs. Such networks exhibited semiconductive behavior, with tunable on/off ratios. Second, electrically continuous 2-D clusters of high aspect ratio SWNTs were formed by allowing capillary forces to develop in a sessile suspension droplet. These constructs displayed tunable metallic conductivity, and may have the applications as interconnects in microelectronics. Finally, highly conductive, 3-D networks of bundled SWNTs were formed via an evaporation method. For these three types of networks, the density of SWNTs, and thus the macroscopic conductance, was readily controlled via the number of deposition cycles used in their formation.

Effect of Bismuth on Intermetallic Compound Growth in Lead Free Solder/Cu Microelectronic Interconnect

The intermetallic compound (IMC) growth kinetics in pure Sn/Cu and Sn10 wt%Bi/Cu solder joints was studied, respectively, after they were aged at 160–210°C for different time. It was found that the total IMC in SnlO wt%Bi/Cu joint developed faster than it did in pure Sn/Cu solder joint, when they were aged at the same temperature. And the activation energy Q a for total IMC in Sn10 wt%Bi/Cu joint was lower than that for pure Sn/Cu interconnect. The IMC growth process was discussed. The IMC Cu 6 Sn 5 was enhanced in compensation of reduced IMC Cu 3 Sn growth. The work reveals that Bi element containing in lead free solder alloys with 10 wt% can enhance IMC growth in lead free solder/Cu joint during service.