Integrated Circuit Fabrication Research Articles

Investigation of the impact of environmental conditions on the mechanical properties of thin-film copper wafers

Thin-film copper offers excellent film texture for multilevel interconnections in integrated circuit fabrication due to its superior resistance to electromigration and high electrical conductivity. To perform a chemical mechanical planarization process during semiconductor fabrication of copper, it is necessary to have a thorough understanding of the nanomechanical properties of thin-film copper. In this study, thin-film copper and reacted passivation layers on silicon substrate wafers are investigated for their nanomechanical properties under various environmental conditions. The results of this study indicate that thin-film copper passivation layers have different properties in deionized (DI) water and polishing slurry environments compared to thin-film copper exposed to ambient air. Interestingly, variations in temperature within wet environments do not significantly affect the properties of thin-film copper wafers; but changes in properties are largely driven by chemical processes. The insights gained from this study emphasize the significance of considering both the passivation layers and wet environments in semiconductor fabrication processes, which contributes to the advancement of copper-based interconnect materials and optimization of the chemical mechanical planarization process in semiconductor manufacturing.

Moore's Law Scaling and Chemical Mechanical Planarization (CMP)

Since the invention of the first integrated circuit in 1958, chemistry and materials have played a critical role in semiconductor process technologies, which has led to an exponential growth of transistors packed into circuits. Decades ago, Gordon Moore posited there would be a doubling of components every two years (revised from his original doubling every one-year prediction). This observation became known as Moore’s law.As Denard scaling took on more complexity, the number of new materials used to build semiconductors increased at a torrid pace. The number of elements in the periodic table, used to fabricate devices, increased roughly five-fold from the 1980’s to the 2000’s.In the earlier years, lithography, etch, thin films, implant, and diffusion were foundational technologies used to fabricate a silicon wafer into hundreds of microchips. In the late 1980’s a new technology Chemical Mechanical Planarization (CMP) was invented. It was developed out of necessity to reduce topography, critical for lithography’s depth of focus requirements. Without this key invention, patterning and building layer upon layer from front end transistors to back-end interconnects would not have been possible.Intel implemented CMP into manufacturing in the early 1990’s on the 0.8 micron technology node which manufactured the 486 microprocessor. CMP was required to planarize dielectric oxide used to insulate the aluminum metal interconnects. Since then, the number of CMP applications over the last three decades has exploded, enabling the scaling of Moore’s Law.CMP is not only used to improve lithography depth of focus. CMP also enables a method of metal interconnect and contact formation called damascene. Planarization is used to create dielectric isolation trenches, discrete plugs for insulation, aid advanced patterning architectures, build through silicon vias (TSVs), and enable complex wafer and chip bonding for die-to-die interconnects for disaggregated products.Transistor scaling alone is no longer sufficient to meet device performance, power, and cost requirements. Complex material and architectural changes are required. And novel CMP applications continue to be added at each new technology node. This author will make an argument that CMP is critical to push scaling and enable future process nodes. Figure 1

Ultra-low-power super class-AB adaptive biasing operational transconductance amplifier with enhanced gain for biomedical applications

The operational transconductance amplifier (OTA) proposed in this article is a bulk-driven (BD), single-stage, super-class-AB, adaptive biasing, functioning in the subthreshold region (ST) with an enormously low power supply of ± 0.25 V, providing high-gain. The input core of the OTA circuit is composed of adaptively biased BD differential input pairs based on flipped voltage follower (FVF), which drive in class-AB mode with a partial positive feedback (PPF) approach. The circuit additionally employs FVF and self-cascode (SC)-based low-power current mirror loads at its output to obtain significantly high gain and unity gain frequency. In addition, using adaptive loads based on source-degenerated metal oxide semiconductor (MOS) resistors raises dynamic current more efficiently, consequently improving the slew rate and unity gain frequency (UGF) without drawing additional power. Employing the cadence spectre tool and the UMC 0.18 μm complementary metal oxide semiconductor (CMOS) process technology, the designed OTA has been simulated. The simulation outcomes substantiate that the amplifier provides high open loop DC gain of 75 dB, 18.75 kHz UGF with a phase margin of 63.93º, and input-referred noise (IRN) of 0.734 µV/Hz0.5 at 1 kHz frequency. The proposed OTA consumes just 60.15 nW of power. The performance results confirmed that the proposed OTA circuit is appropriate in biomedical applications.

An Overview of FPGA-inspired Obfuscation Techniques

Building and maintaining a silicon foundry is a costly endeavor that requires substantial financial investment. From this scenario, the semiconductor business has largely shifted to a fabless model where the Integrated Circuit (IC) supply chain is globalized but potentially untrusted. In recent years, several hardware obfuscation techniques have emerged to thwart hardware security threats related to untrusted IC fabrication. Reconfigurable-based obfuscation schemes have shown great promise of security against state-of-the-art attacks – these are techniques that rely on the transformation of static logic configurable elements such as Look Up Tables (LUTs). This survey provides a comprehensive analysis of reconfigurable-based obfuscation techniques, evaluating their overheads and enumerating their effectiveness against all known attacks. The techniques are also classified based on different factors, including the technology used, element type, and IP type. Additionally, we present a discussion on the advantages of reconfigurable-based obfuscation techniques when compared to Logic Locking techniques and the challenges associated with evaluating these techniques on hardware, primarily due to the lack of tapeouts. The survey’s findings are essential for researchers interested in hardware obfuscation and future trends in this area.

DeepSEM-Net: Enhancing SEM defect analysis in semiconductor manufacturing with a dual-branch CNN-Transformer architecture

Due to the increasing complexity of modern semiconductor integrated circuit fabrication processes, various defects may occur at each process step, leading to a semiconductor integrated circuit yield loss as well as reliability problems. This study introduces DeepSEM-Net, a novel dual-branch architecture that harmoniously integrates Convolutional Neural Networks (CNN) with Transformers. This innovative approach significantly enhances defect classification and precise segmentation in Scanning Electron Microscope (SEM) defect images, crucial for semiconductor manufacturing processes. DeepSEM-Net consists of a classification branch, which synergizes CNN and Transformers for robust global feature extraction, and a segmentation branch, which incorporates a Pyramid Attention module to meticulously recalibrate and exploit the feature map, thereby enriching the segmentation quality. A semi-supervised defect analysis system based on this model markedly reduces manual inspection efforts and is adept at operating in both simultaneous and sequential classification-segmentation modes. Rigorously tested on a diverse dataset from a real 12-inch wafer fab, DeepSEM-Net not only demonstrated a commendable classification accuracy of 97.25% on a 5-class dataset and a segmentation IoU of 84.40% but also exhibited remarkable resilience against the introduction of new defect classes in an unbalanced dataset. The dual-branch strategy of DeepSEM-Net, thus, significantly elevates the efficiency and reliability of SEM defect image analysis, offering a substantial leap forward in addressing yield loss and ensuring the reliability of semiconductor products.

Semiconductor Process Technology and Advances in Image Sensors

The main factor in popularization of camera is that the core component, the image sensor, can be made using a semiconductor process. Since Si absorbs the entire visible light and converts the incident light to the signal electrons, image sensor could be made of the Si. So image sensors have been able to develop along with semiconductor processes. This article reviewed two types of image sensors, the structure and operating principle of pixels, pixel performance items and the relation of these items. The initial digital camera almost used a CCD sensor, but the background to why CIS is now the main focus was explained.

Low-Temperature Deposition of Diamond Films by MPCVD with Graphite Paste Additive

Modern integrated circuits (ICs) take advantage of three-dimensional (3D) nanostructures in devices and interconnects to achieve high-speed and ultra-low-power performance. The choice of electrical insulation materials with excellent dielectric strength, electrical resistivity, strong mechanical strength, and high thermal conductivity becomes critical. Diamond possesses these properties and is recently recognized as a promising dielectric material for the fabrication of advanced ICs, which are sensitive to detrimental high-temperature processes. Therefore, a high-rate low-temperature deposition technique for large-grain, high-quality diamond films of the thickness of a few tens to a few hundred nanometers is desirable. The diamond growth rate by microwave plasma chemical vapor deposition (MPCVD) decreases rapidly with lowering substrate temperature. In addition, the thermal conductivity of non-diamond carbon is much lower than that of diamond. Furthermore, a small-grain diamond film suffers from poor thermal conductivity due to frequent phonon scattering at grain boundaries. This paper reports a novel MPCVD process aiming at high growth rate, large grain size, and high sp3/sp2 ratio for diamond films deposited on silicon. Graphite paste containing nanoscale graphite and oxy-hydrocarbon binder and solvent vaporizes and mixes with gas feeds of hydrogen, methane, and carbon dioxide to form plasma. Rapid diamond growth of diamond seeds at 450 °C by the plasma results in large-grained diamond films on silicon at a high deposition rate of 200 nm/h.

Bioinspired 3D printed elastomer-hydrogel hybrid with robust interfacial bonding for flexible ionotronics

Hydrogels are widely used in flexible ionotronics due to their continuous conductive phase and good biocompatibility. However, their poor mechanical properties affect their stability and lifespan. It is a significant challenge to prepare hydrogels with both high conductivity and mechanical strength, as improving the mechanical properties often results in a tighter network, which reduces electrical conductivity. Human skin is composed of a stiff collagen fibril scaffold for resisting external damage, and a soft matrix that detect various stimuli through ion transport. Herein, inspired by the structure of human skin, a hydrogel composite with remarkable mechanical properties, high ionic conductivity, and self-healing property is prepared. The composite structure with 3D printed elastomeric skeleton and hydrogel matrix, addresses both the contradiction between the ionic conductivity and mechanical properties of hydrogels, as well as the difficulty of realizing complex macrostructures of the skeleton. The issue of weak interface in composites is resolved by creating interfacial covalent bonds. The composite’s self-healing property, combined with a robust interface, ensure the stability and longevity of the composite when used as flexible sensors. This novel approach of creating robust interface is also employed in the encapsulation of hydrogels and the fabrication of flexible microcircuits.

Physical implementation of cobalt ferrite memristor in Chua's circuit for chaotic encryption

Memory resistor, or memristor, has been realized as a discrete electronic device and has a perspective application in the field of cryptography. The physical implementation of the memristor in chaotic circuits has been scarcely explored. In this paper, a memristor is fabricated by spin-coating a cobalt ferrite precursor on a processed silicon and is then electro-sputtered with silver to act as the anode with the base silicon as the cathode. This fabrication process has a scalability potential in conjunction with integrated circuit fabrication techniques and complementary metal oxide semiconductor (CMOS) technologies. The fabricated cobalt ferrite memristor has shown a ratio between the on and off resistance of >1000 and has been implemented in a chaotic Chua's circuit, making it one of few physical implementations of a physical memristor in a physical circuit. The analysis and characterization of this circuit using bifurcation diagrams and Lyapunov exponent prove the chaotic behavior of a real Chua's circuit. This chaotic behavior can be useful in chaotic cryptography as nonperiodic oscillations can be leveraged to make sensitive information more difficult to interpret by bad actors.

Wafer Defect Identification with Optimal Hyper-Parameter Tuning of Support Vector Machine Using the Deep Feature of ResNet 101

As semiconductor processing technologies continue to advance, semiconductor wafers are becoming more densely packed and intricate, resulting in a higher incidence of surface imperfections. Therefore, it is crucial to detect these defects early and accurately classify them to pinpoint the root causes of the defects in the manufacturing process, ultimately leading to improved yield. Therefore, defect detection is critical in the industrial production of monocrystalline silicon. This study employs deep learning techniques to propose a framework for detecting defects on silicon wafers, focusing on optimizing the hyperparameters of support vector machines (SVM). Three methods were utilized to fine-tune the SVM parameters: Bayesian optimization, grid search, and random search techniques. This study demonstrates how selecting optimal values for SVM parameters can lead to better classification. Additionally, real manufacturing data were utilized to evaluate the performance of the proposed SVM classifier, with a comparison to state-of-the-art techniques in the field. By using deep features from ResNet 101 and a support vector machine, this work achieves 74.5% accuracy in identifying wafer defects without employing any optimization technique. However, the performance of the model was further improved by utilizing the random search optimization technique, which yielded the best result among the three optimization techniques tested, with an accuracy of 88.1%.

Mitigating the Effects of Design for Manufacturability on Design Iteration Cycles in Advanced Integrated Circuit Design

In integrated circuit (IC) design for advanced manufacturing processes, iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuits. Layout-dependent effects (LDEs) affect IC design and fabrication, resulting in differences in circuit functionality and performance in presimulation versus postsimulation. These differences can greatly increase the length of design iteration cycles. Foundries have attempted to accelerate the iterative design process by providing process design kit libraries to IC designers. However, these kits can neither fully mitigate the negative affect of LDEs on design for manufacturability (DFM) nor eliminate the difference between presimulation and postsimulation results. To address this problem, this study proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM parameters of all components in a circuit prior to the routing process; these parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components. Accordingly, the IC designer can determine the effects of DFM parameters on the circuit and modify them in advance if necessary. When the LDEs generated by device placement have been confirmed to not affect circuit properties, physical verification of the routing of metal wires in the IC layout can be performed. In this verification, postsimulations only need to focus on problems regarding the wire loading and timing effects of metal routing. The proposed design process is useful for mitigating LDEs in IC design and considerably reduces the time required for iterative improvement processes. Specifically, this study provides a method of enhancing design iteration cycles and provides guidelines for analyzing factors that hinder IC device functionality and performance. In sum, various problems can be resolved by separately extracting the DFM parameters associated with LDEs and parasitic parameters associated with routing.

Is SiC a Predominant Technology for Future High Power Electronics?: A Critical Review

Abstract: Due to the magnificent properties of Silicon Carbide (SiC), such as high saturation drift velocity, large operating temperature, higher cut-off and maximum frequency (fT and fmax), high thermal conductivity and large breakdown voltages (BV), it is desirable for high power electronics. With the latest advancements in semiconductor materials and processing technologies, diverse high-power applications such as inverters, power supplies, power converters and smart electric vehicles are implemented using SiC-based power devices. Especially, SiC MOSFETs are mostly used in high-power applications due totheir capability to achieve lower switching loss, higher switching speed and lower ON resistance than the Si-based (Insulated gate bipolar transistor) IGBTs. In this paper, a critical study of SiC MOSFET architectures, emerging dielectric techniques, mobility enhancement methods and irradiation effects are discussed. Moreover, the roadmap of Silicon Carbide power devices is also briefly summarized.

Raman scattering monitoring of thin film materials for atomic layer etching/deposition in the nano-semiconductor process integration

According to Moore's law, the semiconductor industry is experiencing certain challenges in terms of adapting to highly sophisticated integrated technology. Therefore, controlling materials at the atomic scale is considered a mandatory requirement for further development. To this end, atomic layer deposition and etching skills are being increasingly researched as potential solutions. However, several considerations exist for adopting atomic technology with respect to surface analysis. This review primarily focuses on the use of Raman scattering for evaluating atomic-layered materials. Raman scattering analysis is expected to gradually expand as a semiconductor process and mass-production monitoring technology. As this can enhance the applications of this method, our review can form the basis for establishing Raman scattering analysis as a new trend for atomic-scale monitoring.

Review—Post-Chemical Mechanical Planarization Cleaning Technology

Chemical mechanical planarization (CMP), a commonly employed process for attaining local and global planarization in integrated circuits fabrication, leaves contaminants and defects on the surface polished. Due to the miniaturization of devices, new materials/ processes for the fabrication of IC circuits are considered, introducing new post-CMP issues. So, understanding of post-CMP cleaning process is critical to choose an appropriate method for the given material. Thus, in this review paper, the types of contaminants and defects generated during the post-CMP process and the issues related to it are discussed. The different physical and chemical cleaning methods employed in the post-CMP cleaning process to eradicate these defects are elucidated. Especially, the PVA brushing method, which is mainly preferred currently, is elaborated on in detail. The various chemistries, including the newly suggested ones in recent years for cleaning different substrates, are summarized. The post-CMP cleaning methods for various materials such as Cu, Al, W, Co, Ru, InGaAs, Ge, and SiO2 are mainly addressed here. This review also provides the direction of progress for the post-CMP cleaning process in terms of evolution of new techniques and chemistries for the next generation of materials.

On the Application Potential of Chemically Tailored Metal Oxide and Higher Chalcogenide Nanoparticles for Nanoscale Resistive Switching Devices

Resistive switching (RS) for nonvolatile data storage is a highly relevant field of research. Up to now, RS devices are fabricated via semiconductor processing technologies. This poses the question of whether integration of chemically tailored nanoparticles, either consisting of valence change or phase change materials, can be integrated in nanoelectrode configurations in order to explore their functionality for RS applications. This review discusses the RS properties of such nanoparticles by means of selected examples of both nanoparticle assemblies as well as on the individual particle level. Although this field of research is rather unexplored, it becomes evident that chemically tailored nanoparticles bear great potential for RS applications.

Wafer Defect Identification with Optimal Hyper-Parameter Tuning of Support Vector Machine using the Deep Feature of ResNet 101

As semiconductor processing technologies continue to advance, semiconductor wafers are becoming more densely packed and intricate, resulting in a higher incidence of surface imperfections. Therefore, it is crucial to detect these defects early and accurately classify them to pinpoint the root causes of the defects in the manufacturing process, ultimately leading to improved yield. Therefore, defect detection is critical in the industrial production of monocrystalline silicon. This study employs deep learning techniques to propose a framework for detecting defects on silicon wafers, focusing on optimizing the hyperparameters of support vector machines (SVM). Three methods were utilized to fine-tune the SVM parameters: Bayesian optimization, grid search, and random search techniques. This study demonstrates how selecting optimal values for SVM parameters can lead to better classification. Additionally, real manufacturing data were utilized to evaluate the performance of the proposed SVM classifier, with a comparison to state-of-the-art techniques in the field. By using deep features from ResNet 101 and a support vector machine, this work achieves 74.5% accuracy in identifying wafer defects without employing any optimization technique. However, the performance of the model was further improved by utilizing the random search optimization technique, which yielded the best result among the three optimization techniques tested, with an accuracy of 88.1%.

Mechanical and optical properties of amorphous silicon nitride-based films prepared by electron cyclotron resonance plasma-enhanced chemical vapor deposition

Silicon nitride (SiNx) based films have been recognized as essential dielectric films in the microelectronics and optoelectronics industry due to their desirable properties, such as high electrical insulation, excellent thermal stability, and compatibility with integrated circuit fabrication processes. They are also a potential candidate for fabricating wavelength-selective reflective coatings and surface passivation layers in building-integrated photovoltaics technologies. SiNx-based films are one of the popular choices for antireflective coatings in photovoltaics as well. Recently, SiNx and oxynitride (SiOyNx) based thin film optical filters have been explored to provide distinct color rendering to solar-charged electrical vehicles. Since solar cells have a lifespan of many years and the coating surfaces are substantial, it is essential to produce films with controlled optical and mechanical properties and maintain mechanical integrity against corrosion and wear. This study aims to design a deposition process and optimize minimal parameters for stable plasma conditions during multilayer deposition of SiNx and SiOyNx films using an electron cyclotron resonance plasma-enhanced chemical vapor deposition reactor with SiH4/N2/O2/Ar precursor mixtures at 120 °C. The primary goal was to investigate the influence of gas flow adjustments on the optical and mechanical properties, specifically targeting the refractive index and mechanical properties of the films. We measured the refractive index and the absorption of the films using variable angle spectroscopic ellipsometry. Then, we evaluated the mechanical residual stress ex situ using the wafer curvature measurement method. We have determined the elastic modulus and the hardness of the films using nanoindentation. The experimental results have shown a significant dependence of the optical and mechanical properties on the deposition parameters. To investigate the factors contributing to the intrinsic mechanical stress and to better understand SiNx film degradation mechanisms, we have studied the effect of postdeposition thermal cycling on the properties of the films. Several thermal-cycling experiments from room temperature to 400 °C were performed on different SiNx films, and the results showed an irreversible variation of the mechanical stress toward the tensile stresses caused by delamination of the films, while the refractive index remained unchanged.

Detecting accurate parametric intrusions using optical fiber sensors for long-distance data communication system

The intrusion detectors and warning devices have been aided by advancements in the fields of optical fiber, integrated circuit fabrication technology, and devices. This paper describes a system of long-distance intrusion and a warning system for monitoring third-party physical intrusion in long-distance sensitive Areas. It provides around-the-clock third-party intrusion detection. The signals of the external sensors are influenced by vegetation and external natural conditions, but not in the case of optical cable sensors. A workflow algorithm has been developed in this research paper where Fast Fourier transform (FFT) is used and mathematical interpretation is made. Long-distance data communication for optical perimeter intrusion detection and warning systems is demonstrated using a block diagram. Intrusion detection system range of detection has been demonstrated pictorial also. The higher the magnitude of vibration of equipment or human being, the higher will be the range of the detection by the system. Real-Time intrusion simulation performed during the research work is depicted for a better understanding. We have conducted three simulations namely manual digging, vehicle traversing the fiber and mechanical digging which is depicted with amplitude vs. channel graph and also by waterfall display. The controller employs the distributed acoustic sensing (DAS) principle which is based on interrogating the scattering of light from nanoparticles on the optical fiber in response to changes in refractive index or molecular binding events in the surrounding environment.

Accurate Prediction and Reliable Parameter Optimization of Neural Network for Semiconductor Process Monitoring and Technology Development

Herein, novel neural network (NN) methods that improve prediction accuracy and reduce output variance of the optimized input in the gradient method for cross‐sectional data are proposed, and the variability evaluation approach of optimized inputs in the semiconductor process is suggested. Specifically, electrical parameter measurements (EPMs) and power‐delay product of industrial high‐k metal gate DRAM peripheral 29‐stage ring oscillator circuits, including NMOS, PMOS, and interconnects, are focused on. The proposed methods find an optimized input to achieve a lower NN output variance in the gradient descent than one multilayer perceptron (MLP) and mean ensemble of MLPs even when considering the variabilities of the devices and interconnects. The local optima problem of one MLP is resolved by utilizing multiple MLPs trained with different train/validation data, their trimmed mean, and an additional learnable layer. Moreover, adding the learnable layer secures versatility for various parametric datasets. The methods improve the prediction accuracy (R2) by 5.6–15.6% in sparse data space compared to one MLP and the mean ensemble, decrease the NN output variance of the optimized input by 73.0–81.6% compared to one MLP and the mean ensemble, and are successfully verified by implementing it on EPMs of 3977 test patterns of 314 wafers and 16 lots.

Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration

Owning a high-end semiconductor foundry is a luxury very few companies can afford. Thus, fabless design companies outsource integrated circuit fabrication to third parties. Within foundries, rogue elements may gain access to the customer’s layout and perform malicious acts, including the insertion of a hardware trojan (HT). Many works focus on the structure/effects of a HT, while very few have demonstrated the viability of their HTs in silicon. Even fewer disclose how HTs are inserted or the time required for this activity. Our work details, for the first time, how effortlessly a HT can be inserted into a finalized layout by presenting an insertion framework based on the engineering change order flow. For validation, we have built an ASIC prototype in 65nm CMOS technology comprising of four trojaned cryptocores. A side-channel HT is inserted in each core with the intent of leaking the cryptokey over a power channel. Moreover, we have determined that the entire attack can be mounted in a little over one hour. We also show that the attack was successful for all tested samples. Finally, our measurements demonstrate the robustness of our SCT against skews in the manufacturing process.