MicroBlaze Soft-core Processor Research Articles

FEINT: Automated Framework for Efficient INsertion of Templates/Trojans into FPGAs

Field-Programmable Gate Arrays (FPGAs) play a significant and evolving role in various industries and applications in the current technological landscape. They are widely known for their flexibility, rapid prototyping, reconfigurability, and design development features. FPGA designs are often constructed as compositions of interconnected modules that implement the various features/functionalities required in an application. This work develops a novel tool FEINT, which facilitates this module composition process and automates the design-level modifications required when introducing new modules into an existing design. The proposed methodology is architected as a “template” insertion tool that operates based on a user-provided configuration script to introduce dynamic design features as plugins at different stages of the FPGA design process to facilitate rapid prototyping, composition-based design evolution, and system customization. FEINT can be useful in applications where designers need to tailor system behavior without requiring expert FPGA programming skills or significant manual effort. For example, FEINT can help insert defensive monitoring, adversarial Trojan, and plugin-based functionality enhancement features. FEINT is scalable, future-proof, and cross-platform without a dependence on vendor-specific file formats, thus ensuring compatibility with FPGA families and tool versions and being integrable with commercial tools. To assess FEINT’s effectiveness, our tests covered the injection of various types of templates/modules into FPGA designs. For example, in the Trojan insertion context, our tests consider diverse Trojan behaviors and triggers, including key leakage and denial of service Trojans. We evaluated FEINT’s applicability to complex designs by creating an FPGA design that features a MicroBlaze soft-core processor connected to an AES-accelerator via an AXI-bus interface. FEINT can successfully and efficiently insert various templates into this design at different FPGA design stages.

RECO-ASCON: Reconfigurable ASCON hash functions for IoT applications

The need for reconfigurable lightweight cryptographic processors with low power consumption for securing the Internet of Things (IoT) with adaptive functionalities is getting attracted due to security properties, such as data fidelity, provenance, and privacy concerns. This paper presents RECO-ASCON, a reconfigurable security processor that supports both cryptographic Hash and Hasha ASCON algorithms. The proposed design is implemented in Chisel hardware construction language, an open-source hardware library. It has been evaluated in various hardware platforms such as FPGAs, embedded systems and ASICs with various technology nodes and design flows. In the PYNQ-Z1 board, RECO-ASCON can be mapped to five processors in total with a Micro-Blaze soft-core processor for streaming data to all of them while running at 200MHz without producing any timing violations. Moreover, mapping the proposed RECO-ASCON processor on the Nexsys4-DDR Xilinx Kit (ARTIX-7 chip) would cost ∼ two times fewer resources and run 1.25 × faster than the existing implementation of just one of the ASCON hash functions on the same family of the chip. We implement the proposed processor in 28 nm industry technology with commercial design flow, it achieves a maximum frequency of 1.12 GHz while achieving highest energy efficiency compared to the state-of-the-art implementations. The total area is only 9170.82um2 in 28 nm. To further evaluate the design, we also implement it with all open-source design tools and process technology libraries in 45 nm, it achieves 1 GHz maximum frequency and consumes only 18225um2 in 45 nm. Overall, the proposed reconfigurable processor is compact and more energy efficient, making it a perfect candidate to be deployed in wide range of IoT systems.

MPSoC design and implementation using Microblaze soft core processor architecture for faster execution of Arithmetic application

MPSoC design and implementation using Microblaze soft core processor architecture for faster execution of Arithmetic application

MPSoC design and implementation using microblaze soft core processor architecture for faster execution of arithmetic application

The research paper presents the design methodology with novel task distribution technique on multi-processor system on chip (MPSoC) for speeding up the execution of arithmetic application. Utilisation of multiple soft core processors on field programmable gate array (FPGA) reduces the overload of adding external hardware to a system. Parallel processing of soft core processor with proposed task distribution technique makes any application to execute at faster rate. This task distribution based speed enhancement technique for arithmetic application is very feasible and appealing to the modern applications like neural networks, fuzzy logic, algorithms of machine learning etc. Experimentation on such architecture with arithmetic application shows significant increase in speed of operation with respect to conventional design. This is implemented using Microblaze soft core processor architecture on Xilinx Virtex 5 FPGA board.

Proposal of a reliable embedded circuit to control a stepper motor using microblaze soft-core processor

The vast majority of embedded system designs start with a processor-based system, using a microcontroller or microprocessor as the core element to predict and process the basic control tasks. This paper aims to increase the reliability of controlling a stepper motor by an embedded circuit, which generates four digital signals of pulse width modulation (PWM). The manager of this circuit is an embedded processor licensed from Microblaze, which sits within the FPGA architecture Virtex 5. This processor analyzes the parameters to execute the rotation under the best conditions (energy consumption, speed, precision, reliability). The communication with the PC takes place via the RS232 link to provide feedback. The autonomous processor generates an independent control frequency of the PC. The four digital signals of PWM are simulated on Xilinx's ISim interface and sent to the ULN2803 amplifier circuit to run the stepper motor.

Accelerating Population Count with a Hardware Co-Processor for MicroBlaze

This paper proposes a Field-Programmable Gate Array (FPGA)-based hardware accelerator for assisting the embedded MicroBlaze soft-core processor in calculating population count. The population count is frequently required to be executed in cyber-physical systems and can be applied to large data sets, such as in the case of molecular similarity search in cheminformatics, or assisting with computations performed by binarized neural networks. The MicroBlaze instruction set architecture (ISA) does not support this operation natively, so the count has to be realized as either a sequence of native instructions (in software) or in parallel in a dedicated hardware accelerator. Different hardware accelerator architectures are analyzed and compared to one another and to implementing the population count operation in MicroBlaze. The achieved experimental results with large vector lengths (up to 217) demonstrate that the best hardware accelerator with DMA (Direct Memory Access) is ~31 times faster than the best software version running on MicroBlaze. The proposed architectures are scalable and can easily be adjusted to both smaller and bigger input vector lengths. The entire system was implemented and tested on a Nexys-4 prototyping board containing a low-cost/low-power Artix-7 FPGA.

FPGA implementation of a wireless sensor node with a built-in ADALINE neural network coprocessor for vibration analysis and fault diagnosis in machine condition monitoring

Abstract Industry is a very attractive research field for wireless sensor network (WSN) applications. This is demonstrated by the creation of a special category of these networks dedicated to industrial applications, called industrial wireless sensor networks (IWSN). The sensor node, the main component of the network, must have several characteristics, such as a very high processing speed, reliable results, communication capabilities, and reduced transmission time. In this article, we outline the results of replacing the fast Fourier transform (FFT) processing of vibrational signals with an artificial adaptive linear element (ADALINE) neural network in order to extract the harmonics of the signals and thus detect faults in rotating machines. In addition, a MicroBlaze soft-core processor and an nRF24L01+ transmitter was chosen to manage various tasks within the node and the data exchange between the nodes of the network. A Digilent Cmod A7 platform with an Artix-7 FPGA circuit from Xilinx was selected to implement the different blocks that constitute the wireless node. Practical tests showed that the choice of the ADALINE enabled us to achieve the desired results by reducing the processing time to 7.478 ms, which is a reduction of time of approximately 85% compared to results obtained in scientific research. In addition, we have reduced the number of transmitted packets to only two. These results will have a positive impact on the performance of the node, with measurements using a periodic measurement methodology showing that the lifetime of the node can reach up to 17 h.

Implementation of Sensor Precision Mirror Rate using FPGA

The research contribution is increasing in the field of autonomous spacecraft. The major role contributes to the navigation methods for spacecraft. The intended control design is required precision mirror rate sensor (PMRS) to maintain positioning and stability of the satellite. One major drawback of the PMRS resides in the lock in effect, by which the sensor is not capable of sensing the rotation at low inertial angular rates. In the proposed work due to the uniqueness, it is able to sense the rotation even at the low inertial angular rates. The frequency control loop has been designed, it generates the resonance frequency using dither motor. The frequency control loop of the PMRS, is developed using a 32 bit MICROBLAZE soft core processor along with PID algorithm and same is executed using Xilinx Spartan 6 FPGA.

Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microblaze Soft Core Processor

Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.

Performance Estimation of Scheduling Algorithms on Microblaze Softcore Processor

Performance Estimation of Scheduling Algorithms on Microblaze Softcore Processor

Area and Energy Efficient Viterbi Accelerator for Embedded Processor Datapaths

Viterbi algorithm is widely used in communication systems to efficiently decode the convolutional codes. This algorithm is used in many applications including cellular and satellite communication systems. Moreover, Serializer-deserializers (SERDESs) having critical latency constraint also use viterbi algorithm for hardware implementation. We present the integration of a mixed hardware/software viterbi accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency. Later we investigate the performance of viterbi accelerated embedded processor datapath in terms of execution time and energy efficiency. Our evaluation shows that the viterbi accelerated Microblaze soft-core embedded processor datapath is three times more cycle and energy efficient than a datapath lacking a viterbi accelerator unit. This acceleration is achieved at the cost of some area overhead.

Template attack on SPA and FA resistant implementation of Montgomery ladder

Hardware implementations of the well-known Rivest–Shamir–Adleman (RSA) algorithm have been shown to be vulnerable to power and fault analysis (FA) attacks. To implement protected designs of RSA-Chinese remainder theorem in embedded devices, like smart cards or RFIDs, the one needs to find solutions which require less computations as well as incurs low storage overheads. One such efficient scheme was proposed by Joye et al. in CHES'02 and it was claimed to be secure against both simple power analysis (SPA) and FA attacks. In this study, the authors demonstrate a template attack (TA) against Joye's countermeasure and show that the scheme can be broken with a low number of power traces. In addition, the authors report the experimental results of the proposed attack against an implementation of Joye's scheme on a Xilinx Microblaze soft-core processor of SASEBO-W standard side-channel analysis board. The authors used least squares support vector machine (LS-SVM) based binary classifiers to analyse the collected power traces. The authors also describe the potential threat posed by cache timing attacks on Joye's ladder in presence of a concurrently running spy process and outline a probable countermeasure to the posed attacks.

FPGA Prototype Implementation of Digital Hearing Aid from Software to Complete Hardware Design

The design and implementation of digital hearing aids requires a detailed knowledge of various digital signal processing techniques used in hearing aids like Wavelet Trans-forms, uniform and non-uniform Filter Banks and Fast Fourier Transform (FFT). In this paper the design and development of digital part of hearing aid is divided into three different phases. In the first phase review and Matlab simulation of various signal processing techniques used in the digital hearing aids is presented. In the second phase a software implementation was carried out and the firmware was designed for the Xilinx Microblaze softcore processor system. In the third phase everything was moved into hardware using VHDL hardware description language. The implementation was done on Xilinx Field Programmable Gate Array (FPGA) Development Board.

DEVELOPMENT OF SOFTCORE PROCESSOR

Designing of softcore processor on FPGA is based on software hardware co design. A soft-core processor is a hardware description language (HDL) model of a specific processor (CPU) that can be customized for a given application and synthesized for an ASIC or FPGA target. Embedded Systems which performs specific application using components having hardware and software together is known as embedded system. With hardware design getting complicated day by day, using of software tools for designing the system and testing has made the necessity of today’s technology. Due to the reduced size and greater complexity of hardware models, it requires a higher technological tool for simulation to satisfy the needs of the designers. The more efficient the simulator, complexity in the hardware model can be easily executed in small intervals of time, resulting in design product in a stipulated time intervals. The design of soft core processor system involves strict performance involving area, time, power, cost constraints. Advantages of Softcore processor design improves in design quality reduce integration and test time, supporting growing complexity of embedded system, processor cores, high level hardware synthesizing capabilities, ASIC/FPGA development and platform independence. Xilinx microblaze softcore processor support package allows to create mixed Hardware Software application using micro blaze processor. These processors are called as soft-core processor. Soft IP core of Xilinx micro blaze can be used on series of FPGA.

Distance and Speed Measurements using FPGA and ASIC on a high data rate system

This paper deals with the implementation of FPGA and ASIC designs to calculate the distance and speed of a moving remote object using laser source and echo pulses reflected from that remote object. The project proceeded in three phases for the FPGA implementation: All-in-C design using Xilinx Microblaze soft core processor system, an accelerated design with custom co-processor and Microblaze soft core processor system, and full custom hardware design implemented using VHDL on Xilinx FPGA. Later the complete system was implemented on ASIC. The ASIC implementation optimized the modules for area and timing for a 130nm process technology.

A Spartan 6 FPGA-based data acquisition system for dedicated imagers in nuclear medicine**This paper was originally submitted for inclusion in the special feature on Imaging Systems and Techniques 2011.

We present the development of a four-channel low-cost hardware system for data acquisition, with application in dedicated nuclear medicine imagers. A 12 bit octal channel high-speed analogue to digital converter, with up to 65 Msps sampling rate, was used for the digitization of analogue signals. The digitized data are fed into a field programmable gate array (FPGA), which contains an interface to a bank of double data rate 2 (DDR2)-type memory. The FPGA processes the digitized data and stores the results into the DDR2. An ethernet link was used for data transmission to a personal computer. The embedded system was designed using Xilinx's embedded development kit (EDK) and was based on Xilinx's Microblaze soft-core processor. The system has been evaluated using two different discrete optical detector arrays (a position-sensitive photomultiplier tube and a silicon photomultiplier) with two different pixelated scintillator arrays (BGO, LSO:Ce). The energy resolution for both detectors was approximately 25%. A clear identification of all crystal elements was achieved in all cases. The data rate of the system with this implementation can reach 60 Mbits s−1. The results have shown that this FPGA data acquisition system is a compact and flexible solution for single-photon-detection applications.

An FPGA Implementation Of Hearing Aids based on Wavelet-Packets

Advances in digital signal processing and microelectronics have led to the development of superior digital hearing aids for ameliorating severe defects of hearing. The progress in field programmable gate arrays (FPGA) technology, especially for miniaturized system applications, allowed increasing sophisticated features to be built for better sound reproduction, keeping small size and low power consumption of the devices. In this paper the recent trend of combining interconnects of FPGAs with embedded microprocessors and related peripherals to form a complete system on a programmable chip is employed for the design of digital hearing aids. Wavelet packet transform is applied for speech compensation of the hearing loss. The wavelet packet module is described in VHDL, implemented on FPGA and then added as a peripheral to the processor system. The embedded software processor used is the MicroBlaze soft core processor. The chip used is Digilent XUP II Virtex-II Pro system FPGA containing audio codec LM4550. The features of the design are small area and fast processing and low cost.

线阵光学降水现象自动测量系统

An optical precipitation auto-measurement system based on a linear image sensor was designed to reveal the physical mechanism and essence of the precipitation.First,according to physical characteristics of precipitation particles and the demand for precipitation observation,an optical unit and a data acquisition and processing platform for the high speed linear image sensor were designed.As the mass acquisition data were inconvenient for transmission and processing under a continuous operation,the real-time binarization and encoding processing of the linear image were carried out by Field Programmable Gate Array(FPGA).To eliminate the influence of performance excursion of parallel light source and pixel photoelectric response nonuniformity on the setting thresholds and to ensure the measurement precision and coherence,an adaptive threshold setting scheme was proposed and realized based on a MicroBlaze soft-core processor in the FPGA.The comparison experiment with tipping bucket pluviometer based on calibration in a laboratory was carried out.Experimental result indicates that the resolution of precipitation auto-measurement system can achieve 0.1 mm,and the error of cumulative precipitation amount in synchronization observation is about 15%.Obtained results can satisfy the requirements of precipitation auto-measurement for stabilization and high precision.

HartOS - a Hardware Implemented RTOS for Hard Real-time Applications

This paper introduces HartOS, a hardware-implemented, micro-kernel-structured RTOS targeted for hard real-time embedded applications running on FPGA based platforms. Historically hardware RTOSs have been too inflexible and have had limited features and resources. HartOS is designed to be flexible and supports most of the features normally found in a software-based RTOS. To ensure fast, low latency and jitter-free communication between the CPU and RTOS, HartOS uses the ARM AXI4-Stream bus recently supported by the MicroBlaze softcore processor. Compared to μC/OS-II, HartOS has up to 3 orders of magnitude less mean error in generating the correct period for a periodic task, and around 1 order of magnitude less jitter, while having up to 100% less overhead depending on the tick frequency.

A Custom FPGA Processor for Physical Model Ordinary Differential Equation Solving

Models of physical systems, such as of human physiology or of chemical reactions, are typically comprised of numerous ordinary differential equations (ODEs). Today's designers commonly consider simulating physical models utilizing field-programmable gate arrays (FPGAs). This letter introduces a resource efficient custom processor-the differential equation processing element, or DEPE-specifically designed for efficient solution of ODEs on FPGAs, and also introduces its accompanying compilation tools. We show that a single DEPE on a Xilinx Virtex6 130T FPGA executes several physiological models faster than real-time while requiring only a few hundred FPGA lookup tables (LUTs). Experiments with a commercial high-level synthesis(HLS) tool show that while a single DEPE is 5-50× slower than HLS circuits, DEPE is 10-200 × smaller. We show that a single DEPE is only 10× slower than a relatively massive and costly 3 GHz Pentium 4 desktop processor for ODE solving, and its speed is also competitive with a 700 Mhz TI digital signal processor and an 450 Mhz ARM9 processor. DEPE is 4×-17× faster than a Xilinx MicroBlaze soft-core processor and 3 ×-6 × smaller. DEPE thus represents an excellent processing element for use by itself for small physical models, and in future parallel networks for larger models.