MHz Unity Gain Frequency Research Articles

Three-Stage Operational Amplifier with Frequency Compensation Using Cascade Zero

Short channel MOSFET exhibits the characteristics of wide bandwidth and low DC gain. A low DC gain causes a high gain error and a narrow output linear range in the closed loop. The DC gains can be improved by using the cascade structure, but frequency compensation is required due to the increase in the number of poles. The output nodes of each stage in a cascade Common-Source amplifier have a cascade of zero, and this zero is cancelled out by the input node of the next stage. This paper proposes a three-stage operational amplifier (op-amp) with frequency compensation using cascade zero. This op-amp was implemented in the 180 nm CMOS technology and achieved 86.96 MHz unity–gain frequency, 51.7° phase margin at 32 pF load capacitor and 99.83 dB DC gain, that is, a 36.21 dB improvement over a two-stage op-amp with the same power consumption. The op-amp consumed 7.74 mW with a supply voltage of 1.8 V.

Design and analysis of a three stage CMOS op-amp using indirect feedback compensation

With the rapid change in CMOS technology, the scaling has resulted in faster transistors. But the rate of decrease in threshold voltage is too low. The intrinsic gains from the transistors is diminishing and hence the open-loop gain. This led to paths for the techniques like vertical stacking which is not well suited for low power designs and has constraints on swing. Thus, horizontal cascading must be used to achieve higher gains for the op-amp at lower VDD. This paper presents a simple three stage class A op-amp using Indirect Feedback Compensation. The op-amp has been designed and simulated at 180nm process and it produces an open-loop gain of 84.7db, 45.65MHz unity gain frequency, 89° phase margin and 14.45V/μSec SR and it is capable to drive a 30pF load.

Design of FinFET Based Self-Biased OTA for Low Power Applications

This work explores the design of an Operational Trans conductance Amplifier (OTA) using Independent Gate (IG) FinFET. For the different configurations of FinFET such as IG, Low Power (LP) and Shorted Gate (SG), optimal gm and ro values have been found. FinFET devices are used to increase the performance by reducing the power dissipation as the front and back gate voltages are controlled independently. The designed three stage FinFET based OTA operates at 0.5 V power supply and achieves gain of 64 dB, 33 phase margin and 20 MHz unity gain frequency. The proposed OTA circuit is tested in Cadence virtuoso with FinFET 32nm BSIM-CMG model.

A Pseudo Single-Stage Amplifier With an Adaptively Varied Medium Impedance Node for Ultra-High Slew Rate and Wide-Range Capacitive-Load Drivability

This paper presents a pseudo single-stage (PSS) amplifier with an adaptively varied medium impedance node to achieve an ultra-high slew rate (SR) and at the same time stable operation in a wide capacitive load range. Owing to the characteristics of the proposed technique, this amplifier achieves a 1.1-to-8.67 $\text{V}/\mu\text{s}$ slew rate and a 0.01-to-1.66 MHz unity gain frequency over a 0.1-to-15 nF capacitive load $(C_{L})$ with an over 69° phase margin while consuming a total quiescent power of only 7.4 $\mu\text{W}$ . This chip was fabricated in a 0.18 $\mu\text{m}$ CMOS process with a silicon area of 0.0021 mm2.

Low‐power CMOS variable gain amplifier based on a novel tunable transconductor

A CMOS variable gain amplifier (VGA) based on a novel linear and tunable triode transconductor is presented. The proposed transconductor employs local negative feedback for linearisation controlling the drain voltage of the input transistors biased in the triode region. The new design is able to operate at low supply voltage and the stability is guaranteed. The transconductor features a 47.75 dB dc gain and a 4.23 MHz unity gain frequency with a power consumption of only 91 µA. To show the feasibility of the proposed transconductor, a VGA has been fabricated. Measurement results for a 0.13 µm CMOS design show a −3 dB bandwidth above 2.8 MHz and a third-order harmonic distortion at 500 kHz below −46 dB over the whole gain range. The VGA exhibits a maximum power consumption of only 395 µW from a single 1.2 V supply.

0.0045 mm 2 15.8 µW three‐stage amplifier driving 10×‐wide (0.15–1.5 nF) capacitive loads with >50° phase margin

A three-stage amplifier employing embedded capacitor-multiplier compensation (ECMC) and active parallel compensation (APC) to enhance the area efficiency when driving nF-range capacitive loads (C L) is presented. Unlike the conventional current-buffer Miller compensation, ECMC applied to the dominant compensation path saves substantial power and area, while securing a large gain–bandwidth product. The created left-half-plane zero also benefits the phase margin (PM). For the APC, unlike the traditional passive parallel compensation, this work benefits from the Miller effect to avoid the area-consuming resistor, and reduces the entailed capacitances without lowering the parasitic pole position. A multi-path G m-boosting second stage enhances the effective transconductance and DC gain. With 0.0045 mm2 of area and 15.8 µW of power, the 0.18 µm CMOS three-stage amplifier measures 1.13 MHz unity-gain frequency, 0.41 V/µs average slew rate and 56.2° PM at 1 nF C L. Stable responses with >50° PM are attained for a 10 × range of C L from 0.15 to 1.5 nF. The achieved figure-of-merit accounting for both die area and power compares favourably with the state of the art.

A high-performance 1.2 V–99 μW rail-to-rail CMOS class AB amplifier

This paper presents a compact, reliable 1.2V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18μm CMOS technology, exhibits 86dB open loop gain and 97dB CMRR. Experimental measurements prove its correct functionality operating with 1.2V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5MHz unity gain frequency and a 3.15V/μs slew-rate for a capacitive load of 100pF, with a power consumption of 99μW.

Ultra‐low power design strategy for two‐stage amplifier topologies

A novel two-stage amplifier topology and ultra-low power design strategy for two-stage amplifiers that utilises pole zero cancellation to address the additional power requirements for stability are presented. For a 288 nA total bias, the presented amplifier achieves a 1.07 MHz unity gain frequency with a 8560 pF MHz/mA figure of merit.

A design of low voltage OPAMP using split-length transistors

In the paper, we present a design of a low voltage Operation Amplifier (OPAMP) circuit using split-length transistors. Indirect feedback compensation is an advanced technique used to stabilize the operation of an OPAMP. Cascode transistors are usually implemented for indirect feedback systems. However, these transistors are not suitable for low voltage design. In this study, we have taken advantage of split-length transistors and indirect feedback compensation technique to design a high performance OPAMP. As a result, the OPAMP operates not only at low supply voltage but also at high frequency. The OPAMP has been designed and fabricated in a 0.18um CMOS technology. This OPAMP achieves 100 dB gain, 90 MHz unity gain frequency and 60 degrees phase margin at 2 V supply voltage.

Analog circuit synthesis performing fast Pareto frontier exploration and analysis through 3D graphs

This paper presents a technique for performing analog design synthesis at circuit level providing feedback to the designer through the exploration of the Pareto frontier. A modified simulated annealing which is able to perform crossover with past anchor points when a local minimum is found which is used as the optimization algorithm on the initial synthesis procedure. After all specifications are met, the algorithm searches for the extreme points of the Pareto frontier in order to obtain a non-exhaustive exploration of the Pareto front. Finally, multi-objective particle swarm optimization is used to spread the results and to find a more accurate frontier. Piecewise linear functions are used as single-objective cost functions to produce a smooth and equal convergence of all measurements to the desired specifications during the composition of the aggregate objective function. To verify the presented technique two circuits were designed, which are: a Miller amplifier with 96 dB Voltage gain, 15.48 MHz unity gain frequency, slew rate of 19.2 V/μs with a current supply of 385.15 μA, and a complementary folded cascode with 104.25 dB Voltage gain, 18.15 MHz of unity gain frequency and a slew rate of 13.370 MV/μs. These circuits were synthesized using a 0.35 μm technology. The results show that the method provides a fast approach for good solutions using the modified SA and further good Pareto front exploration through its connection to the particle swarm optimization algorithm.

The Design of an Operational Amplifier Using Silicon Carbide JFETs

Superior performance of the Silicon Carbide (SiC) semiconductor in high temperature and harsh environment is widely known. However, utilizing the Vertical Channel 4H-SiC JFET (SiC JFET) for analog design exhibits significant design challenges, even at room temperature. The fundamental challenges are low intrinsic gain, the limitation of the Gate to Source Voltage Range (GSVR), and restrictions on utilizing Channel Length (CL) as a design parameter due to fabrication complexity. These challenges must be successfully overcome at room temperature, before moving towards high temperature design. The main objective of this paper is to establish a design base, overcome the challenges, demonstrate the feasibility, and present a novel all SiC JFET based operational amplifier (opamp) that addresses overall performance at room temperature. Before attempting design, Enhancement Mode (EM) and Depletion Mode (DM) SiC JFETs are characterized, analyzed, and modeled for simulation. A unique and reliable four stage opamp configuration is presented that takes design requirements into account, uses threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) in place of CL as a design parameter, and employs gain enhancing design techniques while achieving maximum obtainable frequency response. The final opamp is fabricated and tested and shown to have 66.7 dB DC gain and 5.71 MHz unity gain frequency.

A Novel Low-Power CMOS Operational Amplifier with High Slew Rate and High Common-Mode Rejection Ratio

Problem statement: High speed operational amplifier is always an on-go ing research topic since major high speed application are needed. Approach: A two-stage operational amplifier (op amp) is designed, simulated and fabricated using a UMC 0 .5 µm 2P2M CMOS technology. Results: This chip includes a compensation technique to ensure st ability and zero systematic input-offset-voltage. The fabricated chip achieves a 84 dB open loop gain , a 24 V µS -1 slew rate, a 84 dB CMRR utilizing a capacitive load of 5 pF, a 30 MHz unity gain frequency and consumes 2.8 mW from a 2.5 V power supply. Conclusion: The proposed chip, which is the first available CMO S operational amplifier in Jordan as the authors are aware, is we ll-suited to low-voltage applications since it does not require cascade output stages.

Rail-to-rail BiCMOS operational amplifier using input signal adapters with floating outputs

An operational amplifier with rail-to-rail input and output voltage range in 0.6 μm BiCMOS technology is presented. Two simple input signal adapters with floating outputs serving as pre-stages are introduced. They are followed by a differential amplifier. The adapters translate the input signals into a floating level within the operating region of the differential amplifier, enabling rail-to-rail operation. An inverter-based simple rail-to-rail class AB output stage has been used. With a single supply of 1.5 V, the proposed rail-to-rail operational amplifier achieves 72 dB DC open-loop gain, 2.54 MHz unity-gain frequency, 62° phase margin, 2.5 V/μs slew rate, and 147 μW power consumption.

Fast settling opamp with low power consumption

This paper presents a design strategy to minimize step response settling time of a two stage miller opamp with low power consumption. Appropriate spacing between poles and zero has been kept, so an underdamped transient response with minimum settling time is obtained. Analytical results show that for a specific load capacitor, if zero frequency is placed at appropriate distance from unity gain frequency, then minimum settling time can be obtained. Analysis using device modelling has been carried out to determine element values for optimum compensation followed by its simulations in triple metal layer n-well CMOS process using 0.5 µ technology. Best simulation results obtained on Tanner tool show 86.2 dB gain, 136.6 MHz unity gain frequency (ωμ ), 25 ns settling time (ts ) with 1pf load, 211 V/µs slew rate (SR) with 1pf load, and 2.56 mW of power dissipation. The approach reported has been found to be the best after carrying out extensive performance evaluation through simulation.

An optimization approach to designing OTAs for low-voltage sigma-delta modulators

High performance operational transconductance amplifier (OTA) structures for high-speed, low-voltage, switched-capacitor (SC) based sigma-delta modulator applications have been designed utilizing an efficient circuit optimization strategy presented in this paper. The main idea is to use external programs together with a circuit optimizer to construct flexible optimization algorithms. Optimization goals and constraints are derived from analytical equations and application requirements. Using a 0.35 /spl mu/m CMOS processing technology a complementary folded cascode feedforward compensated (CFCFC) OTA with 2.5 V supply obtained 470 MHz unity-gain frequency, 350 V//spl mu/s slew rate, over 74 dB gain, and over 70/spl deg/ phase margin using 10 pF load capacitances. The optimization strategy was verified by measuring fabricated CFCFC OTA and sigma-delta modulator. The measurement results demonstrate a good agreement with the simulations.

Compact High Gain CMOS Op Amp Design using Comparators

This paper discusses the design of high gain, general purpose op amps. The op amp is based on a novel cascaded design using comparators and with structural simplicity approaching that of digital circuits. Ideally, the design tool presented here can be used to optimize gain and CMRR independent of the other op amp performance parameters. The designed op amp has 140 dB open-loop gain and 43 MHz unity gain frequency (GBW) in Berkeley Spice3f Level-2 simulation. The circuit is implemented using a 2.0 μm nwell CMOS process through MOSIS. The op amp is self-biased and requires only power supplies of ±2.5 V. It occupies an area of 113 μm×474 μm.

A Low-Voltage Fully Differential Constant-Gm Rail-to-Rail CMOS Operational Amplifier

A low-voltage fully differential CMOS operational amplifier with constant-g_m and rail-to-rail input and output stages is presented. It is the fully differential version of a previously realized single-ended operational amplifier where a novel circuit to ensure constant transconductance has been implemented [1]. The input stage is a rail-to-rail structure formed by two symmetrical OTAs in parallel (the input transistors are operating in weak inversion). The class-AB output stages have also a full voltage swing. A rail-to-rail input common mode feedback structure allows the output voltage control. Measurements in a 0.7 µ standard CMOS process with threshold voltages of about 0.7 V have been done. The minimum experimental supply voltage is about 1.1 V. The circuit provides a 60 dB low frequency voltage gain and about 1.5 MHz unity gain frequency for a total power consumption of about 0.72 mW at a 1.5 V supply voltage.

A fast-settling 3 V CMOS buffer amplifier

This paper presents a two-stage fast, power-efficient 3 V CMOS buffer amplifier with rail-to-rail input/output voltage ranges. Because of its constant g/sub m/, class-AB input stage, the amplifier is free of slew-rate limitation and its settling-time is quasi-independent on input step amplitude. The amplifier has 6 MHz unity-gain frequency, 1 mW power-consumption and settles to 1% accuracy within 180 ns on 100 pF load. As the class-AB input stage operates at constant quiescent current over the input voltage range, CMRR exceeds 70 dB.

A programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested Miller compensation for 120 dB gain and 6 MHz UGF

The paper presents a rail-to-rail class-AB operational amplifier in a standard v/sub th/=0.6 V CMOS technology operating at 1.5 V. A hybrid nested Miller compensation technique yields 6 MHz unity gain frequency at 300 /spl mu/A supply current, 120 dB gain and programmability. Operation down to 1.0 V at 15 /spl mu/A is possible with 300 kHz UGF. The die area of the chip is 0.05 mm/sup 2/ (70 mil/sup 2/).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>