Abstract
A novel two-stage amplifier topology and ultra-low power design strategy for two-stage amplifiers that utilises pole zero cancellation to address the additional power requirements for stability are presented. For a 288 nA total bias, the presented amplifier achieves a 1.07 MHz unity gain frequency with a 8560 pF MHz/mA figure of merit.
Highlights
Power-efficient amplifier topologies are fundamental for analogue processing both in the continuous and discrete time domains
The prevalence of limited power budgets in medical sensors indicates that advances in lowpower analogue amplifiers are critical for the future of implantable biomedical systems that are constrained through battery life and wireless telemetry [1, 2]
This allows a simple reduction in power by a factor of two for single-stage systems, but a second stage is often required in switched capacitor (SC) applications for high gain and wide output swing
Summary
Power-efficient amplifier topologies are fundamental for analogue processing both in the continuous and discrete time domains. 103 2pVov where UGF, CL, Itotal and Vov are the unity gain frequency, load capacitance, total bias current and overdrive voltage of the input transistors, respectively. With the input transistors biased in weak inversion, the FOM is derived as FOMwi. 103 4p · hUT with η and UT being the sub-threshold slope factor and thermal voltage, respectively. By coupling the input signal to biasing transistors M3–4 for instance, a larger transconductance can be achieved with the same bias current. This allows a simple reduction in power by a factor of two for single-stage systems, but a second stage is often required in switched capacitor (SC) applications for high gain and wide output swing. We identify appropriate scaling factors for the FOM such as to make this applicable to two-stage amplifiers
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