Power and Area Efficient Capacitor Multiplier Technique for Multi-Fin Two Stage Opamp

Abstract

A two stage operational amplifier operating at low power and voltage using multi-fin technology applicable for driving a broad range of capacitive load (CL) is presented in this paper. It makes use of a novel embedded capacitor multiplier (CM) compensation mechanism which has several advantages: 1) Since Capacitor multiplier (CM) is embedded at the first stage (i.e. at the differential input stage) of the operational amplifier there is no requirement of extra bias circuit and power.2) Unlike other compensation techniques it create a LHP (Left Half Plane) due to the feed forward signal path which in turn increases the stability of the two stage operational amplifier.3) It provides a very fast transient response and enhances the power and area efficiency by minimizing the physical size of the capacitor. The proposed circuit is incorporated with AB amplifier at the output stage to achieve fast transient behavior and to maintain low static power dissipation. The circuit is simulated at 45nm technology using cadence analog virtuoso tool. The simulation results is obtained by substituting different values of the capacitive load (CL). The simulation result demonstrates that when driving a capacitive load (CL) of 20pF the amplifier measures 1.56-v/μs average slew rate (SR), 83° phase margin (PM) and 7.4MHZ unity-gain frequency (UGF), and when it is driving a capacitive load of 15nF it measures 0.045-v/μs average slew rate (SR) and 0.87MHZ unity-gain frequency (UGF), 67° phase margin (PM) while dissipating only 4.46μW under 1.5V supply.