MHz Operation Research Articles

SAW Humidity Sensing with rr-P3HT Polymer Films.

In the present paper the humidity sensing properties of regioregular rr-P3HT (poly-3-hexylthiophene) polymer films is investigated by means of surface acoustic wave (SAW) based sensors implemented on LiNbO3 (1280 Y-X) and ST-quartz piezoelectric substrates. The polymeric layers were deposited along the SAW propagation path by spray coating method and the layers thickness was measured by atomic force microscopy (AFM) technique. The response of the SAW devices to relative humidity (rh) changes in the range ~5-60% has been investigated by measuring the SAW phase and frequency changes induced by the (rh) absorption in the rr-P3HT layer. The SAW sensor implemented onto LiNbO3 showed improved performance as the thickness of the membrane increases (from 40 to 240 nm): for 240 nm thick polymeric membrane a phase shift of about -1.2 deg and -8.2 deg was measured for the fundamental (~78 MHz operating frequency) and 3rd (~234 MHz) harmonic wave at (rh) = 60%. A thick rr-P3HT film (~600 nm) was deposited onto the quartz-based SAW sensor: the sensor showed a linear frequency shift of ~-20.5 Hz per unit (rh) changes in the ~5-~50% rh range, and a quite fast response (~5 s) even at low humidity level (~5% rh). The LiNbO3 and quartz-based sensors response was assessed by using a dual delay line system to reduce unwanted common mode signals. The simple and cheap spray coating technology for the rr-P3HT polymer films deposition, complemented with fast low level humidity detection of the tested SAW sensors (much faster than the commercially available Michell SF-52 device), highlight their potential in a low-medium range humidity sensing application.

Thermal management and switching performance of β-Ga2O3 vertical FinFET with diamond-gate structure

In this paper, a beta-phase gallium oxide (β-Ga2O3) vertical FinFET with diamond-gate has been studied by Silvaco-ATLAS simulation. The diamond-gate structure achieves adjustable pin (p-insulator-n) junction owing to the diamond-SiO2-Ga2O3 heterostructure. This design also enhances heat dissipation by virtue of the high thermal conductivity of the diamond. Compared to conventional FinFETs, the diamond-gate FinFET (DG-FinFET) reduces the static operating temperature rise by around 17.30%. Additionally, due to its greater heat dissipation capacity, DG-FinFETs provide a 5.84% increase in current density at 1 kA cm−2 current density level. The structural changes in the diamond-gate also result in a significant reduction in the gate-source capacitance (C GS). At 1 MHz operating frequency and the same gate voltage, DG-FinFETs have 69.29% less gate-source charge (Q GS), 70.80% less charge/discharge delay time, 73.70% less switching loss, and 57.15% less conduction loss. Overall, the simulation and analysis presented in this work indicate a promising advancement of the DG-FinFET structure in high-power and rapid switching applications.

The CMOS Pseudo-Thyristor: a zero-static current discriminator circuit

A very low power discriminator circuit for pixelized detectors, called the Pseudo-Thyristor is described in this document. It is a positive feedback topology using regular PMOS and NMOS field-effect transistors (FET's) with zero static current. When a small charge is injected into the circuit, it flips rapidly due to the positive feedback and outputs a logic transition for further digitization. Simulation shows that in a 65 nm process, it is possible to achieve a detecting threshold below 5 fC while maintain the average power consumption below 10 micro-Watts when the hit occupancy is <10% for 40 MHz operation.

Resonant Gate Drive Circuit with Active Clamping to Increase Efficiency and Reliability

In power converters with high switching frequency, drive losses constitute a significant portion of the overall power losses. Resonant gate drivers can reduce drive losses, thereby enhancing the efficiency. However, resonant drivers suffer certain challenges: parameter drifts lead to the mismatch between the resonant frequency and the control frequency, and this mismatch can cause gate-to-source voltage overshoot. Moreover, the resonant driver is susceptible to external interference. This paper proposes a resonant circuit structure and control timing scheme aimed at overcoming these limitations. By incorporating a half-bridge clamp circuit, the proposed design achieves voltage clamping, thereby insulating the system from disturbances caused by mains power fluctuations. When there is a mismatch in resonant frequencies, the strategy employs a combination of hardware circuit diodes and control system timing to prevent overvoltage issues. Additionally, the utilization of MOSFETs minimizes the loss caused by prolonged current flow through body diodes, further reducing the resonant driving losses. Simulations have demonstrated the system’s stability under varying resonant parameters and its effective anti-interference capabilities in voltage clamping. Experiments achieved a power saving of 83.3% at a 1 MHz operating frequency. Both simulations and experimental validations confirm the feasibility of the proposed solution, its effectiveness in interference suppression, handling of resonant mismatches, and its role in further augmenting power conservation.

A 0.11pJ/bit read energy embedded NanoBridge non-volatile memory and its integration in a 28 nm 32 bit RISC-V microcontroller units

A 28 nm 512 Kb NanoBridge (NB) non-volatile memory is developed for an energy-efficient microcontroller unit. 0.11 pJ/bit read energy is achieved by utilizing an inverter sense scheme thanks to large ON/OFF conductance ratio of a split-electrode NB. The read energy is 71% and 54% less than those of a ReRAM and a silicon oxide nitride oxide silicon commercial embedded NOR flash at the same technology node, respectively. Moreover, a 28 nm 32 bit RISC-V microcontroller unit embedded with a 2 Mb NB non-voltage memory is fabricated and achieves 80 MHz operation frequency.

Accelerating deep convolutional neural network on FPGA for ECG signal classification

Abnormal activity of the heart is known as cardiac arrhythmia which must be recognized in earlier stage to prevent sudden death and premature death. The occurrence of arrhythmia increases with age, and it is detected using an electrocardiogram (ECG) signal. Conversely, it is very complex to manually achieve the quick and exact classification due to the complexity, non-linearity and low amplitude of the ECG signal. As a result, the healthcare field requires an automatic system to recognize abnormal heartbeats from a huge amount of ECG records. So, the deep learning algorithm named as Deep Convolutional Neural Network (DCNN) is proposed in this research to analyze the ECG signal on a field-programmable gate array (FPGA). Before performing a classification process, two different processes called signal pre-processing as well as feature extraction are required. For the process of signal pre-processing, the Error Normalised Least Mean Square (ENLMS) algorithm is utilized in our work, and Discrete Wavelet Transform (DWT) technique is performed to take out the relevant features from the ECG signal. Finally, FPGA based one-dimensional DCNN with 3 convolutional layers, 3 pooling layers, and 3 fully connected layers is proposed to classify the signals with proper complex features. The publicly available MIT-BIH arrhythmia and PTB databases are exploited in this research to process ECG signals on the multi-input structure. In addition, different performance parameters like classification accuracy, specificity, sensitivity, and precision are engaged to evaluate the proposed methodology; also, it is compared with different FPGA based existing classifiers. The analysis shows that the proposed design accomplishes 98.6 % classification accuracy on the MIT-BIH arrhythmia database and 99.67 % accuracy on the PTB database, which is 0.304 % higher than a multilayer perception (MLP) and 0.47 % higher than decision-based classifier. Moreover, the proposed FPGA based DCNN accelerator consumes 0.45 mW, 185.426 MHz operation frequency and takes 15 s to complete the classification process.

Picosecond to microsecond dynamics of X-ray irradiated materials at MHz pulse repetition rate

Modern X-ray free-electron lasers (XFELs) produce intense femtosecond X-ray pulses able to cause significant damage to irradiated targets. Energetic photoelectrons created upon X-ray absorption, and Auger electrons emitted after relaxation of core-hole states trigger secondary electron cascades, which contribute to the increasing transient free electron density on femtosecond timescales. Further evolution may involve energy and particle diffusion, creation of point defects, and lattice heating. This long-timescale (up to a microsecond) X-ray-induced dynamics is discussed on the example of silicon in two-dimensional geometry. For modeling, we apply an extended Two-Temperature model with electron density dynamics, nTTM, which describes relaxation of an irradiated sample between two successive X-ray pulses, emitted from XFEL at MHz pulse repetition rate. It takes into account ambipolar carrier diffusion, electronic and atomic heat conduction, as well as electron-ion coupling. To solve the nTTM system of equations in two dimensions, we developed a dedicated finite-difference integration algorithm based on Alternating Direction Implicit method with an additional predictor-corrector scheme. We show first results obtained with the model and discuss its possible applications for XFEL optics, detectors, and for diagnostics tools. In particular, the model can estimate the timescale of material relaxation relevant for beam diagnostic applications during MHz operation of contemporary and future XFELs.

High-Efficiency GaN-Based Power Amplifiers for Envelope Nonlinearities’ Mitigation in VHF Wideband Polar-Mode Transmitters

Space-based communications at the very high frequency (VHF) band for air traffic management is a new technology application under development that requires energy-efficient architectures to mitigate the power limitations of satellite platforms. The usage of high-efficiency radiofrequency (RF) transmitters can help reduce the power consumption, but nonlinearities concerning the amplified signal in wide fractional bandwidth systems are a problem to solve. This paper proposes a high-efficiency (RF) power amplifier (PA) for satellite communications at the VHF band that aims to reduce the envelope distortion inherent to wide fractional bandwidth multicarrier polar-mode transmitters. Its design is based on a solution called hybrid-coupled switching voltage PA in combination with gallium nitride (GaN) high electron mobility transistor (HEMT) technology. The developed VHF PA prototype delivers up to 95 W from a 28 V power supply, with a drain efficiency about 80% within the 118 MHz to 138 MHz operating band. To test its linearity performance, operating in a polar-mode configuration, a GaN-based wideband envelope amplifier (EA) has been developed to modulate the RF PA supply port. This EA improves its power efficiency by combining it with a slow envelope power supply (SEPS). Some measurements have been taken for a 100 W peak envelope power (PEP) and 10 MHz (maximum carrier spacing) four-tone digitally-modulated test signal, where any distortion product is attenuated 46 dB below the average power of the amplified signal without applying any digital predistortion (DPD) technique.

Load and Coupling Variations Analysis of Capacitive Power Transfer at 6.78MHz Operating Frequency for Biomedical Implantable Device

This paper presents the design and analysis of load and coupling variations for a current Wireless Power Transfer (WPT) technique, known as Capacitive Power Transfer (CPT). Due to its strength, CPT becomes an effective and essential alternative to conservative technique, which is Inductive Power Transfer (IPT). It can compete IPT in industrial demand since it has a small number of component usage, uncomplicated topology, increases electromagnetic interference (EMI) shielding performance and robust to surrounding metallic elements. Class E power amplifier with the presence of π1b matching resonant circuit is applied in this work as a high frequency ac power source since it has the ability to perform dc-to-ac inversion efficiently. It supports the CPT system to attain a maximum power transmission. MATLAB software is used to design and simulate the CPT circuit; and the analysis is made up from the results. This proposed system able to generate 1W of output power by maintaining up to 98% efficiency at 6.78MHz operating frequency for Biomedical Implantable Device application. The analysis of load variation is in the range of 50Ω until 1kΩ; meanwhile for coupling variation is between 1mm to 15mm.

Analysis of thermal-offset drift of a high-resolution current probe using a planar Hall resistance sensor

Abstract. We developed a pin-type current probe with high sensitivity, targeting electrical-probing printed circuit boards (PCBs). The developed sensor showed good enough characteristics, with 1 mA resolution on current measurements and up to 1 MHz operating frequency for analyzing highly integrated PCBs. During its characterization, however, we experienced a monotonously varying output signal in the time range of a few tens of minutes. We modeled it as the thermal-offset drift, being caused by Joule heating during sensor operation, and showed several solutions for reducing the offset by modifying the planar Hall resistance (PHR) layout and electric operation conditions and applying sensor circuitry with pulse width modulation.

A Scalable Electronic-Embedded Transformer, a New Concept Toward Ultra-High-Frequency High-Power Transformer in DC–DC Converters

The demand for high-power and high-density isolated dc-dc converter is driven by the rapid development of energy storage system, data center power supplies and transportation electrification. However, designing a high-power and high-frequency transformer presents significant challenges due to the trade-off between thermal management, leakage inductance minimization, and insulation requirements. In order to overcome this trade-off between power rating and operation frequency, a scalable electronic-embedded transformer (EET) is proposed with a low voltage bridge integrated into the transformer windings. The EET addresses the challenge through its simple open-loop control and natural current sharing, enabling easy parallel connection and scaling to different power ratings. Based on this concept, a bi-directional EET-based dc transformer (EET-DCX) is proposed to solve the transformer-level paralleling and resonant point shift issues in traditional LLC-DCX designs. By employing the embedded full bridge, the EET-DCX effectively cancels out the impedance of the leakage inductance, ensuring optimal operation at any frequency. Additionally, the EET-DCX retains the inherent advantages of the LLC-DCX, such as load-independent voltage gain, simple open-loop control, full load range zero voltage switching (ZVS), and low circulating current. Leveraging these advantages, the proposed EET-DCX solution has the potential to push the boundaries of transformer performance to the MHz operation frequency range with hundreds of kilowatts power capability. To validate these merits, a 12 kW 500 kHz EET-DCX with four planar EET units was built. This article is accompanied by two videos demonstrating the dynamic load changing and frequency changing test.

A Compact Fully Electronically Tunable Memristive Circuit Based on CCCDTA with Experimental Results.

This work presents a flux-controlled memristor structure employing a Current-Controlled Current Differencing Transconductance Amplifier (CCCDTA) with a grounded capacitor. The proposed emulator's invariant and variant parts can be safely adjustable, showing promising characteristics of up to 1.5 MHz operating frequency. Furthermore, there is no need for an additional circuit, switching mechanism or changing the circuit topology for the changing of operation modes. To justify the performance of the emulator with incremental and decremental mode operations, a Monte Carlo and temperature analysis are validated using TSMC 0.18 µm technology under a symmetrical supply voltage of ±0.9 V. Furthermore, the workability of the proposed circuit is tested with commercial elements such as ALD1116, AD844 and LM13700. When compared with other studies, the presented emulator circuit demonstrates promising performance in various features.

MI-Sensor Element Features and Estimation of Penetration Depth and Magnetic Permeability by Magnetoresistance and Magnetoreactance of CoFeSiB Amorphous Wires

The magnetoimpedance (MI) of amorphous soft magnetic Co <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">68.15</sub> Fe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4.35</sub> Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12.5</sub> B <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sub> wires produced by the in-rotating water quenching technique was systematically studied. The behavior of the MI-element designed for magnetic sensors was examined in an external longitudinal dc magnetic field in the low-frequency range (f ≤ 1 MHz) and at the beginning of the intermediate frequency range (2 MHz ≤ f ≤ 5 MHz). A critical frequency of about 5 kHz - 7 kHz was observed with an initial increase in the MI effect. A maximum MI ratio of 334% was recorded at 0.95 MHz in a magnetically saturated MI-element. The intermediate frequency range is explored using the magnetoresistive - MR and magnetoreactive - MX components of magnetoimpedance Z. The MI anisotropy field profile occurs in the MHz operating frequency range with values increasing up to 25 A/m, exhibiting frequency dependence. The magnetic penetration depth was calculated using experimental magnetoresistance data, and the values obtained were about 3 μm - 4 μm for 5 MHz, showing a saturation trend. The magnetic permeability is analyzed in the framework of the electromagnetic classical high-limit model of a cylinder, which includes penetration depth and magnetoreactance. In our experiments and calculations, the classical high limit is satisfied in the operating frequency range of a few MHz. The magnetic permeability peak value is about 35% lower than the comparable data of amorphous CoFeNiMoSiB glass-coated microwires.

A Compact Rat-Race Coupler with Harmonic Suppression for GSM Applications: Design and Implementation Using Artificial Neural Network.

In this paper, a compact microstrip rat-race coupler at a 950 MHz operating frequency is designed, simulated, and fabricated. New branches are proposed in this design using high-/low- impedance open-ended resonators. In the conventional rat-race coupler, there are three long λ/4 branches and a 3λ/4 branch, and they occupy a very large area. In the presented designed, three compact branches are proposed for use instead of three λ/4 branches and an ultra-compact branch is suggested for use instead of the 3λ/4 branch. Additionally, an artificial neural network (ANN) approach is incorporated to improve the performance of the resonators using a radial basis function (RBF) network. The proposed compact structure has achieved a reduction of more than 82% compared with the size of the conventional coupler structures. Additionally, the proposed coupler can suppress the 2nd up to the 5th harmonic to improve the performance of the device.

The design of inductive power transfer system for fish aquarium using class-E inverter and LCCL impedance matching

&lt;p&gt;Nowadays, the accessories in fish aquarium systems such as water pump, internal filter, and LED light are powered using cables. This will cause to safety issue such as tangled wire, and risk of electric shock. Therefore, this work aims to design a wireless power transfer system to power up the fish aquarium’ accessories wirelessly without require any physical connection between source and loads. To be more specific, inductive power transfer (IPT) is used instead of capacitive power transfer (CPT) due to high efficiency ability owned by IPT. Class-E inverter circuit is proposed in this paper to convert DC to AC at nearly 100% efficiency. The inverter provides a low switching loss which is important as the circuit operates at high frequency, 1 MHz operating frequency. Furthemore, LCCL impedance matching circuit is added into receiver part of the system to enhance the efficiency of overall circuit. The analyses were done based on the distance between the coils and the misalignment of the coils against the output power and efficiency. The developed prototype is supplied by 24 V DC and capable to deliver 5 W power. The overall efficiency of the prototype is 87.81%.&lt;/p&gt;

Single-Sided Interspiraled Inductive Impedance Matching for Magnetic Resonance Wireless Power Transfer

This paper presents a single-sided impedance matching technique, i.e., matching from only the transmitter or receiver side, using a switchable interspiraled coil. This technique is suited for active impedance matching in magnetic resonance wireless power transfer. The switchable coil consists of 9 selectable, single-turn coils placed in-between the 9.5 turns of a spiraled resonator coil with an inductance of approximately 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu H$</tex-math> </inline-formula> . The self-inductances of the single-turn coils vary between 33-493 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$nH$</tex-math> </inline-formula> . The interspiraled coil was realized on a single-sided PCB, making the system compact in size. Circuit analysis and simulation show that the inductance selectability enables impedance matching over a range of distances in a Wireless Power Transfer (WPT) System at 6.78 MHz operation frequency. Measurement and simulation of the efficiency indicate that the proposed interspiraled coil may significantly improve the Power Transfer Efficiency (PTE) when the distance and the load change.

Convolutional neural network-based lightweight hardware IP core design for EEG epilepsy prediction

Epilepsy is one of the most common neurological disorders. In order to realize a portable and wearable epilepsy prediction device, a lightweight hardware IP core is proposed for EEG epilepsy prediction. The scheme first analyzes the epileptic EEG signal and extracts the time-frequency feature maps of interictal and preictal EEG signals. Then it reduces the network parameters using the single-channel approach to reduce the number of neurons and network complexity, and trains the lightweight epilepsy prediction convolutional neural network by combining the time-frequency feature maps. Finally, a hardware convolutional layer is designed with pipeline function, and it connect 8 layers with feature map buffer to realizes the lightweight EEG epilepsy prediction hardware IP core. Using TSMC 65 nm process, the hardware IP core is functionally verified with 87.9% prediction accuracy. The area is 2.55 mm2 and the power is 4.45 mW. Under 1V & 20 MHz operating conditions, single prediction latency is 3.29 ms and energy efficiency is 0.146 μJ/class.

T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training

Recently, on-device training has become crucial for the success of edge intelligence. However, frequent data movement between computing units and memory during training has been a major problem for battery-powered edge devices. Processing-in-memory (PIM) is a novel computing paradigm that merges computing logic into memory, which can address the data movement problem with excellent power efficiency. However, previous PIM accelerators cannot support the entire training process on chip due to its computing complexity. This article presents a PIM accelerator for end-to-end on-device training (T-PIM), the first PIM realization that enables end-to-end on-device training as well as high-speed inference. Its full-custom PIM macro contains 8T-SRAM cells to perform the energy-efficient in-cell AND operation and the bit-serial-based computation logic enables fully variable bit-precision for input data. The macro supports various data mapping methods and computational paths for both fully connected and convolutional layers, in order to handle the complex training process. An efficient tiling scheme is also proposed to enable T-PIM to compute any size of deep neural network with the implemented hardware. In addition, configurable arithmetic units in a forward propagation path make T-PIM handle power-of-two bit-precision for weight data, enabling a significant performance boost during inference. Finally, T-PIM efficiently handles sparsity in both operands by skipping the computation of zeros in the input data and by gating-off computing units when the weight data are zero. Finally, we fabricate the T-PIM chip in 28-nm CMOS technology, occupying a die area of 5.04 mm2, including five T-PIM cores. It dissipates 5.25–51.23 mW at 50–280 MHz operating frequency with 0.75–1.05-V supply voltage. We successfully demonstrate that T-PIM can run the end-to-end training of VGG16 model on the CIFAR10 and CIFAR100 datasets, achieving 0.13–161.08- and 0.25–7.59-TOPS/W power efficiency during inference and training, respectively. The result shows that T-PIM is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.02\times $ </tex-math></inline-formula> more energy-efficient than the state-of-the-art PIM chip that only supports backward propagation, not a whole training. Furthermore, we conduct an architectural experiment using a cycle-level simulator based on actual measurement results, which suggests that the T-PIM architecture is scalable and its scaled-up version provides up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$203.26\times $ </tex-math></inline-formula> higher power efficiency than a comparable GPU.

An 8-bit integer true periodic orbit PRNG based on delayed Arnold’s cat map

Designing a pseudo-random number generator (PRNG) exhibiting true periodic orbits with large periods is promising for embedded applications. Implementing chaotic behaviors on a finite precision digital platform using conventional unsigned integer or floating-point arithmetic yields short period limit-cycles. It leads the output to diverge from the true chaotic orbits. This paper presents an unsigned integer encoded PRNG based on the delayed quantized Arnold’s Cat Map (QACM) that exhibits true periodic orbits with large periods. The proposed PRNG is obtained by delaying one of the 2-D QACM outputs with a linear feedback shift register (LFSR) thereby increasing its period. By investigating its period, we show that the periodicity increases with an increase in the delay and bit-precision. We also present the proposed PRNG unit’s hardware architecture and its synthesis results targeting on a Xilinx Zynq 7000 Field Programmable Gate Array (FPGA) with 8-bit precision and delay δ=58. Further, we synthesize the design using 90 nm CMOS technology for ASIC realization. The synthesis results demonstrate the throughput as 2.208 Gbps and 5.46 Gbps at 138 MHz and 342 MHz operating frequency on FPGA and ASIC respectively. We experimentally evaluate the performance of random numbers using the NIST 800-22-1 tests along with the correlation and key sensitivity tests.

Single-electron pump in a quantum dot array for silicon quantum computers

It is necessary to load single electrons into individual quantum dots (QDs) in an array for implementing fully scalable silicon-based quantum computers. However, this single-electron loading would be impacted by the variability of the QD characteristics, and suppressing this variability is highly challenging even in the state-of-the-art silicon front-end process. Here, we used a single-electron pump (SEP) for loading single electrons into a QD array as a preparatory step to use electrons as spin qubits. We used parallel gates in the QD array as a SEP and demonstrated 100 MHz operation with an accuracy of 99% at 4 K. By controlling the timing of a subsequent gate synchronously as a shutter, we found that the jitter representing electron transfer was less than 10 ns, which would be acceptable for a typical operating speed of around 1 MHz for silicon qubits.