Accelerating deep convolutional neural network on FPGA for ECG signal classification

Abstract

Abnormal activity of the heart is known as cardiac arrhythmia which must be recognized in earlier stage to prevent sudden death and premature death. The occurrence of arrhythmia increases with age, and it is detected using an electrocardiogram (ECG) signal. Conversely, it is very complex to manually achieve the quick and exact classification due to the complexity, non-linearity and low amplitude of the ECG signal. As a result, the healthcare field requires an automatic system to recognize abnormal heartbeats from a huge amount of ECG records. So, the deep learning algorithm named as Deep Convolutional Neural Network (DCNN) is proposed in this research to analyze the ECG signal on a field-programmable gate array (FPGA). Before performing a classification process, two different processes called signal pre-processing as well as feature extraction are required. For the process of signal pre-processing, the Error Normalised Least Mean Square (ENLMS) algorithm is utilized in our work, and Discrete Wavelet Transform (DWT) technique is performed to take out the relevant features from the ECG signal. Finally, FPGA based one-dimensional DCNN with 3 convolutional layers, 3 pooling layers, and 3 fully connected layers is proposed to classify the signals with proper complex features. The publicly available MIT-BIH arrhythmia and PTB databases are exploited in this research to process ECG signals on the multi-input structure. In addition, different performance parameters like classification accuracy, specificity, sensitivity, and precision are engaged to evaluate the proposed methodology; also, it is compared with different FPGA based existing classifiers. The analysis shows that the proposed design accomplishes 98.6 % classification accuracy on the MIT-BIH arrhythmia database and 99.67 % accuracy on the PTB database, which is 0.304 % higher than a multilayer perception (MLP) and 0.47 % higher than decision-based classifier. Moreover, the proposed FPGA based DCNN accelerator consumes 0.45 mW, 185.426 MHz operation frequency and takes 15 s to complete the classification process.