MHz Maximum Frequency Research Articles

Hardware Architecture for Realtime HEVC Intra Prediction

Researchers have, in recent times, achieved excellent compression efficiency by implementing a more complicated compression algorithm due to the rapid development of video compression. As a result, the next model of video compression, High-Efficiency Video Coding (HEVC), provides high-quality video output while requiring less bandwidth. However, implementing the intra-prediction technique in HEVC requires significant processing complexity. This research provides a completely pipelined hardware architecture solution capable of real-time compression to minimize computing complexity. All prediction unit sizes of 4×4, 8×8, 16×16, and 32×32, and all planar, angular, and DC modes are supported by the proposed solution. The synthesis results mapped to Xilinx Virtex 7 reveal that our solution can do real-time output with 210 frames per second (FPS) at 1920×1080 resolution, called Full High Definition (FHD), or 52 FPS at 3840×2160 resolution, called 4K, while operating at 232 Mhz maximum frequency.

On the implementation of large period piece-wise linear Arnold cat map

This paper presents a piece-wise linear cat map (PWLCM) obtained by perturbing the conventional quantized Arnold cat map (QACM) with a nonlinear term. The effect of the nonlinear term on the dynamics of the QACM is investigated. We show that the eigenvalues, hence the Lyapunov exponents of the PWLCM depend on the initial conditions, which is not the case for the QACM. As a result, the proposed PWLCM is a generalized form of the QACM, whose the period exponentially increases with respect to the precision, thus taking as value 1.09 × 10513 for only 10-bit precision; while that of the corresponding QACM is only 768. The nonlinear term increases the sensitivity of the system to the initial conditions, which contributes to increase its period, hence to enhance its complexity. An electronic implementation of both the QACM and the PWLCM in the case of 4-bit precision using Multisim is presented. The proposed architecture of both the QACM and the PWLCM are implemented using Verilog and prototyped on the Zynq 7020 FPGA board. For 4-bit precision, the FPGA implementation performs 1.072 Gbps throughput at 134 MHz maximum frequency. We verified that experimental and simulation behaviors of the proposed system perfectly match, thus confirming the effectiveness of the proposed electronic circuit for exhibiting the expected dynamics in real-time.

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Applications, such as Internet of Things, deal with huge amount of transmitted, processed and stored images that required a high computing capability. Therefore, there is a need a computing architecture that contribute in increasing the throughput by exploiting modern technologies in both spatial and temporal parallelisms. This paper conducts a parallel quad-engine cybersecurity architecture with new configuration to increase the throughput. using DE1-SoC and Neek FPGA boards and HDL. In this architecture, each engine operates with 600MHz maximum frequency. Each image is divided into four parts of equal size and each part processed by single engine concurrently to achieve spatial parallelism. Internally, engine is handling image’s part in temporal parallelism and deep pipelining abstraction applied in every engine by dividing it to sub modules to execute different tasks concurrently. All data processed in engines is encrypted via AES algorithm that implemented as a significant part of engine architecture. The obtained results increased the throughput by four times, with 153,600Mbps, that make this computing architecture efficient and suitable for fast applications such as IoT and cybersecurity level of processing.

Needles and Lightning Leader Dynamics Imaged with 100–200 MHz Broadband VHF Interferometry

AbstractA new short‐baseline VHF interferometer with 200 MHz bandwidth images lightning with significantly higher spatial resolution than our previous system with a 60 MHz maximum frequency. Needles (Hare et al., 2019, https://doi.org/10.1038/s41586‐019‐1086‐6), needle‐associated negative leaders, a nearby bidirectional leader, and their interactions were imaged during an intracloud lightning flash. Six recoil leaders traversing the positive leader channel definitively determined the leader path and verified that needles originate from positive channels. Two negative leaders initiated from the positive channel, either from or close to needles, when another active positive leader passed ~1 km away. While the needles develop continuously with a VHF source density decreasing from the front end to the back end, a bidirectional leader initiated nearby and had strong influence on subsequent needle dynamics. These rarely observed yet perhaps common lightning processes are analyzed comprehensively to give new insight into the origin and impact of needles on positive lightning leaders.

Design and Implementation of a Reconfigurable Cryptographic Coprocessor with Multiple Side-Channel Attacks Countermeasures

Nowadays, countermeasures against side-channel attack (SCA) have become necessary in hardware security. And the need for supporting multiple crypto algorithms on a chip is increasing. We propose a reconfigurable crypto coprocessor, which not only supports multiple crypto algorithms, but also provides multiple effective SCA countermeasures of SPA, DPA and EMA, by making use of its own reconfigurable features other than using extra resources. The countermeasure methods include several global and encryption flow related countermeasures, which can also be reconfigured along with the circuit function. This coprocessor is a coarse-grained reconfigurable architecture composed of several reconfigurable modules, such as logic arithmetic, shift, modular ADD/Substrate, permutation, S-box and modular multiplication units, all of which are reconfigurable. This reconfigurable cryptographic coprocessor is integrated into a system-on chip with a 32-bit CPU and fabricated in 0.18 m CMOS process with 1.8[Formula: see text]V supply and 100 MHz maximum frequency. Experimental results show that it can successfully resist SPA and DPA with one million power traces. As for EMA, if we use full countermeasures, it can resist EMA with up to 1.2 million electromagnetic traces without revealing the right subkey. Thus, this reconfigurable coprocessor can provide a good solution for both supporting multiple algorithms and providing SCA resistance, with no frequency influence, neglectable area overhead and small power overhead.

An efficient floating-point FFT twiddle factor implementation based on adaptive angle recoding CORDIC algorithm

In this paper, a single-precision floating-point FFT twiddle factor (TF) implementation is proposed. The architecture is based on the Adaptive Angle Recoding CORDIC (AARC) algorithm. The TF design was built and verified on Altera Stratix IV FPGA chip and 65nm SOTB synthesis. The FPGA implementation had 103.9 MHz maximum frequency, throughput result of 16.966 Mega-Sample per second (MSps), and resources utilization of 7.747 ALUTs and 625 registers. On the other hand, the SOTB synthesis has 16.858 standard cells on an area of 298x291 μm2, 166 MHz maximum frequency, and the speed of 27.107 MSps. The accuracy results were 1.133E-10 Mean-Square-Error (MSE) and about 26 part-per-million (ppm) maximum error.

An FPGA-based single-precision floating-point 2048-points FFT implementation based on adaptive angle recoding CORDIC

In this paper, an FPGA-based single-precision floating-point 2048-point FFT implementation is proposed, based on an adaptive angle recoding CORDIC algorithm. The design is built and verified on Altera Stratix V FPGA chip. The implementation had 102.55 MHz maximum frequency, throughput result of 8424.382 FFTs/s, and resources utilization of 76,282 ALUTs and 15,687 registers. The accuracy results were 5.889E-06 (Mean-Square-Error (MSE).

Implementation of Layered Decoding Architecture for LDPC Code using Layered Min-Sum Algorithm

For binary field and long code lengths, Low Density Parity Check (LDPC) code approaches Shannon limit performance. LDPC codes provide remarkable error correction performance and therefore enlarge the design space for communication systems.In this paper, we have compare different digital modulation techniques and found that BPSK modulation technique is better than other modulation techniques in terms of BER. It also gives error performance of LDPC decoder over AWGN channel using Min-Sum algorithm. VLSI Architecture is proposed which uses the value re-use property of min-sum algorithm and gives high throughput. The proposed work has been implemented and tested on Xilinx Virtex 5 FPGA. The MATLAB result of LDPC decoder for low bit error rate (BER) gives bit error rate in the range of 10-1 to 10-3.5 at SNR=1 to 2 for 20 no of iterations. So it gives good bit error rate performance. The latency of the parallel design of LDPC decoder has also reduced. It has accomplished 141.22 MHz maximum frequency and throughput of 2.02 Gbps while consuming less area of the design.

Real-time Architecture and FPGA Implementation of Adaptive General Spectral Substraction Method

Spectral Subtraction (SS) method is one method for speech enhancement or noise cancellation. There are many variations of SS method, one of them is Adaptive General Spectral Subtraction (AGSS). In this paper, we implement the noise cancellation method in FPGA as hardware to perform real-time speech enhancement. The hardware implementation consists of FIFO block, window block, FFT/IFFT block, noise cancellation block, half overlap block, and hardware buffer block. Our hardware design utilizes 5086 logic elements with additional 2.18kB memory in total. Latency of the hardware is 2.48 μs in 217 clock cycles with 87.54 MHz maximum frequency. The latency is less than the sampling period which is 125 μs, so it can perform real-time speech enhancement, as have been tested in Altera DE2-70 board.

Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

This paper proposes a novel sub-architecture to optimize the data flow of REMUS-II (REconfigurable MUltimedia System 2), a dynamically coarse grain reconfigurable architecture. REMUS-II consists of a µPU (Micro-Processor Unit) and two RPUs (Reconfigurable Processor Unit), which are used to speeds up control-intensive tasks and data-intensive tasks respectively. The parallel computing capability and flexibility of REMUS-II makes itself an excellent candidate to process multimedia applications, which require a large amount of memory accesses. In this paper, we specifically optimize the data flow to deal with those performance-hazard and energy-hungry memory accessing in order to meet the bandwidth requirement of parallel computing. The RPU internal memory could work in multiple modes, like 2D-access mode and transformation mode, according to different multimedia access patterns. This novel design can improve the performance up to 26% compared to traditional on-chip memory. Meanwhile, the block buffer is implemented to optimize the off-chip data flow through reducing off-chip memory accesses, which reducing up to 43% compared to direct DDR access. Based on RTL simulation, REMUS-II can achieve 1080p@30fps of H.264 High Profile@ Level 4 and High Level MPEG2 at 200MHz clock frequency. The REMUS-II is implemented into 23.7mm2 silicon on TSMC 65nm logic process with a 400MHz maximum working frequency.

The Development of Nanosecond Pulse Power Supply of Electrochemical Micromachining

This paper makes some research on designing and manufacturing a nanosecond pulse power supply of electrochemical micromachining, including DC power supply, waveform generation circuit, rectifier and filter circuit，power amplification and rapid protection circuit. This power supply can generate 5MHz maximum frequency and square wave of 100ns pulse width, stably. The voltage ranges from 0V to 10V, and duty ratio ranges from 0.1 to 0.5, continuously.