Abstract
Applications, such as Internet of Things, deal with huge amount of transmitted, processed and stored images that required a high computing capability. Therefore, there is a need a computing architecture that contribute in increasing the throughput by exploiting modern technologies in both spatial and temporal parallelisms. This paper conducts a parallel quad-engine cybersecurity architecture with new configuration to increase the throughput. using DE1-SoC and Neek FPGA boards and HDL. In this architecture, each engine operates with 600MHz maximum frequency. Each image is divided into four parts of equal size and each part processed by single engine concurrently to achieve spatial parallelism. Internally, engine is handling image’s part in temporal parallelism and deep pipelining abstraction applied in every engine by dividing it to sub modules to execute different tasks concurrently. All data processed in engines is encrypted via AES algorithm that implemented as a significant part of engine architecture. The obtained results increased the throughput by four times, with 153,600Mbps, that make this computing architecture efficient and suitable for fast applications such as IoT and cybersecurity level of processing.
Highlights
Data processing and transfer and store have grown dramatically in the last year because they are used in different applications via different communication networks. This growth requires an exploitation of modern technologies to enhance and increase this processing in a parallelism manner to achieve high throughput
This paper focuses on hardware architecture implementation on field- programmable gate arrays (FPGAs) that based on true spatial and temporal parallelism using quad engines for cybersecurity
In [18], Rahimunnisa et al the proposed structure is implemented in a Virtex-6 XC6VLX75T FPGA device, which gave a throughput of 37.1 Gb/s with a maximum frequency of 505.5 MHz in [19], Groth implemented AES encryption on a Xilinx Kintex27 FPGA for application data of the biometric image
Summary
Data processing and transfer and store have grown dramatically in the last year because they are used in different applications via different communication networks This growth requires an exploitation of modern technologies to enhance and increase this processing in a parallelism manner to achieve high throughput. To obtain faster and more efficient computation power to encrypt massive data with high throughput, the AES algorithm must be implemented in a parallel manner. This paper focuses on hardware architecture implementation on FPGA that based on true spatial and temporal parallelism using quad engines for cybersecurity. This architecture works through partition each image into four parts and distributes these parts to multiple engines that can process data in temporal and spatial parallelism the image parts concurrently.
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