Design Space Exploration Method Research Articles

Hybrid Evolutionary Design Space Exploration Algorithm With Defence Against Third Party IP Vulnerabilities

With the globalization of the semiconductor industry, the supply chain is fragmented across geographies, which has resulted in the importing of third-party IP cores in designs. Such third party IP cores have increased concerns about hardware Trojans. To address such concerns, development of an effective Trojan detection methodology is crucial. In this article, we present a low-cost Trojan detection and activation prevention mechanism for high level synthesis. In particular, a particle swarm optimization-based design space exploration method is proposed which is combined with a Trojan detection mechanism to minimize resource requirements. Additionally, a hybrid evolutionary algorithm-based Trojan detection method is formed with a novel vendor allocation procedure to find low-cost solutions. The proposed algorithm is compared with existing methods-based on Pareto and non-Pareto-based evaluations to verify their efficiency. From the experiment results, it has been verified that the proposed algorithm offers defence against Trojans similar to existing algorithms with less hardware overhead.

A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders

A cross-layer design space exploration (DSE) method based on a proposed co-simulation technique is presented herein. The proposed method is demonstrated evaluating the impacts on both coding efficiency and power dissipation of applying distinct approximate logic operators in a s $\mu {\mathrm{ m}}$ of absolute differences (SAD) kernel that accelerates an H.265/HEVC (high-efficiency video coding) encoder. The proposed method simulates the gate-level circuit dynamically inside the application, with realistic results of the impact of the adder-tree approximate logic implementation on both quality and encoder bit-rate results. A comprehensive DSE is shown herein, with 13 types of 6 classes of approximate adders in the SAD accelerator hardware blocks. Over 3,000 logic variants of approximations at gate-level were developed. Actual video sequences as inputs to the x265 software encoder are co-simulated, to dynamically capture the video motion-estimation (ME) behavior in the presence of logic approximations. While the prior art that only estimates the impact of the approximate logic on power, area, and quality on static designs with statistical assumptions, which are agnostic to the actual algorithm data-dependent behavior in the application, our method explores accurately the trade-off between power dissipation and coding efficiency dynamically over the entire HEVC encoding. Our approach shows that the lower-part-or and error-tolerant adder I approximate adders, as well as truncation-to-zero deliver better compression-power trade-offs, with substantial differences from the static analysis.

Cartonist: Automatic Synthesis and Interactive Exploration of Nonstandard Carton Design

Cartons are commonly used in the packaging industry, and standard carton patterns are broadly used in mass production. However, their designs may not fit different containees or specific fabrication requirements well. Taking the dimensions of the containees as input, we study the patterns of cartons and propose a system named “Cartonist” to efficiently explore the pattern variations. A synthesis algorithm is proposed to create a space of nonstandard carton patterns, based on which a design space exploration method is demonstrated. Cartonist enables a user to customize the design of carton patterns for different applications, considering design criteria such as material efficiency, folding ease and stability. We perform a user study to evaluate the effectiveness of our proposed system for carton design.

Toward Efficient Design Space Exploration for Fault-Tolerant Multiprocessor Systems

The design space exploration (DSE) of fault-tolerant multiprocessor systems is very complex, as it contains three interacting NP-hard problems: 1) task hardening; 2) task mapping; and 3) task scheduling. In addition, replication-based task hardening can introduce new tasks, called replicas, into the system, enlarging the design space further. As a population-based global optimization algorithm, evolutionary algorithms (EAs) have been widely used to explore this huge design space over the last decade. However, as analyzed in this paper, the search space of previous works is highly redundant, resulting in poor efficiency and scalability. This paper proposes an efficient EA-based DSE method for the design of large-scale fault-tolerant multiprocessor systems. The main novelties of this paper include: 1) mapping exploration is explicitly separated, i.e., task mapping is optimized during the evolutionary search, while replica mapping is constructed heuristically according to the current co-synthesis state; 2) the design space of task hardening and task mapping are explored independently by a cooperative co-EA; and 3) as a complement to global search of EA, problem-specific local search operators are designed for both task hardening and task mapping, reducing the number of fitness evaluations required. Compared with the most relevant state-of-the-art method, the superiority of the proposed method is demonstrated using extensive experiments on a large set of benchmarks, e.g., $1.75\times \sim 2.50\times $ better results can be obtained on the benchmarks of 300 tasks and 30 processors.

Security/Timing-Aware Design Space Exploration of CAN FD for Automotive Cyber-Physical Systems

The controller area network with flexible data-rate (CAN FD) is the new generation of the CAN technology to meet the daily increasing bandwidth requirement for automotive cyber-physical systems (ACPS). However, ACPS is a security-critical system, an efficient security/timing-aware design space exploration (DSE) method is required to fully utilize CAN FD's high data phase data rate. In this paper, we propose an AUTOSAR-compliant system model that integrates both timing and security constraint, an integrated mixed-integer linear programming formulation (i-MILP) for the optimal DSE of CAN FD, and a divide-and-conquer approach to the i-MILP (dc-MILP) to address its timing complexity problem. The experiment results show that dc-MILP scales well for industrial-size systems and saves 1.94%–4.76% bandwidth utilization and guarantees the schedulability for more signal sets by comparing with the state-of-the-art algorithm.

Hybrid meta-model-based design space exploration method for expensive problems

Multiple meta-models used together in the search process at least can offer an insurance against the poorly fitted meta-models and can improve robustness of the predictions, compared with the single meta-model based methods. In this work, a hybrid meta-model-based design space exploration (HMDSE) method is proposed. In the proposed method, a part of the current expensive points which are evaluated by the expensive problems to be solved are used firstly to construct a so-called important region. And then, three representative meta-models, kriging, radial basis functions (RBF), and quadratic function (QF), are used in the search of the obtained important region. To avoid the local minima, the remaining region will be searched simultaneously. In addition, the whole design space will also be searched to further demonstrate the global optimum. Through test by six benchmark math functions with design variables ranging from 10 to 24, the proposed HMDSE method shows great accuracy, efficiency, and robustness compared with the efficient global optimization (EGO). Then, it is applied in a practical vehicle lightweight design problem with 30 design variables, achieving desired results.

Toolflows for Mapping Convolutional Neural Networks on FPGAs

In the past decade, Convolutional Neural Networks (CNNs) have demonstrated state-of-the-art performance in various Artificial Intelligence tasks. To accelerate the experimentation and development of CNNs, several software frameworks have been released, primarily targeting power-hungry CPUs and GPUs. In this context, reconfigurable hardware in the form of FPGAs constitutes a potential alternative platform that can be integrated in the existing deep-learning ecosystem to provide a tunable balance between performance, power consumption, and programmability. In this article, a survey of the existing CNN-to-FPGA toolflows is presented, comprising a comparative study of their key characteristics, which include the supported applications, architectural choices, design space exploration methods, and achieved performance. Moreover, major challenges and objectives introduced by the latest trends in CNN algorithmic research are identified and presented. Finally, a uniform evaluation methodology is proposed, aiming at the comprehensive, complete, and in-depth evaluation of CNN-to-FPGA toolflows.

Systematic design space exploration using a template-based ontological method

The realization of complex engineered systems using models that are typically incomplete, inaccurate and not of equal fidelity requires the understanding and prediction of process behavior in design. This necessitates the need for extending designer’s abilities in making design decisions that are robust, flexible and modifiable particularly in the early stages of design. To address this requirement, we propose in this paper, an ontology for design space exploration and a template-based ontological method that supports systematic design space exploration ensuring the determination of the right combination of design information that meets the different goals and requirements set for a process chain. Using the proposed method, a designer is able to (1) systematically adjust the design space in due time to manage the risks of errors accumulating and propagating during the design of different stages of the process chain, (2) improve the ability to communicate and understand the interactions between design information in the process chain. We achieve the said through (1) procedure for design space exploration is identified to determine the sequence of activities needed for the systematic exploration of design space under uncertainty; (2) the decision-based design information flow is archived using the design space exploration process template and represented by utilizing frame-based ontology to facilitate the management of re-usable information. We demonstrate the efficacy of this template-based ontological method for design space exploration by carrying out the design of a multi-stage hot rod rolling system in steel manufacturing process chain.

Processor Design Space Exploration via Statistical Sampling and Semi-Supervised Ensemble Learning

The design space exploration (DSE) has become a major challenge in microprocessors design due to the increasing complexity of microprocessor architecture and the extremely time-consuming software simulation technology. To more effectively and efficiently perform DSE, recently machine learning techniques are widely explored to build predictive models with a small set of simulations. However, most previous models are supervised models and the training samples are randomly selected. Thus they still suffered from high simulation cost or low prediction accuracy. In order to minimize the simulation overhead for DSE, this paper proposes an efficient DSE method which combines Latin hypercube sampling and semi-supervised ensemble learning technique. Latin hypercube sampling is first employed to select a small set of representative design points for simulation. Then a semi-supervised learning based AdaBoost model (SemiBoost) is proposed to predict the responses of the configurations that have not been simulated. We conduct extensive evaluations on the benchmarks of SPEC CPU2006 suite, and the experimental results demonstrate that the proposed SemiBoost model is superior to existing state-of-the-art models in terms of both efficiency and effectiveness.

Civil turbofan engine exhaust aerodynamics: Impact of bypass nozzle after-body design

It is envisaged that the next generation of civil large turbofan engines will be designed for greater bypass ratios when compared to contemporary architectures. The underlying motivation is to reduce specific thrust and improve propulsive efficiency. Concurrently, the aerodynamic performance of the exhaust system is anticipated to play a key role in the success of future engine architectures. The transonic flow topology downstream of the bypass nozzle can be significantly influenced by the after-body geometry. This behavior is further complicated by the existence of the air-flow vent on the nozzle after-body which can have an impact on the performance of the exhaust system. This paper aims to investigate the aerodynamics associated with the geometry of the bypass nozzle after-body and to establish guidelines for the design of separate-jet exhausts with respect to future large turbofan engines. A parametric geometry definition has been derived based on Class-Shape Transformation (CST) functions for the representation of post-nozzle-exit components such as after-bodies, plugs, and air-flow vents. The developed method has been coupled with an automatic mesh generation and a Reynolds Averaged Navier–Stokes (RANS) flow solution method, thus devising an integrated aerodynamic design tool. A cost-effective optimization strategy has been implemented consisting of methods for Design Space Exploration (DSE), Response Surface Modeling (RSM), and Genetic Algorithms (GAs).The combined approach has been deployed to explore the aerodynamic design space associated with the bypass nozzle after-body geometry for a Very High Bypass Ratio (VHBR) turbofan engine with separate-jet exhausts. A detailed investigation has been carried out to expose the transonic flow mechanisms associated with the effect of after-body curvature combined with the impact of the air-flow vent. A set of optimum curved after-body geometries has been obtained, with each subsequently compared against their respective conical representation. The obtained results suggest that no significant performance improvements can be obtained through curving the nozzle after-body relative to the case of a conical design. However, it is shown that the application of surface curvature has the potential to unlock new parts in the design space that allow analysts to reduce the required after-body length without any loss in aerodynamic performance. The developed approach complements the existing tool-set of enabling technologies for the design and optimization of future large aero-engines, consequently leading to increased thrust and reduced Specific Fuel Consumption (SFC).

Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies

This works presents a Design Space Exploration (DSE) method for Behavioral IPs (BIPs) given in ANSI-C or SystemC to find the smallest micro-architecture for a specific target latency. Previous work on High-Level Synthesis (HLS) DSE mainly focused on finding a tradeoff curve with Pareto-optimal designs. HLS is, however, a single process (component) synthesis method. Very often, the latency of the components requires a specific fixed latency when inserted within a larger system. This work presents a fast multi-threaded method to find the smallest micro-architecture for a given BIP and target latency by discriminating between all different exploration knobs and exploring these concurrently. Experimental results show that our proposed method is very effective and comprehensive results compare the quality of results vs. the speedup of your proposed explorer.

Energy Provision and Storage for Pervasive Computing

Soon, pervasive computers will enormously outnumber humans. Devices requiring sufficient energy to operate maintenance-free for periods of years and beyond render today's technologies insufficient. With the gap between energy requirements of embedded systems and achievable levels of harvested power reducing, viable hybrid energy and power management subsystems have emerged that combine harvesting with finite, rechargeable energy buffers. Coupled with advances in wireless power transfer and energy storage, the authors suggest that an energy design space is emerging. There are, as yet, no tools or systematic methods for design space exploration or engineering in this context. It's important to develop such a methodology, and critical to link it with methodologies for system design and verification. The authors discuss key factors such an energy design methodology should incorporate, including size, weight, energy and power densities; mobility; efficiencies of harvesters and buffers; time between charges, (dis)charge speeds, and charge cycles; and availability and predictability of harvestable energy. This article is part of a special issue on energy harvesting.

Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures

Abstract As embedded systems have evolved to appear in many different domains, symmetric multiprocessing (SMP) has been the design choice from low-end to high-end devices. In this paper we present Prenaut, a design space exploration method for finding the best on-chip SMP architectures given processor cores, Level 1, Level 2, and Level 3 caches. Unlike traditional design space exploration tools that are majorly concerned with optimizations in processor, memory and cache structures with a fixed on-chip architecture, Prenaut explores architectures that have not been considered in symmetric multiprocessing domain. These architectures consist of shared instruction caches between cores and heterogeneous cache topologies that feature bypassing a level in the cache hierarchy. The design idea behind Prenaut is to build a data oriented design space exploration method that exploits simulation data to its full extent rather than discarding it. Therefore, Prenaut uses simulation data and applies machine learning methods for estimating design parameters. This provides very rapid estimation of the Pareto set and guides designers through the overall system design process. The design space is pruned by topological clustering of design points which groups similar topologies and new simulation points are selected via an ordered look up table that prevents infeasible random jumps in the design space. For the selected benchmarks, Prenaut can estimate the Pareto set up to 147x faster and the clustering information can reduce the design space up to 82% in comparison with a state-of-the-art evolutionary algorithm.

Aerodynamic Design of Separate-Jet Exhausts for Future Civil Aero-engines—Part I: Parametric Geometry Definition and Computational Fluid Dynamics Approach

This paper presents the development of an integrated approach which targets the aerodynamic design of separate-jet exhaust systems for future gas-turbine aero-engines. The proposed framework comprises a series of fundamental modeling theories which are applicable to engine performance simulation, parametric geometry definition, viscous/compressible flow solution, and design space exploration (DSE). A mathematical method has been developed based on class-shape transformation (CST) functions for the geometric design of axisymmetric engines with separate-jet exhausts. Design is carried out based on a set of standard nozzle design parameters along with the flow capacities established from zero-dimensional (0D) cycle analysis. The developed approach has been coupled with an automatic mesh generation and a Reynolds averaged Navier–Stokes (RANS) flow-field solution method, thus forming a complete aerodynamic design tool for separate-jet exhaust systems. The employed aerodynamic method has initially been validated against experimental measurements conducted on a small-scale turbine powered simulator (TPS) nacelle. The developed tool has been subsequently coupled with a comprehensive DSE method based on Latin-hypercube sampling. The overall framework has been deployed to investigate the design space of two civil aero-engines with separate-jet exhausts, representative of current and future architectures, respectively. The inter-relationship between the exhaust systems' thrust and discharge coefficients has been thoroughly quantified. The dominant design variables that affect the aerodynamic performance of both investigated exhaust systems have been determined. A comparative evaluation has been carried out between the optimum exhaust design subdomains established for each engine. The proposed method enables the aerodynamic design of separate-jet exhaust systems for a designated engine cycle, using only a limited set of intuitive design variables. Furthermore, it enables the quantification and correlation of the aerodynamic behavior of separate-jet exhaust systems for designated civil aero-engine architectures. Therefore, it constitutes an enabling technology toward the identification of the fundamental aerodynamic mechanisms that govern the exhaust system performance for a user-specified engine cycle.

Multi-objective optimization of multimedia embedded systems using genetic algorithms and stochastic simulation

To meet the ever shrinking time-to-market for multimedia embedded systems, designers need effective system-level optimization techniques to support their design decisions. Despite multimedia embedded systems' highly variable execution times and soft real-time constraints, most previous work has adopted a constant execution time (worst-case) approach to evaluate if a candidate architecture satisfies the timing constraints. Such an approach is too pessimistic and might result in unnecessary costly architectures. In this work, we propose a new method for design space exploration of multimedia embedded systems. Given a system specification, the proposed method automatically explores the design space to quickly identify Pareto-optimal solutions (or an approximation) that optimize conflicting design metrics, such as price and power consumption. Our approach combines (i) a fast and formal strategy for performance evaluation that captures the varying runtime behavior of multimedia systems and (ii) a new multi-objective genetic algorithm for architecture exploration. The experiments on well-known benchmarks show the efficiency of our method in comparison to similar ones.

Methodology and Tools for Next Generation Cyber‐Physical Systems: The iCyPhy Approach

AbstractThe realization of complex, cyber‐physical “systems of systems” can substantially benefit from model‐based hierarchical and compositional methodologies to make their design possible let alone optimal. In this paper, we introduce the methodology being developed within the industrial Cyber‐Physical (iCyPhy) research consortium, which addresses the complexity and heterogeneity of cyber‐physical systems by formalizing the design process in a hierarchical and compositional way, and provides a unifying framework where different modeling, analysis and synthesis tools can seamlessly interconnect. We use assume‐guarantee contracts and their algebra (e.g. composition, conjunction, refinement) to provide formal support to the entire design flow. The design is carried out as a sequence of refinement steps from a high‐level specification (top‐down phase) to an implementation built out of a library of components at the lower level (bottom‐up phase). At each step, the design is refined by combining synthesis from requirements, optimization and simulation‐based design space exploration methods. We illustrate our approach on design examples of embedded controllers for aircraft power distribution and air management systems.

Formal Vulnerability Analysis of Security Components

Vulnerability to malicious fault attacks is an emerging concern for hardware circuits that are employed in mobile and embedded systems and process sensitive data. We describe a new methodology to assess the vulnerability of a circuit to such attacks, taking into account built-in protection mechanisms. Our method is based on accurate modeling of fault effects and detection status expressed by Boolean satisfiability (SAT) formulas. Vulnerability is quantified based on the number of solutions of these formulas, which are determined by an efficient #SAT solver. We demonstrate the applicability of this method for design space exploration of a pseudo random number generator and for calculating the attack success rate in a multiplier circuit protected by robust error-detecting codes.

GPU Performance and Power Tuning Using Regression Trees

GPU performance and power tuning is difficult, requiring extensive user expertise and time-consuming trial and error. To accelerate design tuning, statistical design space exploration methods have been proposed. This article presents Starchart, a novel design space partitioning tool that uses regression trees to approach GPU tuning problems. Improving on prior work, Starchart offers more automation in identifying key design trade-offs and models design subspaces with distinctly different behaviors. Starchart achieves good model accuracy using very few random samples: less than 0.3% of a given design space; iterative sampling can more quickly target subspaces of interest.

A Design Space Exploration Method Using Artificial Neural Networks and Metamodeling

This paper suggests a design space exploration method using Artificial Neural Networks and metamodeling to systematically reduce the design space to a relatively small region. This method consists of three major steps. Firstly, self-organizing maps is employed to analyze design variables and objective function(s) with the original samples as preliminary reduction optimization of the initial large design space. Successively, resampling within the preliminary reduction space, clustering sample points using the fuzzy c-means clustering method with the given number of cluster, and choosing the most attractive cluster to construct kriging model and identify the design optimum within the reduced design space in the last step. The accuracy and validity of proposed methodology is proved by a heat exchanger design problem. It is found that the proposed method can intuitively capture promising design regions in which it is efficient to acquire the global or near-global desigm optimum.

Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design

High level synthesis has now almost become an industry de facto standard for designing Application Specific Processors (ASPs) and Application Specific Integrated Circuits (ASICs). High level synthesis (HLS) designing requires an efficient exploration approach with the ability to determine optimal/near-optimal scheduling solutions and module selection with significant speed and precision. A novel exploration approach using the ‘S-value’ method that reduces the final power dissipation of the solution using minimal control step is presented in this paper. This approach is based on the proposed ‘Primacy Selector (S-value)’ metric and ‘Intersect Matrix’ topology methods that have a tendency to escape local optimal solutions and thereby reach global solutions. Two novel aspects discussed in this paper are: (a) introduction of ‘Intersect Matrix’ topology with its associated algorithm, which is used to check for precedence violation during scheduling, (b) introduction of S-value method metric, which assists in choosing the highest priority node during each iteration of the scheduling optimization process. Comparative analysis of the proposed approach is done with an existing design space exploration method for qualitative assessment using proposed ‘Quality Cost Factor (Q-metric)’. An average improvement of approximately 5.07% in quality of final scheduling solution and average reduction of 59% in exploration runtime has been achieved by the proposed approach compared to a current scheduling approach for the DSP benchmarks.