Metal/interlayer/semiconductor Research Articles

Design and Optimization of Potentially Low-Cost and Efficient MXene/InP Schottky Barrier Solar Cells via Numerical Modeling

This paper uses numerical modeling to describe the design and comprehensive analysis of cost-effective MXene/n-InP Schottky barrier solar cells. The proposed design utilizes Ti3C2Tx thin film, a 2D solution-processible MXene material, as a Schottky transparent conductive electrode (TCE). The simulation results suggest that these devices can achieve power conversion efficiencies (PCEs) exceeding 20% in metal–semiconductor (MS) and metal–interlayer–semiconductor (MIS) structures. Combining the proposed structures with low-cost InP growth methods can reduce the gap between InP and other terrestrial market technologies. This is useful for specific applications that require lightweight and radiation-hard solar photovoltaics.

Modification of interface properties of Au/n-GaN Schottky junction by rare-earth oxide Nd2O3 as an interlayer and its microstructural characterization

We demonstrate the impact of rare-earth Nd2O3 interlayer on the electrical properties of Au/n-GaN Schottky junction (SJ), the Au/Nd2O3/n-type GaN metal/interlayer/semiconductor (MIS) junctions were prepared and characterized. X-ray diffraction (XRD) and transmission electron microscopy (TEM) techniques were employed to analyze the structural properties of the deposited Nd2O3 films on the n-GaN surface. Results confirmed that the Nd2O3 layer was formed on the n-GaN surface. The MIS junction electrical results are compared with the Au/n-GaN Schottky junction (SJ) results. Electrical outcomes demonstrated that the MIS junction revealed a good rectification behaviuor with a higher barrier height (BH) (0.66 eV) than the SJ (0.59 eV), which indicates the BH is manipulated by the Nd2O3 interlayer. The I–V, Cheung's, ΨS-V and α(V)–V plots were employed to derive BH and determined that values were similar to one another, demonstrating that the techniques used here are consistent and valid. The capacitance-frequency (C-f) and conductance-frequency (G-f) properties of SJ and MIS junction are assessed in the range of 1 kHz-1 MHz and results demonstrate that the capacitance and conductance are sturdily reliant on frequency. The estimated interface state density (NSS) of the MIS junction is less than the SJ which shows that the Nd2O3 interlayer was responsible to reduces the NSS. Results demonstrate that ohmic and space charge limited conduction mechanisms in the forward bias of the SJ and MIS junctions. Experimental outcomes established that the Schottky emission directs the reverse current in the SJ. Though, the Poole-Frenkel emission ruled reverse current in the lower bias, while the Schottky emission governs reverse current in the higher bias region of the MIS junction. Findings demonstrate that the Nd2O3 layer could be appropriate for the development of MIS/MOS devices.

Barrier Modification by Methyl Violet Organic Dye Molecules of Ag/P-Inp Structures

Abstract This work includes fabrication and electrical characterization of Metal/Interlayer/Semiconductor (MIS) structures with methyl violet organic film on p-InP wafer. Metal(Ag)/ Interlayer (methyl violet =MV)/Semiconductor(p-InP) MIS structure presents a rectifying contact behavior. The values of ideality factor (n) and barrier height (BH) for the Ag/MV/p-InP MIS diode by using the current-voltage (I-V) measurement have been extracted as 1.21 and 0.84 eV, respectively. It was seen that the BH value of 0.84 eV calculated for the Ag/MV/p-InP MIS structure was significantly higher than the value of 0.64 eV of Ag/p-InP control contact. This situation was ascribed to the fact that the MV organic interlayer increased the effective barrier height by influencing the space charge region of inorganic semiconductor. The values of diffusion potential and barrier height for the Ag/MV/p-InP MIS diode by using the capacitance-voltage (C-V) measurement have been extracted as 1.21 V and 0.84 eV, respectively. The interface-state density of the Ag/MV/p-InP structure was seen to change from 2.57×1013 eV-1cm-2 to 2.19×1012 eV-1cm-2.

Effective Schottky barrier height and interface trap density reduction engineering using 2-dimensional reduced graphene oxide interlayer for metal-interlayer-semiconductor contact structure

The contact resistance at the metal-semiconductor (MS) interface has become the foremost challenge to ensuring high performance in nanoelectronics as devices are scaled down. A metal-interlayer-semiconductor (MIS) contact structure is a promising technique for Fermi-level unpinning to overcome the issue of fundamental contact resistance. Herein, an MIS contact structure with a 2-dimensional reduced graphene oxide (rGO) interlayer is proposed as an effective source/drain contact structure. The demonstration of a metal-rGO-semiconductor MIS (rGO MIS) contact structure with different interlayer thicknesses indicated that the rGO interlayer with a thickness of a few nanometers significantly enhanced the reverse current density (JR) by ∼2.0 × 103 times compared to that of the MS contact. In addition, the effective Schottky barrier height was reduced from 0.576 to 0.205 eV. This drastic improvement is attributed to the unique properties of rGO, such as its wide band gap, electrical conductivity, and Van der Waals interface leading to a metal-induced gap state reduction, tunneling resistance lowering, and passivation effect when it is adopted as an interlayer of the MIS contact. This result demonstrates the promising potential of using rGO as an MIS interlayer, which will pave the way toward high-performance emerging nanoelectronic devices.

MoS2 Transistors with Low Schottky Barrier Contact by Optimizing the Interfacial Layer Thickness

Molybdenum disulfide (MoS2) has attracted great attention from researchers because of its large band gap, good mechanical toughness and stable physical properties; it has become the ideal material for the next-generation optoelectronic devices. However, the large Schottky barrier height (ΦB) and contact resistance are obstacles hampering the fabrication of high-power MoS2 transistors. The electronic transport characteristics of MoS2 transistors with two different contact structures are investigated in detail, including a copper (Cu) metal–MoS2 channel and copper (Cu) metal–TiO2-MoS2 channel. Contact optimization is conducted by adjusting the thickness of the TiO2 interlayer between the metal and MoS2. The metal-interlayer-semiconductor (MIS) structure with a 1.5 nm thick TiO2 layer has a smaller Schottky barrier of 22 meV. The results provide insights into the engineering of MIS contacts and interfaces to improve transistor characteristics.

Electrical Performance Enhanced Doping Less Tunnel Field Effect Transistor by Metal Electrode Work Function Engineering

Tunnel field effect transistor (TFET) has been proposed as one of the promising alternative devices to MOSFET since it has low power consumption and excellent subthreshold swing (SS) characteristics of less than 60 mV / dec. However, conventional TFET fabrication requires ion implantation process to form p-i-n structure in active region, which induces a random distribution of dopant atoms. In the nm-scale device, even a small number of dopant atom dispersion can cause electrical characteristic variations such as threshold voltage (Vt)1, so alternative method for forming p-i-n region instead of doping process is needed.Doping-less TFET (DL-TFET) introduces charge plasma concept2 that controls carrier concentration of Si region by band alignment in MOS contact not by doping process, so random dopant fluctuation (RDF) issue can be solved. Since the active region carrier concentration is determined by the work function of the metal electrode, it is necessary to analyze the device performance by the metal work function condition. In this work, we manufactured doping-less TFET with adapting various metal work function to enhance electrical performance, and conducted CV measurement in MOS structure to confirm Si band bending and charge plasma by analyzing flat band voltage (VFB).DL-TFET was fabricated on SOI wafer and the overall structure is shown in Fig. 1. (a). In the case of the source region, the metal work function must be larger than that of Si to form the p-type active area, and drain region, on the contrary, must have smaller work function for n-type active region. Obviously, gate electrode work function has similar work function to intrinsic Si. For fabricating DL-TFET, we conducted reactive ion etch (RIE) process to define Si active layer and formed gate oxide (SiO2) by thermal oxidation. Then, we deposited gate metal and removed source / drain region oxide for contact hole. Spacer oxide was deposited using PECVD to isolate each metal electrode, finally we deposited source / drain metal. IV characteristics are shown in Fig. 1. (b), (c) when Pt / W / Al is applied at source / gate / drain area and we compared IV curve of various metal electrode and thermal conditions.In addition, to confirm whether the charge plasma was formed as intended, we fabricated MOS capacitor with 10 nm oxide thickness as shown in Fig. 1. (d). Through frequency sweep, we determined suitable bias frequency and conducted CV measurement (see Fig. 1. (e), (f), (g)). Band bending and charge plasma were confirmed by evaluating VFB shift depending on work function of each MOS gate material (see Fig. 1. (h)). Finally, we discussed the optimal metal electrode combination in terms of ambipolar current, off current, on current and SS. Key Words: Charge plasma, Doping-less TFET, Work function, CV measurement References Changho Shin, Jeong-Kyu Kim, Gwang-Sik Kim, Hyunjae Lee, Changhwan Shin, Jong-Kook Kim, Byung Jin Cho, and Hyun-Yong Yu, “Random Dopant Fluctuation-Induced Threshold Voltage Variation-Immune Ge FinFET With Metal–Interlayer–Semiconductor Source/Drain,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 63, No. 11, pp 4167-4172, Nov 2016. doi: 10.1109/TED.2016.2606511 Raymond J. E. Hueting, Bijoy Rajasekharan, Cora Salm, and d Jurriaan Schmitz, " The Charge Plasma P-N Diode" IEEE ELECTRON DEVICE LETTERS, vol. 29, issue 12, pp 1367-1369, Dec 2008. doi: 10.1109/LED.2008.2006864 Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2021, the MOTIE (Ministry of Trade, Industry & Energy 20010836) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

Enhancement of DRAM Performance by Adopting Metal–Interlayer–Semiconductor Source/Drain Contact Structure on DRAM Cell

The effects of a metal–interlayer–semiconductor (MIS) source/drain (S/D) contact structure on a dynamic random access memory (DRAM) cell transistor are investigated using 3-D technology computer-aided design simulation. When the MIS S/D contact structure is used in a DRAM cell, the retention time increases by approximately 16.22 times when compared with that of the device using the metal–semiconductor (MS) S/D contact structure owing to the lowered S/D doping concentration, leading to a decrement of the gate-induced drain leakage. Furthermore, the write time and charge-sharing time, respectively, are approximately 0.74 and 0.69 times shorter when compared with the device using the MS S/D contact structure owing to better ohmic characteristics, which increase the drain current during the write/read operations. Thus, the MIS S/D contact structure can effectively enhance the retention and write/read characteristics of a DRAM cell, and it can be a promising S/D contact alternative for the DRAM cell in the sub-2y-nm technology node.

Effect of Temperature on the Electrical and Current Transport Properties of Au/Nd2O3/n-GaN Metal/Interlayer/Semiconductor (MIS) Junction

The Au/Nd2O3/n-type GaN metal/interlayer/semiconductor (MIS) junctions were fabricated with high-k rare-earth oxide interlayer and explored its electrical properties in the wide temperature range of 150–400 K. An anomalous decrease in barrier height and an increase in the ideality factor with a decrease in the temperature were observed. The anomalous barrier height and ideality factor are ascribed to a role of barrier inhomogeneities at the interface of MIS junction assuming a double Gaussian distribution of barrier heights in the temperature ranges of 150–225 K and 225–400 K. Double Gaussian distribution giving mean barrier heights of 0.84 eV and 1.23 eV and standard deviations of 0.0085 V and 0.0187 V for the two temperature regions. A modified conventional energy plot gives mean barrier height $$\left( {\overline{\Phi }_{bo} } \right)$$ and Richardson constant (A*) as 0. eV and 13.44 Acm−2 K−2 (150–225 K) and 1.23 eV and 22.85 Acm−2 K−2 (250–400 K), respectively. The estimated A* value in the temperature range of 250–400 K was closely matched with the theoretical value of n-type GaN. Moreover, results express that the obtained interface state density of the MIS junction decreases with increasing temperature. Results explained that the reverse current conduction governed by Poole–Frenkel emission at the temperature range of 150–225 K and Schottky emission at 250–400 K, respectively.

LER-Induced Random Variation–Immune Effect of Metal-Interlayer–Semiconductor Source/Drain Structure on N-Type Ge Junctionless FinFETs

Herein, the line-edge roughness (LER)-induced random performance variation–immune effect of metal–interlayer–semiconductor (MIS) source/drain (S/D) in 7 nm n-type Ge (n-Ge) junctionless field-effect transistors (JLFETs) were investigated by 3-D TCAD simulations. Compared to the device without MIS S/D, the n-Ge JLFET with MIS S/D could effectively reduce the Ge fin doping concentration while maintaining the performance. It was demonstrated analytically that the reduced Ge fin doping concentration of the device with MIS S/D, compared to the device without MIS S/D, decreased the LER-induced random performance variations of the n-Ge JLFET; the standard deviations were reduced to ~0.0318 V for ${V} _{\text {th}}$ (reduced by ~51.6%), $4.89\times 10^{\text {-6}}$ A/ $\mu \text{m}$ for ${I} _{\text {on}}$ (reduced by ~92.1%), $1.44\times 10^{\text {-9}}$ A/ $\mu \text{m}$ for ${I} _{\text {off}}$ (reduced by ~93.7%), 1.27 mV/dec for SS (reduced by ~23.1%), and ~5.40 mV/V for drain-induced barrier lowering (DIBL) (reduced by ~30.8%). In addition, LER-induced random performance variation was investigated in terms of scaling down fin widths. The results provided critical insight into the variability reduction of the 7 nm n-Ge JLFETs.

Schottky barrier engineering with a metal nitride–double interlayer–semiconductor contact structure to achieve high thermal stability and ultralow contact resistivity

A new contact structure of a metal nitride-double interlayer-semiconductor structure with high thermal stability and ultralow contact resistivity is developed as a next-generation contact scheme via application of interface engineering. As conventional metal–interlayer–semiconductor structures exhibit degradation under thermal stressing owing to the intermixing of materials, three approaches for achieving enhanced thermal stability and ultralow contact resistance are applied. First, a metal nitride with high thermal stability and low reactivity is used as the contact metal. Second, a material with high crystallization temperature is used for the interlayer to prevent the grain boundary diffusion of metal through the interlayer. Lastly, a double interlayer structure is adopted to reduce the Schottky barrier height by utilizing the dipole effect. The corresponding contact was demonstrated to successfully sustain its structure after annealing of 550 ℃. Moreover, it exhibited a specific contact resistivity of 2.20 × 10−8 Ω·cm2, which is a reduction of ~198× and ~2.72× to those of the metal–semiconductor structure and the metal–interlayer–semiconductor structure, respectively. The proposed contact structure and interface engineering techniques in this study provide a valid method to achieve high thermal stability while maintaining low contact resistivity, which is a priority requirement for the emerging nanoscale technology.

Synthesis of CuO–graphene nanocomposite material and the effect of gamma radiation on CuO–graphene/p-Si junction diode

Here, we introduce high-quality CuO–Graphene nanocomposite synthesis by hydrothermal method and used it as the interfacial layer to investigate radiation resistance in metal/interlayer/semiconductor (MIS) junction diode structure. In order to determine the effect of the nanocomposite layer on the electrical characteristics of Al/CuO–Graphene/p-Si/Al MIS junction diode, the current–voltage (I–V) measurements were performed at room temperature. The main electrical parameters of the junctions such as ideality factor (n), barrier height (Φb) were calculated using the thermionic emission (TE) theory and the results were compared with reference Schottky Diode (SD). The Φb and n values were calculated as 0.70 eV, 1.93 and 0.72 eV, 1.75 for reference SD and CuO–Graphene/p-Si MIS junction, respectively. The n value of the device reduced in the presence of the nanocomposite layer between the metal and the semiconductor. In addition, the Φb and series resistance (Rs) parameters were calculated from I–V measurements using Norde functions and the results were compared with the TE method. Furthermore, to determine the radiation tolerance property of the devices, gamma radiation was applied and the electrical parameters were evaluated for unirradiated and irradiated cases. The results showed that the fabricated devices may have various applications; thanks to radiation tolerance property. To the best of our knowledge, there is no research available regarding the exposure of CuO–Graphene thin films to gamma-ray irradiation studied using the I–V technique. Therefore, we believe that this study can make an important contribution to the literature.

Electrical and carrier transport properties of Au/Pr6O11/n-GaN MIS structure with a high-k rare-earth oxide interlayer at high temperature range

The electrical and carrier transport properties of Au/Pr6O11/n-GaN metal/interlayer/semiconductor (MIS) structure with an electron beam deposited high-k rare-earth oxide as an interlayer have been investigated in the temperature range of 270–420 K. The electrical characteristics such as current–voltage (I–V), turn-on voltage and series resistance (RS) are analyzed at different temperatures. These analysis showed that the obtained barrier heights (Φb) increase while ideality factor (n) and RS decrease with increasing temperature. The characteristic temperature (T0) is determined from the RS against temperature plots, and the value (T0) is well matched with each other. The calculated thermal coefficient (Kj) value is – 2.1 mV/K at ≥ 270 K. The obtained effective barrier height (1.22 eV) is consistent with the theoretical value. The temperature-dependent ideality factor values are in good agreement with characteristic energy of 31 meV. The estimated interface state density (NSS) increases with decreasing temperature that could be associated with the molecular restructuring and reordering of the Pr6O11/n-GaN interface. The reverse bias results showed that the current conduction is dominated by Poole-Frenkel emission in the temperature range of 270–330 K while the Schottky emission is dominated in the temperature range of 360–420 K.

Schottky Barrier Height Engineering inβ-Ga2O3Using SiO2Interlayer Dielectric

This paper reports on the modulation of Schottky barrier heights (SBH) on three different orientations of $\beta$-Ga$_2$O$_3$ by insertion of an ultra-thin SiO$_2$ dielectric interlayer at the metal-semiconductor junction, which can potentially lower the Fermi-level pinning (FLP) effect due to metal-induced gap states (MIGS). Pt and Ni metal-semiconductor (MS) and metal-interlayer-semiconductor (MIS) Schottky barrier diodes were fabricated on bulk n-type doped $\beta$-Ga$_2$O$_3$ single crystal substrates along the (010), (-201) and (100) orientations and were characterized by room temperature current-voltage (I-V) and capacitance-voltage (C-V) measurements. Pt MIS diodes exhibited 0.53 eV and 0.37 eV increment in SBH along the (010) and (-201) orientations respectively as compared to their respective MS counterparts. The highest SBH of 1.81 eV was achieved on the (010)-oriented MIS SBD using Pt metal. The MIS SBDs on (100)-oriented substrates exhibited a dramatic increment ($>$1.5$\times$) in SBH as well as reduction in reverse leakage current. The use of thin dielectric interlayers can be an efficient experimental method to modulate SBH of metal/Ga$_2$O$_3$ junctions.

Improved switching characteristics of p-type tin monoxide field-effect transistors through Schottky energy barrier engineering

Metal–interlayer–semiconductor contact reduces metal-induced gap states, mitigating Fermi-level pinning at metal/semiconductor interface. Here, switching property of p-type SnO FET is enhanced by increasing electron Schottky barrier at off-state.

Clean Interface Contact Using a ZnO Interlayer for Low-Contact-Resistance MoS2 Transistors.

Two-dimensional transition metal dichalcogenides (TMDCs) have emerged as promising materials for next-generation electronics due to their excellent semiconducting properties. However, high contact resistance at the metal-TMDC interface plagues the realization of high-performance devices. Here, an effective metal-interlayer-semiconductor (MIS) contact is demonstrated, wherein an ultrathin ZnO interlayer is inserted between the metal electrode and MoS2, providing damage-free and clean interfaces at electrical contacts. Using TEM imaging, we show that the contact interfaces were atomically clean without any apparent damages. Compared to conventional Ti/MoS2 contacts, the MoS2 devices with a Ti/ZnO/MoS2 contact exhibit a very low contact resistance of 0.9 kΩ μm. These improvements are attributed to the following mechanisms: (a) Fermi-level depinning at the metal/MoS2 interface by reducing interface disorder and (b) presence of interface dipole at the metal/ZnO interface, consequently reducing the Schottky barrier and contact resistance. Further, the contact resistivity of a Ti/ZnO/MoS2 contact is insensitive to the variation of ZnO thickness, which facilitates large-scale production. Our work not only elucidates the underlying mechanisms for the operation of the MIS contact but also provides a simple and damage-free strategy for conventional aggressive metal deposition that is potentially useful for the realization of large-scale 2D electronics with low-resistance contacts.

High Temperature Characterization of a MIS Schottky Diode Based on Diamond-Like Carbon Nanocomposite Film

Many kind of materials have been inserted between metals and semiconductors to obtain metal–interlayer–semiconductor (MIS) Schottky diodes with higher barrier height. It is well known that the interlayer materials have to meet some requirements such as hold on the substrate, thermal stability and wear resistance. In this context, the diamond-like carbon (DLC) films seem good candidates as a material that can fulfill these requirements due to their superior properties. In this study, sulfur doped diamond-like carbon (S-DLC) nanocomposite film was deposited electrochemically, and it was used as an interlayer to fabricate an Au/S-DLC/p-Si MIS Schottky diode. An Au/p-Si metal semiconductor diode was also fabricated for comparison. The electrodeposited S-DLC film was characterized by scanning electron microscopy, Raman spectroscopy and x-ray photoelectron spectroscopy. Temperature dependence of the current–voltage (I–V) characteristic of the diodes was studied in the range of 300–700 K. The ideality factors (n) and barrier heights (Φb) were calculated from the forward bias I–V characteristics. It was observed that both parameters showed temperature dependence. Barrier height values were increased with increasing temperature, while ideality factors values were decreased. The observed non-linearity in Richardson plots were explained by Gaussian distributions of inhomogeneities of barrier heights. Modified Richardson plots were used to obtain actual values of barrier height. It was shown that S-DLC film can be a good candidate for the high temperature diode applications.

P‐198: Late‐News Poster: Off‐Current Reduction in p‐Type SnO Thin‐Film Transistors through Fermi‐Level Unpinning

High off‐current in p‐type SnO thin‐film transistors (TFTs) limits the application to active matrix devices for next generation display industry. Here, we propose a new approach to suppress the off‐current using metal‐interlayer‐semiconductor (MIS) contact structure. The MIS contact structure makes Fermi‐level pinning (FLP) alleviated through an ultrathin interlayer (IL) which prevents metal‐induced gap states (MIGSs), the origin of severe FLP, and thereby Schottky barrier height (SBH) can be modulated. With the electron SBH (eSBH) increasing, the electron injection from drain electrode into the SnO channel is suppressed, which results in the reduction of the off‐current from 5.1 × 10‐8 A to 2.4 × 10‐9 A and the enhancement of the ION/OFF from 2.7 × 102 to 2.8 × 103 compared with the conventional metal‐semiconductor (MS) contacted TFTs. This work shows not only the enhancement in device performance but also a new perspective on the origin of off‐current in the p‐type SnO TFTs.

Microstructural, chemical and electrical characteristics of Au/magnetite (Fe3O4)/n-GaN MIS junction with a magnetite interlayer

Magnetite (Fe3O4) layers were prepared on n-type GaN surface by the e-beam method and its microstructural and compositional characteristics were evaluated by XRD, XPS and TEM techniques. The XRD, XPS and TEM evaluations confirmed the formation of the Fe3O4 layer on the n-GaN surface. Then, the Au/Fe3O4/n-GaN metal/interlayer/semiconductor (MIS) junction was fabricated and its electrical properties investigated with the I-V and C-V approaches. The MIS junction showed a good rectification nature with a high barrier height (0.83 eV) compared to the SE (0.71 eV). This implies that the barrier height was markedly affected by the Fe3O4 layer. Further, the barrier height was extracted by means of Cheung's, Norde and ψS-V plot and it was found that the values are nearly matched with one another, indicating that the methods used were consistent and valid. The frequency-dependent properties of the MIS and SE junctions have also been discussed. The interface state density (NSS) of the MIS junction was found to be lower than the SE, indicating that the Fe3O4 layer plays a vital role in the decreased NSS. Based on the analysis, it can be concluded that the Fe3O4 layer is an apt material for the fabrication of new electronic device applications.

Schottky Barrier Height Modulation Using Interface Characteristics of MoS2 Interlayer for Contact Structure.

Schottky barrier height (SBH) engineering of contact structures is a primary challenge to achieve high performance in nanoelectronic and optoelectronic applications. Although SBH can be lowered through various Fermi-level (FL) unpinning techniques, such as a metal/interlayer/semiconductor (MIS) structure, the room for contact metal adoption is too narrow because the work function of contact metals should be near the conduction band edge (CBE) of the semiconductor to achieve low SBH. Here, we propose a novel structure, the metal/transition metal dichalcogenide/semiconductor structure, as a contact structure that can effectively lower the SBH with wide room for contact metal adoption. A perpendicularly integrated molybdenum disulfide (MoS2) interlayer effectively alleviates FL pinning by reducing metal-induced gap states at the MoS2/semiconductor interface. Additionally, it can induce strong FL pinning of contact metals near its CBE at the metal/MoS2 interface. The technique using FL pinning and unpinning at metal/MoS2/semiconductor interfaces is first introduced in the MIS scheme to allow the use of various contact metals. Consequently, significant reductions of the SBH from 0.48 to 0.12 eV for GaAs and from 0.56 to 0.10 eV for Ge are achieved with several different contact metals. This work significantly reduces the dependence on contact metals with lowest SBH and proposes a new way of overcoming current severe contact issues for future nanoelectronic and optoelectronic applications.

Schottky barrier height modulation of metal–interlayer–semiconductor structure depending on contact surface orientation for multi-gate transistors

A metal–interlayer–semiconductor (MIS) structure that is realized by inserting an ultrathin interlayer between a contact metal and a semiconductor has been investigated recently as a low-resistance non-alloyed contact structure. However, a comprehensive and systematical investigation of Schottky barrier height (SBH) modulation through the insertion of an interlayer depending on the contact surface orientation has not been conducted despite its importance for its use in multi-gate transistors. Therefore, in this work, the SBH modulation of the MIS contact structure for different contact surface orientations is systematically investigated, and a comprehensive analysis platform of the MIS contact structure is suggested. Two factors, (1) alleviation of Fermi-level pinning due to metal-induced gap states and interface states and (2) formation of the interface dipole, contribute to the SBH modulation in the MIS contact structure. Their contributions depending on the contact surface orientation are evaluated through a comparison of the contact structures on (100)- and (110)-oriented germanium (Ge). These factors and how they should be considered for a certain contact surface in Ge-channel multi-gate transistors are investigated. The investigation and the proposed analysis platform will contribute to the design of high-performance non-alloyed contact schemes for next-generation multi-gate transistors.