Metal Oxide Semiconductor System Research Articles

Exploring Terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR Integrated Circuits: Advancements and Obstacles

The text provides a description of the characteristics of several NMOS and CMOS circuit approaches, as well as an explanation of the limitations associated with each technology. Next, the CMOS domino circuit, a novel form of circuit, is explained. This entails interconnecting dynamic CMOS gates in a manner that enables the activation of all gates in the circuit simultaneously using a single clock edge. Consequently, there is no need for intricate clocking methods, allowing the dynamic gate to operate at its maximum speed. This circuit features a basic mode voltage-controlled oscillator operating at 135 GHz in 80-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR, a 405 GHz push-push voltage controller in 38-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR with an on-chip patch antenna, a 128 GHz Schottky diode frequency doubler, a 170 GHz Schottky diode detector, a 600 GHz plasma wave detector in 122-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR and a 40 GHz phase-locked loop with a frequency doubled output at 110 GHz. Given this and the trends in performance of n METAL OXIDE SEMICONDUCTOR transistors and Schottky diodes produced in complementary metal-oxide semiconductors, we lay out a plan for terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR systems and circuits, highlighting critical challenges that need to be addressed. With the advent of terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

(Invited) Investigating Defects in the High-k/Ingaas System at Cryogenic Temperature

III-V RF devices operating at cryogenic temperature are highly desirable for application areas such as space communication or quantum computing. In the case of quantum computation, integration of the readout and control electronics close to the quantum bit (Qubit) stage is needed to allow scaling of the number of Qubits needed for practical applications. Many characteristics of high frequency operation at cryogenic temperature in novel III-V devices are not fully understood. In this study, we will focus on the behaviour of defects at or near the interface between the high dielectric constant (high-k) oxide and InGaAs semiconductor at cryogenic temperature and how it may affect the full device operation at low temperature.The thermal budget constraints associated with the processing III-V semiconductor devices prohibit the use of high temperature thermal treatments to reduce oxide defect densities in the high-k. This leads to defective oxides presenting higher instability, variability, and degradation issues than in the Si/SiO2 system. The methods developed to investigate defects in the Si/SiO2 metal oxide semiconductor (MOS) system generally attribute the divergence in capacitance voltage (CV) and conductance voltage (GV) from the ideal CV and GV characteristics mostly to interface state defects (ITs) [1], which is not the case of the III-V MOS system. As a consequence, attempts to fit the multi-frequency CV and GV response of III-V MOS structures in the weak inversion regime, using interface states alone, cannot recreate the experimental data.In this study, we present an advanced MOS defects characterisation method capable of discerning between the contributions of oxide defects (sometimes labelled ‘border traps’) and ITs. The method relies on the fully physics based simulation of MOS systems, including inelastic tunnelling from the semiconductor to localized defects in the oxide [2] to reproduce the experimental multi-frequency CV and GV characteristics. The simulations include physical models accurately describing the carrier capture/emission processes by oxide traps, and which incorporate tunneling into the dielectric in conjunction with lattice relaxation at the interface/border trap sites [3, 4]. The results will show that the simulations are able to reproduce the room temperature experimental data (both CV and GV) of InGaAs/Al2O3 MOS structures in all bias regions. This new method enables the precise extraction of the density, energy and spatial distribution away from the interface of electrically active oxide defects from different experimental results.Results will also be presented showing how the multi-frequency CV and GV response of n-InGaAs/Al2O3 and p-InGaAs/Al2O3 MOS structures change with reducing temperature. Measurements at 223K show a marked reduction in the CV and GV dispersion with frequency in the accumulation and depletion regions, consistent with a phonon assisted tunnelling interaction of electrons and holes with defects in the Al2O3. Reduction in the measurement temperature to 10K still demonstrates a residual dispersion of the capacitance and conductance with frequency, which is more marked in the case of the p-InGaAs/Al2O3 MOS structure. The models and trap distributions extracted from room temperature will be applied to the reduced temperature measurements (233 K and 10 K) to investigate the validity of the models and to gain further understanding of defect behaviour and associated device implications at cryogenic temperatures.[1] E. H. Nicollian and J. R. Brews, “MOS Physics and Technology,” John Wiley & Sons, New York, 1982.[2] A. Palma, et al. Phys. Rev. B Condens. Matter Mater. Phys., 56 (15), pp. 9565-9574 (1997).[3] E. Caruso, et al. IEEE Trans. Electron Devices, 67 (10), pp. 4372-4378 (2020)[4] G. Sereni, et al. “IEEE Trans. Electron Devices, vol. 62, no. 3, pp. 705–712, (2015).

Parallel Gate Operations Fidelity in a Linear Array of Flip‐Flop Qubits

AbstractQuantum computers based on silicon are promising candidates for long term universal quantum computation due to the long coherence times of electron and nuclear spin states. Furthermore, the continuous progress of micro‐ and nano‐electronics, also related to the scaling of metal–oxide–semiconductor systems, makes it possible to control the displacement of single dopants thus suggesting their exploitation as qubit holders. Flip‐flop qubit is a donor based qubit where interactions between qubits are achievable for distance up to several hundred nanometers. In this work, a linear array of flip‐flop qubits is considered and the unwanted mutual qubit interactions due to the simultaneous application of two one‐qubit and two two‐qubit gates are included in the quantum gate simulations. In particular, by studying the parallel execution of couples of one‐qubit gates, namely and , and of couples of two‐qubit gate, that is, , a safe inter‐qubit distance is found where unwanted qubit interactions are negligible thus leading to parallel gates fidelity up to 99.9%.

Formation and characterization of holmium oxide on germanium‐based metal‐oxide‐semiconductor capacitor

The influence of different thermal oxidation/nitridation durations (5, 10, 15, and 20 minutes) at 400°C for transforming metallic Ho sputtered on Ge substrate in N2O gas ambient have been systemically investigated to develop Ho2O3/Ge based on metal-oxide-semiconductor (MOS) device. The structural and chemical properties of the film were characterized using X-ray diffraction spectroscopy, X-ray photoelectron spectroscopy (XPS), and high-resolution transmission electron microscopy. Cubic-Ho2O3 dielectric layer has been formed along with sandwiched interfacial layer (IL) between substrate Ge and high-k interface comprising tetragonal-GeO2, GeOx, and cubic-Ge3N4 compounds. Energy band alignment for Ho2O3/IL/Ge MOS stack has been determined from XPS spectrum where 10-minute sample exhibited maximum conduction band offset, ΔEc ~ 2.47 eV and valance band offset, ΔEv ~ 4.67 eV, inducing lower leakage current density, J ~ 10−5 A cm−2 at the higher electrical breakdown, EBD ~ 8.59 MV cm−1. The electrical results of this sample also revealed higher dielectric constant k ~ 13.60, lowest effective oxide charge, slow trap density, and interface trap density which has been attributed to the confinement of Ho2O3 dielectric interface and densification Ge3N4 interfacial compound. An oxidation/nitridation model related to Ho2O3/IL/Ge stack growth is being proposed. It has been anticipated that Ho2O3 could serve as a gate dielectric oxide for Ge-based MOS systems such as a capacitor.

Effect of quantum confinement on the defect-induced localized levels in 4H-SiC(0001)/SiO2 systems

In the present study, we characterize the nature of interface states in silicon carbide (SiC) metal–oxide–semiconductor (MOS) systems by analyzing the electrical characteristics of MOS field effect transistors (MOSFETs) based on the results of numerical calculations. In the calculation, the potential distributions and energy sub-bands were calculated by solving Poisson and Schrödinger equations, respectively. As a result, we demonstrate that the defect-induced localized levels in the bandgap are subjected to quantum confinement at the inversion layer, leading to the increase in their energy levels. The result implies that the conventional interface defects (e.g., near-interface oxide traps), which create defect states at certain energy levels measured from the vacuum level, are unlikely to be the major origin of the interface states in SiC MOS systems. The interface state density is almost uniquely determined by the oxide formation process (as oxidation or interface nitridation) and independent of the acceptor concentration (3 × 1015–1 × 1018 cm−3). It is also suggested that the drain current decrease observed in heavily doped MOSFETs is mainly due to the decrease in the drift mobility rather than that in the free carrier density.

The Role of Oxide Traps Aligned With the Semiconductor Energy Gap in MOS Systems

This work demonstrates that when inelastic tunneling between oxide traps and semiconductor bands is considered, the traps with energy aligned to the semiconductor bandgap play a significant role in the frequency dispersion of the capacitance–voltage ( C–V ) and conductance–voltage ( G–V ) characteristics of metal–oxide–semiconductor (MOS) systems. The work also highlights that a nonlocal model for tunneling into interface states is mandatory to reproduce experiments when carrier quantization in the inversion layer is accounted for. A model, including these ingredients, is used to evaluate the energy and depth distribution of oxide traps in a n-In0.53Ga0.47As/Al2O3 MOS system and is able to accurately fit the C–V frequency dispersion from depletion to weak inversion. The oxide trap distribution determined from the C–V response predicts the corresponding G–V dispersion with frequency.

Lateral Photovoltaic Effect and Photo‐Induced Resistance Effect in Nanoscale Metal‐Semiconductor Systems

AbstractFunctionalization of photoelectric effect in nanostructures is presenting a promising strategy for humans to achieve precise detection and efficient transformation. Due to the high applied value, numerous materials and constructions are adopted for photoelectric effect to deliver on its potential performance. Among these functional materials, metal‐semiconductor (MS) or metal‐oxide‐semiconductor (MOS) systems own unparalleled advantage including reliable stability, superb physical performance, and simple fabrication process. Herein, two types of photoelectric effect, lateral photovoltaic and photo‐induced resistance effect, in nanostructure MS or MOS systems are reviewed. These effects have great potential in applications and will play a beneficial role in future investigations. In addition, how each component of the system contributes to the photoelectric properties and responds to external fields are detailed, suggesting future study directions in photoelectric fields.

Investigating positive oxide charge in the SiO2/3C-SiC MOS system

This paper investigates the origin of the fixed positive oxide charge often experimentally observed in Metal Oxide Semiconductor (MOS) structures of SiO2 formed on cubic silicon carbide (3C-SiC). The electrical properties of MOS structures including either thermally grown SiO2 or deposited SiO2 by Plasma Enhanced Chemical Vapour Deposition (PECVD) on epitaxial 3C-SiC layers grown directly on Si are investigated. MOS structures with a range of oxide thickness values subjected to different thermal treatments were studied. It was found that both thermally grown and deposited SiO2 on 3C-SiC exhibit similar positive charge levels indicating that the charge originates from interface states at the 3C-SiC surface and not from the oxide. The nature of this surface charge in the SiO2/3C-SiC system is also discussed based on the current data and previously published results.

87%-Efficient 330-mW 0.6-<italic>μ</italic>m Single-Inductor Triple-Output Buck–Boost Power Supply

Microsystems that sense, process, and communicate data can save money, energy, and lives. Such varied functionality, however, demands power that can easily deplete a small battery. Integrating so many analog and digital functions can also imperil performance with noise and distortion. To survive all this with an exhaustible battery, blocks require several efficient power supplies that both buck and boost the battery voltage. Luckily, switched inductors are flexible and efficient, but also bulky. So what these microsensors need are single-inductor multiple-output supplies that buck and boost. But to reconfigure the inductor for such diverse operation requires many power-consuming switches. Plus, cycling between outputs requires time and delays response time. The single-inductor supply proposed bucks and boosts and cycles between outputs frequently with two input switches, one inductor, and one switch and one capacitor per output. Other buck–boost supplies either bypass the inductor or require one to two more switches and up to one more inductor and one more capacitor. The prototype presented here bucks two outputs and boosts one output with five switches by energizing the inductor to buck outputs first. By collecting sufficient energy this way, the inductor can feed boost outputs directly. A sixth switch engages only when boost power is greater than a threshold that the input voltage and buck power levels establish. This way, the 0.6- μ m complementary metal oxide semiconductor system bucks and boosts 2.7–4.0 V to 1.2, 1.8, and 4.0 V to deliver 80%−87% of the 379–412 mW drawn. The system cycles every 1–3 μ s and responds within 5–10 μ s.

(Invited) The Inversion Behaviour of Narrow Band Gap Mos Systems: Experimental Observations, Physics Based Simulations and Applications

Impedance spectroscopy of the metal-oxide semiconductor (MOS) system has played a central role in the development of silicon-based complementary MOS (CMOS) technology over the past 50 years [1, 2]. With current research interest into alternative semiconductor channels to silicon for MOSFET and tunnel FET technologies, the measurement and interpretation of the overall impedance of the MOS structure requires detailed analysis to separate and quantify the contribution of interface states, and near interface traps (border traps), on the capacitance and conductance response, and to separate the contribution of these electrically active defect states from the ac response of minority carriers in the case of genuine inversion of the semiconductor/dielectric interface. There has been considerable progress in recent years in reducing the interface state density (Dit) [3], [4], [5], in narrow gap InxGa1-xAs MOS structures to the point where genuine surface inversion can be observed for both n- and p-type In0.53Ga0.47As MOS capacitors, which is confirmed by analysis of the minimum capacitance of n- and p-type In0.53Ga0.47As MOS structure with doping concentration ranging from approximately 1x1016 to 1x1018 cm-3 [6]. In this presentation we will provide an overview of the experimental relationship between specific functions of the capacitance (C) and conductance (G) for the case of narrow band gap III-V MOS structures which exhibit genuine surface inversion, where the capacitance and conductance of the MOS system as a function of ac angular frequency (ω) are related, and in particular, the peak values of G/ω and −dC/dloge(ω) (≡− ωdC/dω) are equal, and that these peak magnitudes occur at the same value of ω [7]. The relationship is also confirmed by physics based ac simulations of MOS structures and through analysis of the equivalent circuit model in inversion. Results will be presented for InGaAs and InGaSb MOS structures (Al2O3 and Al2O3/HfO2 ALD oxides) where genuine inversion of the III-V/oxide surface is confirmed by the G/ω and −dC/dloge(ω) functions, which have peak values of Cox 2/2(Cox+Cd) when the surface is inverted (where Cox is the gate oxide capacitance and Cd is the maximum capacitance of the semiconductor surface in inversion). In the case of p type InGaSb MOS structures it is also notable that the accumulation frequency dispersion is very low (<0.7%/decade) indicating a reduced density of border traps at energies in the Al2O3 gate oxide aligning with the In0.3Ga0.7Sb valence band edge, which is approximately aligned with the lowest energy in the In0.53Ga0.47As conduction band gamma valley. Finally, experimental results and physics based simulations will be presented, which indicate that the peak values of G/ω and −dC/dloge(ω) in inversion for any MOS system which demonstrates an inversion response within the typically range of temperatures and ac signal frequencies employed in experiments, opens a route to determine the gate oxide capacitance in inversion (where the gate oxide field and gate leakage are reduced), and that the angular frequency associated with the peak values of the G/ω and −dC/dloge(ω) functions allows the determination of the minority carrier generation rate in the semiconductor, which is relevant to the leakage currents in MOSFETs and the optical performance in photonic applications. [1] E. H. Nicollian and J. R. Brews, MOS Physics and Technology. New York, NY, USA: Wiley, 1982 [2] E. H. Nicollian and A. Goetzberger, “The Si-SiO2 interface—Electrical properties as determined by the metal-insulator-silicon conductance technique,” Bell Syst. Tech. J., vol. 46, no. 6, pp. 1055–1133, 1967. [3] É. O’Connor et al., J. Appl. Phys., vol. 109, no. 2, p. 024101, 2011. [4] H.-D. Trinh et al., Appl. Phys. Lett., vol. 97, no. 4, pp. 042903-1–042903-3, 2010. [5] T. D. Lin et al., “Realization of high-quality HfO2 on In0.53Ga0.47As by in-situ atomic-layer-deposition,” Appl. Phys. Lett., vol. 100, no. 17, p. 172110, 2012. [6] E. O'Connor, K. Cherkaoui, S. Monaghan, B. Sheehan, I. M. Povey, and P. K. Hurley, Appl. Phys. Lett 110, 032902 (2017) [7] Scott Monaghan, Éamon O’Connor, Rafael Rios, Fahmida Ferdousi, Liam Floyd, Eimear Ryan, Karim Cherkaoui, Ian M. Povey, Kelin J. Kuhn, and Paul K. Hurley, IEEE Transaction on Electron Devices, 61, 4176 (2014)

Examining the relationship between capacitance-voltage hysteresis and accumulation frequency dispersion in InGaAs metal-oxide-semiconductor structures based on the response to post-metal annealing

In this work, we investigated the effect of forming gas annealing (FGA, 5% H2/95% N2, 250°C to 450°C) on border trap density in high-k/InGaAs metal-oxide-semiconductor (MOS) systems using accumulation frequency dispersion and capacitance-voltage (CV) hysteresis analysis. It is demonstrated that the optimum FGA temperature that reduces the accumulation frequency dispersion is 350°C for HfO2/n-InGaAs and 450°C for Al2O3/n-InGaAs MOS system. Volume density of border traps (Nbt) is estimated using the accumulation frequency dispersion based on a distributed model for border traps. It is shown that for HfO2/n-InGaAs MOS system, Nbt is reduced from 9.4×1019cm−3eV−1 before FGA to 6.3×1019cm−3eV−1 following FGA at 350°C. For the case of Al2O3/n-InGaAs MOS system, Nbt is reduced from 5.7×1019cm−3eV−1 for no FGA to 3.4×1019cm−3eV−1 for FGA at 450°C. Furthermore, it is shown that the most pronounced reduction in border trap density estimated from CV hysteresis analysis is observed at the same optimum FGA temperature that reduces the accumulation frequency dispersion, indicating that these two techniques for border trap analysis are correlated.

A study of capacitance–voltage hysteresis in the HfO2/InGaAs metal-oxide-semiconductor system

In this work, we performed a study of capacitance–voltage (C–V) hysteresis in HfO2/InGaAs metal-oxide-semiconductor (MOS) systems. The charge trapping density estimated from the C–V hysteresis is comparable to or even greater than the typical interface state density in high-k/InGaAs MOS systems. Based on an oxide thickness series, it is demonstrated that the magnitude of C–V hysteresis increases linearly with the increasing HfO2 thickness, with the corresponding density of trapped charge being a constant value over the range of oxide thicknesses, indicating that the charge trapping is occurring in a plane near/at the HfO2/InGaAs interfacial transition region. C–V hysteresis with a hold in accumulation was also investigated. It is observed that the C–V hysteresis has a power law dependence on the stress time in accumulation at the initial stage of stressing and tends to reach a plateau for sufficiently long stress times. Moreover, a larger gate voltage used during the stress increases the oxide field, allowing more border traps to be accessed.

Capacitance and Conductance for an MOS System in Inversion, with Oxide Capacitance and Minority Carrier Lifetime Extractions

Experimental observations for the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As metal-oxide-semiconductor (MOS) system in inversion indicate that the measured capacitance (C) and conductance (G or G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ), are uniquely related through two functions of the alternating current angular frequency (ω). The peak value of the first function (G/ω) is equal to the peak value of the second function (-dC/dlog <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</sub> (ω) ≡ -ωdC/dω). Moreover, these peak values occur at the same angular frequency (ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ), that is, the transition frequency. The experimental observations are confirmed by physics-based simulations, and applying the equivalent circuit model for the MOS system in inversion, the functional relationship is also demonstrated mathematically and shown to be generally true for any MOS system in inversion. The functional relationship permits the discrimination between high interface state densities and genuine surface inversion. The two function peak values are found to be equal to C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /(2(C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> + C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> )) where C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> is the oxide capacitance per unit area and C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> is the semiconductor depletion capacitance in inversion. The equal peak values of the functions, and their observed symmetry relation about ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> on a logarithmic ω plot, opens a new route to experimentally determining C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> . Finally, knowing ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> permits the extraction of the minority carrier generation lifetime in the bulk of the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As layer.

Advanced methodology for electrical characterization of metal/high-k interfaces

A methodology for the quantitative electrical characterization of defects at metal/high-k interfaces is proposed. It includes modelling of trapping in the oxide, fit of experiments, and calculation of the system band diagram after trapping. As a result, the defect concentrations and energy levels are extracted. The methodology is demonstrated on metal-oxide–semiconductor systems, but its results can be extended on whatever structure containing an interface between a metal and a high-k dielectric film.

The Characterization and Passivation of Fixed Oxide Charges and Interface States in the $\hbox{Al}_{2}\hbox{O}_{3}/ \hbox{InGaAs}$ MOS System

In this paper, we present a review of experimental results examining charged defect components in the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As metal-oxide-semiconductor (MOS) system. For the analysis of fixed oxide charge and interface state density, an approach is described where the flatband voltage for n- and p-type Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As MOS structures is used to separate and quantify the contributions of fixed oxide charge and interface state density. Based on an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> thickness series (10-20 nm) for the n- and p-type In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As layers, the analysis reveals a positive fixed charge density ( ~ 9 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ) distributed throughout the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and a negative sheet charge density (- 8 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ) located near the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As interface. The interface state density integrated across the energy gap is ~1 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> and is a donor-type (+/0) defect. The density of the fixed oxide charge components is significantly reduced by forming gas (5 % H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> / 95% N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ambient at 350 °C for 30 minutes) annealing. The interface state distribution obtained from multi-frequency capacitance-voltage and conductance-voltage measurements on either MOS structures or MOSFETs indicates a peak density located around the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As midgap energy, with a sharp increase in the interface state density toward the valance band and evidence of interface states aligned with the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As conduction band. The integrated interface state density obtained from multi-frequency capacitance-voltage and conductance-voltage analysis is in good agreement with the approach of comparing the flatband voltages in n- and p -type Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As MOS structures. Finally, this paper reviews recent work based on an optimization of the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As surface preparation using (NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> ) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> S, combined with minimizing the transfer time to the atomic layer deposition reactor for Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , which indicates interface state reduction and genuine surface inversion for both n- and p -type Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As MOS structures.

Electrically active interface defects in the In0.53Ga0.47As MOS system

• The energy distribution of electrically active interface states at the Al 2 O 3 /In 0.53 Ga 0.47 As interface has been evaluated. • Analysis reveals a peak of donor-like interface trap density 1.5 × 10 13 cm −2 eV −1 located at ∼0.36 eV above E v . • Acceptor-like interface traps are also present located in the In 0.53 Ga 0.47 As conduction band . • The interface state distribution is similar to reports for others oxides. • Results suggest the interface states originate from the In 0.53 Ga 0.47 As surface. In this work we present experimental results examining the energy distribution of the relatively high (>1 × 10 12 cm −2 eV −1 ) density of electrically active defects which are commonly reported at the interface between high dielectric constant (high- k ) thin films and In 0.53 Ga 0.47 As. The interface state distribution is examined for the Al 2 O 3 /In 0.53 Ga 0.47 As metal-oxide-semiconductor (MOS) system based on analysis of the full gate capacitance ( C g – V g ) of the surface n -channel In 0.53 Ga 0.47 As MOS transistors. The experimental capacitance, recorded at −50 °C and 1 MHz to approximate a high frequency response, is compared to the theoretical C g – V g response to evaluate the interface state distribution across the In 0.53 Ga 0.47 As energy gap and extending into the In 0.53 Ga 0.47 As conduction band. To improve the accuracy of the fitting process, the Maserjian Y-function was used in the modeling of the interface defects and fixed oxide charge densities. The analysis reveals a peak of donor-like interface traps with a density of 1.5 × 10 13 cm −2 eV −1 located at ∼0.36 eV above the In 0.53 Ga 0.47 As valence band edge, a high density of donor-like states increasing towards the In 0.53 Ga 0.47 As valence band. The analysis also indicates acceptor-like interface traps located in the In 0.53 Ga 0.47 As conduction band, with a density of ∼2.5 × 10 13 cm −2 eV −1 at 0.3 eV above the In 0.53 Ga 0.47 As conduction band minima. The reported interface state density is similar to reports for others oxides, suggesting that the recorded interface states originate from the In 0.53 Ga 0.47 As surface.

Phase and amplitude sensitive scanning microwave microscopy/spectroscopy on metal–oxide–semiconductor systems

In this paper, an analytical model for phase and amplitude sensitive scanning microwave microscopy on metal–oxide–semiconductor structures is presented. The phase and amplitude of the microwave signals are calculated as a function of operation frequency, oxide thickness, tip radius, bias, and doping level. For doping profiling applications it is found that both the microwave amplitude and phase signals can be used. Under appropriate operation conditions, the phase signals can be larger by a factor of 40. Series resistances turn out to be problematic as they lead to non–monotonic contrast at low doping levels. The phase and amplitude behavior on a material system with a frequency dependent dielectric constant is also investigated and the possibilities of complex impedance spectroscopy are explored.

Electrical Characterization of the MOS (Metal-Oxide-Semiconductor) System: High Mobility Substrates

Recent developments on CMOS-driven III-V and Ge MOS (Metal-oxide-semiconductor) technologies provide new opportunities in advancing the performance envelope of MOS device as well as the relevant electrical characterization techniques. Understanding the capacitance-voltage (CV) and conductance voltage (GV) responses of the III-V/Ge MOS devices can lead to better assessments of the oxide-semiconductor material systems and more accurate performance predictions.

Photoemission study of fully silicided Pd2Si gates with interface modification induced by dopants

Work function shifts for fully silicided (FUSI) Pd2Si gates with BF2 and P predoping, originally observed as the flatband voltage shifts in metal-oxide-semiconductor (MOS) diodes, were also reproducible for backside x-ray photoelectron spectroscopy measurements. The Pd composition ratios of FUSI layers were reduced in the vicinity of the gate SiO2 layer, which directly affects apparent work function in the MOS system. However, other non-negligible changes, such as pileup of predoped elements and Pd precipitation, were also found for the predoped cases. The work function shift by predoping should be considered to be a result of interaction of such multiple factors.

A comparison of older and newer versions of intraoral digital radiography systems: Diagnosing noncavitated proximal carious lesions

The authors conducted a study to compare the accuracy of an older and newer version of two intraoral digital systems in terms of radiographic detection of proximal carious lesions. Under in vitro and standardized conditions, the authors obtained radiographs of 160 noncavitated proximal surfaces using the Digora FMX (Soredex, Tuusula, Finland), the Digora Optime, the Schick CDR (Schick Technologies, Long Island City, N.Y.) and the Schick CDR Wireless (Schick Technologies) systems. Eight observers recorded proximal carious lesions on a five-point confidence scale. The presence of caries was validated histologically. The new digital systems (Digora Optime and Schick CDR Wireless) had significantly higher sensitivities than their predecessors. The authors found no significant differences in specificity among the Digora FMX, Schick CDR and Schick CDR Wireless systems, all of which had a significantly higher specificity than did the Digora Optime system (P < .02). The positive predictive value for the Digora Optime system was affected by its high sensitivity and low specificity, and it was lower than that for the two CDR systems (P < .02). Regarding overall accuracy, the difference between the older and newer versions of the photostimulable storage phosphor and complementary metal oxide semiconductor systems was not statistically significant. However, the authors found more false-positive diagnoses made with the Digora Optime system than with the Digora FMX system. Though the difference in specificities was statistically significant, the authors question whether the difference between the Digora Optime and the other systems is clinically relevant. Therefore, dentists can purchase any of these systems after considering factors other than those evaluated in this study.