Metal-oxide-semiconductor High Electron Mobility Transistors Research Articles

DC and RF Performance of AlGaN/GaN/SiC MOSHEMTs With Deep Sub-Micron T-Gates and Atomic Layer Epitaxy MgCaO as Gate Dielectric

In this letter, we report on the dc and RF performance of AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOSHEMTs) with various gate lengths ( ${L}_{\mathsf {G}}$ ) from 90 to 500 nm using atomic-layer-epitaxy single crystalline Mg0.25Ca0.75O as gate dielectric. The 90-nm T-gate MOSHEMT simultaneously demonstrates a ft/fmax of 113/160 GHz with high on/off ratio of $5\times 10^{8}$ . The on/off ratio increases to $2\times 10^{11}$ at ${L}_{\mathsf {G}}=350$ nm by reducing short channel effects. The gate leakage current is around 10−11 A/mm at off-state and 10−5 A/mm at on-state. A 160 nm ${L}_{\mathsf {G}}$ MOSHEMT also exhibits an output power density of 4.18 W/mm at ${f} = 35$ GHz and ${V}_{\mathsf {DS}}=20$ V. MgCaO demonstrates to be a promising dielectric for GaN MOS technology in serving as the surface passivation layer and reducing the gate leakage current while maintaining high RF performances for high-power applications.

Microwave frequency small-signal equivalent circuit parameter extraction for AlInN/GaN MOSHEMT

This article presents an accurate and efficient extraction procedure for microwave frequency small-signal equivalent circuit parameters of AlInN/GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMT). The parameter extraction technique is based on the combination of conventional and optimization methods using the computer-aided modeling approach. The S-, Y-, and Z- parameters of the model are extracted from extensive dynamic AC simulation of the proposed device. From the extracted Y- and Z- parameters the pad capacitances, parasitic inductances and resistances are extracted by operating the device at low and high frequency pinch-off condition depending upon requirement. Then, the intrinsic elements are extracted quasi analytically by de-embedding the extrinsic parameters. S-parameter simulation of the developed small-signal equivalent circuit model is carried out and is compared with TCAD device simulation results to validate the model. The gradient based optimization approach is used to optimize the small-signal parameters to minimize the error between developed SSEC model and device simulation based s-parameters. The microwave characteristics of optimized SSEC model is carried out (fT = 169 GHz and fmax = 182 GHz) and compared with experimental data available from literature to validate the model.

Current linearity and operation stability in Al2O3-gate AlGaN/GaN MOS high electron mobility transistors

To investigate current linearity and operation stability of metal–oxide–semiconductor (MOS) AlGaN/GaN high electron mobility transistors (HEMTs), we have fabricated and characterized the Al2O3-gate MOS-HEMTs without and with a bias annealing in air at 300 °C. Compared with the as-fabricated (unannealed) MOS HEMTs, the bias-annealed devices showed improved linearity of ID–VG curves even in the forward bias regime, resulting in increased maximum drain current. Lower subthreshold slope was also observed after bias annealing. From the precise capacitance–voltage analysis on a MOS diode fabricated on the AlGaN/GaN heterostructure, it was found that the bias annealing effectively reduced the state density at the Al2O3/AlGaN interface. This led to efficient modulation of the AlGaN surface potential close to the conduction band edge, resulting in good gate control of two-dimensional electron gas density even at forward bias. In addition, the bias-annealed MOS HEMT showed small threshold voltage shift after applying forward bias stress and stable operation even at high temperatures.

Evaluation of AlGaN/GaN metal–oxide–semicondutor high-electron mobility transistors with plasma-enhanced atomic layer deposition HfO2/AlN date dielectric for RF power applications

A plasma enhanced atomic layer deposition (PEALD) HfO2/AlN dielectric stack was used as the gate dielectric for AlGaN/GaN metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) for high-frequency power device applications. The capacitance–voltage (C–V) curves of the HfO2/AlN/GaN MOS capacitor (MOSCAP) showed a small frequency dispersion along with a very small hysteresis (∼50 mV). Moreover, the interface trap density (Dit) was calculated to be 2.7 × 1011 cm−2 V−1 s−1 at 150 °C. Using PEALD-AlN as the interfacial passivation layer (IPL), the drain current of the HfO2/AlN MOS-HEMTs increased by about 46% and the gate leakage current decreased by six orders of magnitude as compared with those of the conventional Schottky gate AlGaN/GaN HEMTs processed using the same epitaxial wafer. The 0.3-µm-gate-length HfO2/AlN/AlGaN/GaN MOS-HEMTs demonstrated a 2.88 W/mm output power, a 23 dB power gain, a 30.2% power-added efficiency at 2.4 GHz, and an improved device linearity as compared with the conventional AlGaN/GaN HEMTs. The third-order intercept point at the output (OIP3) of the MOS-HEMTs was 28.4 as compared with that of 26.5 for the conventional GaN HEMTs. Overall, the MOS-HEMTs with a HfO2/AlN gate stack showed good potential for high-linearity RF power device applications.

GaN MOSHEMT employing HfO2 as a gate dielectric with partially etched barrier

In order to suppress the gate leakage current of a GaN high electron mobility transistor (GaN HEMT), a GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) is proposed, in which a metal-oxide-semiconductor gate with high-dielectric-constant HfO2 as an insulating dielectric is employed to replace the traditional GaN HEMT Schottky gate. A 0.5 μm gate length GaN MOSHEMT was fabricated based on the proposed structure, the barrier layer is partially etched to produce a higher transconductance without deteriorating the transport characteristics of the two-dimensional electron gas in the channel, the gate dielectric is HfO2 deposited by atomic layer deposition. Current-voltage characteristics and radio frequency characteristics are obtained after device preparation, the maximum current density of the device is 900 mA mm−1, the source-drain breakdown voltage is 75 V, gate current is significantly suppressed and the forward gate voltage swing range is about ten times higher than traditional GaN HEMTs, the GaN MOSHEMT also demonstrates radio frequency characteristics comparable to traditional GaN HEMTs with the same gate length.

Channel Mobility in GaN Hybrid MOS-HEMT Using SiO2as Gate Insulator

The channel mobility in SiO2/GaN hybrid metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) has been studied. The formalism used for the inversion mobility in MOSFETs has been adapted to the case of GaN MOS-HEMTs, which operate in accumulation condition. Using the values of interface trapped charges ( ${Q}_{{ {\,trap}}} = {1.35} \times {10}^{12}$ cm $^{{ {-2}}}$ ) and surface roughness (RMS = 0.15 nm) determined by capacitance-voltage measurements and nanoscale morphological analyses allowed to derive meaningful physical parameters for the mobility model. The temperature dependence of the peak mobility—that decreases from 110 cm $^{{ {2}}}\text{V}^{ {-1}}\text{s}^{{ {-1}}}$ at room temperature down to 91 cm $^{{ {2}}}\text{V}^{{ {-1}}}\text{s}^{{ {-1}}}$ at 423 K—is mainly ruled by phonon and Coulomb scattering effects. The implications in practical devices were discussed, considering the possible improvement of the device on-resistance that can be obtained by reducing the interfaces state density at the SiO2/GaN interface.

High-Performance GaN MOSHEMTs Fabricated With ALD Al2O3Dielectric and NBE Gate Recess Technology for High Frequency Power Applications

High-performance GaN metal–oxide–semi-conductor high-electron-mobility transistors (MOSHEMTs) using Al2O3 gate dielectric deposited by atomic layer deposition (ALD) and damage-free neutral beam etch (NBE) gate recess process for millimeter-wave power applications are demonstrated. The high-quality ALD Al2O3 reduces the gate leakage current of the device and the NBE method eliminates the plasma-induced defects in the nitride materials. The MOSHEMT device fabricated exhibits a high maximum drain current density ( ${I}_{\textsf {DS,max}}$ ) of 1.65 A/mm and a high peak extrinsic transconductance ( ${g}_{\textsf {m.ext}}$ ) of 653 mS/mm. The MOSHEMT device also demonstrates excellent RF performances, including ${f}_{T}/{f}_{\textsf {MAX}}= 183$ /191 GHz, NF $_{\textsf {min}}= 2.56$ dB with ${G}_{\textsf {AS}}= 5.61$ dB at 54 GHz, and an output power density of 2.7 W/mm associated with a power-added efficiency of 20.9% and a linear power gain of 9.4 dB at 38 GHz. To the best of our knowledge, the noise performance at 54 GHz is the best reported so far for the AlGaN/GaN HEMTs.

Normally-off AlGaN/GaN MOS-HEMT using ultra-thin Al0.45Ga0.55N barrier layer

In this work, we report on the fabrication of a normally-off AlGaN/GaN Metal–Oxide–Semiconductor High Electron Mobility Transistor (MOS-HEMT) using an ultra-thin Al0.45Ga0.55N barrier layer. The AlGaN barrier was thinned down to 1 nm using a digital etching process (Oxidation/Etching) and was followed by a PECVD deposition technique of a 7 nm thick SiOx layer used as gate insulator. Thanks to the thin AlGaN barrier layer (4 nm), only a few digital etching cycles are required to shift the threshold voltage toward positive values. The fabricated normally-off device exhibits a pinch-off voltage of +1.1 V, a maximum IDS current of 460 mA mm−1 at VGS = +5 V, an On-state resistance (RON) of 7.8 Ω · mm and an ION/IOFF ratio higher than 109. Moreover, the pulsed IDS–VDS and capacitance–voltage (C–V) curves versus frequency confirm that there is no damage induced by the digital etching process.

Effects of air annealing on DC characteristics of InAlN/GaN MOS high-electron-mobility transistors using atomic-layer-deposited Al2O3

We evaluated the DC characteristics of InAlN/GaN metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) using atomic-layer-deposited (ALD-)Al2O3 by focusing on air annealing to control defect levels in Al2O3 and electronic states at the Al2O3/InAlN interface. We clarified that the transconductance linearity and subthreshold slope were improved by air annealing, indicating a reduction in the number of electronic states at the Al2O3/InAlN interface. Furthermore, the cathodoluminescence study demonstrated that the oxygen-related defects in ALD-Al2O3 were decreased by air annealing. Consequently, we could successfully reduce the threshold voltage shift of InAlN/GaN MOS-HEMTs by using air-annealed ALD-Al2O3.

20 nm high performance novel MOSHEMT on InP substrate for future high speed low power applications

In this work, the DC and RF performance of a 20 nm gate length novel metal oxide semiconductor high electron mobility transistor (MOSHEMT) on InP substrate is studied using Sentaurus TCAD tool. The proposed MOSHEMT device features heavily doped In0.52Ga0.48As source/drain regions, delta doped planes on both sides of the In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel, a multi layer cap and a very thin layer of HfO2 as gate dielectric. The TCAD simulation results obtained at room temperature using physics based carrier transport model indicates that the 20 nm gate length proposed MOSHEMT device is capable of providing a peak drain current of 2860 mA/mm at VDS = 0.6 V and the peak transconductance obtained for the proposed device is 2890 mS/mm. The fT and fmax obtained for the Lg = 20 nm proposed MOSHEMT on InP substrate are 537 GHz and 631 GHz respectively. At 300 K, the measured Hall mobility of the electrons in the quantum well channel is 11620 cm2/V. The on state resistance (RON), subthreshold swing (SS) and drain induced barrier lowering (DIBL) obtained for the Lg = 20 nm proposed InP-MOSHEMT are 105 Ω μm, 160 mV/dec and 178 mV/V respectively. These devices are undoubtedly, the most suitable candidates for future high speed, low power post silicon logic applications.

High Performance Tri-Gate GaN Power MOSHEMTs on Silicon Substrate

We demonstrate high-performance GaN power metal–oxide–semiconductor high electron mobility transistors (MOSHEMTs) on silicon substrate based on a nanowire tri-gate architecture. The common issue of partial removal of carriers by nanowire etching in GaN tri-gate transistors was resolved mainly by optimized tri-gate geometry, including filling factor and trench width. The tri-gate reduced the OFF-state leakage current ( ${I}_{\mathrm{OFF}}$ ) and the subthreshold slope, increased the ON/OFF ratio, and improved the breakdown voltage ( ${V}_{\mathrm {BR}}$ ) of the device. With a gate-to-drain separation ( ${L}_{\mathrm {GD}}$ ) of $5~\mu \text{m}$ , the tri-gate MOSHEMTs exhibited ${V}_{\mathrm {BR}}$ of 792 V at ${I}_{\mathrm{OFF}}$ of $0.3~\mu \text{A}$ /mm, along with a small specific ON-resistance ( ${R}_{\mathrm {ON, SP}}$ ) of $0.91~\pm ~0.08~\text{m}\Omega \cdot $ cm2. With ${L}_{\mathrm {GD}}$ of $15~\mu \text{m}$ , hard ${V}_{\mathrm {BR}}$ of 1755 V at ${I}_{\mathrm{OFF}}$ of $45~\mu \text{A}$ /mm with high soft ${V}_{\mathrm {BR}}$ of 1370 V at ${I}_{\mathrm{OFF}}= 1\,\,\mu \text{A}$ /mm were achieved, rendering excellent high-power figure of merits (FOMs) up to 1.25 GW/cm2. These results unveil the significant potential of nanostructured GaN transistors for future power applications.

High-performance enhancement-mode Al2O3/InAlGaN/GaN MOS high-electron mobility transistors with a self-aligned gate recessing technology

The paper reports high-performance enhancement-mode MOS high-electron mobility transistors (MOS-HEMTs) based on a quaternary InAlGaN barrier. Self-aligned gate technology is used for gate recessing, dielectric deposition, and gate electrode formation. An improved digital recessing process is developed, and an Al2O3 gate dielectric grown with O2 plasma is used. Compared to results with AlGaN barrier, the fabricated E-mode MOS-HEMT with InAlGaN barrier delivers a record output current density of 1.7 A/mm with a threshold voltage (VTH) of 1.5 V, and a small on-resistance (Ron) of 2.0 Ω·mm. Excellent VTH hysteresis and greatly improved gate leakage characteristics are also demonstrated.

Effects of postdeposition annealing on TiO2/GaN/AlGaN/GaN/Si metal-oxide-semiconductor high-electron mobility transistors

This study presents TiO2/GaN/AlGaN/GaN/Si metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs). The measured direct current, microwave, and power characteristics of the MOS-HEMT are better than for identical geometry HEMT devices. Furthermore, the effects of postdeposition annealing (PDA) in an oxygen environment on the electrical properties of the MOS-HEMTs are investigated. This is the first report of effect of PDA on TiO2 GaN-based MOS-HEMTs. The quality of the TiO2/GaN interface shows significant improvement after annealing. These results clearly establish the potential of annealed TiO2 AlGaN/GaN MOS-HEMTs for high power microwave devices.

Effect of Barrier Thickness on Linearity of Underlap AlInN/GaN DG-MOSHEMTs

In this proposed work, an extensive study on the linearity performance of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) has been analyzed using 2D Sentaurus TCAD simulation. Specifically a brief comparison is made on the linearity and intermodulation distortion characteristics of the proposed device due to variation of barrier layer thickness from 2 nm to 6 nm. Various parameters such as transconductance ([Formula: see text], second-order transconductance ([Formula: see text]), third-order transconductance ([Formula: see text]), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3) and third-order intermodulation distortion (IMD3) of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) are discussed. The simulated results obtained confirms that by careful optimization of barrier layer thickness linearity characteristics of this proposed device can be improved, which can be suitable for analog and circuit applications.

Low-temperature atomic layer deposition-grown Al2O3 gate dielectric for GaN/AlGaN/GaN MOS HEMTs: Impact of deposition conditions on interface state density

The oxide/semiconductor interface state density (Dit) in Al2O3/AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor (MOS-HEMT) structures with gate oxides grown by atomic layer deposition at low deposition temperature is analyzed in this work. MOS-HEMT structures with Al2O3 gate oxide were deposited at 100 and 300 °C using trimethylaluminum precursor and H2O and O3 oxidation agents. The structures were found to show negative net charge at oxide/barrier interface with density (Nint) of 1013 cm−2, which was attributed to the reduction of barrier surface donor density (NDS). Dit was determined using capacitance transient techniques, and the results were assessed by the simulations of the capacitance–voltage characteristics affected by interface traps. The results indicate a lower interface quality of the sample with Al2O3 grown using O3 agent compared to those with H2O, even though the former provided lowest gate leakage among the analyzed structures. Moreover, to uncover the NDS nature, Dit distributions determined here were compared to that reported previously on devices with Nint close to zero, i.e., with fully compensated surface barrier polarization charge by NDS [Ťapajna et al., J. Appl. Phys. 116, 104501 (2014)]. No clear correlation between Dit and NDS was concluded, indicating the nature of NDS to be different from that of interface states in the energy range analyzed here.

Modelling of capacitance and threshold voltage for ultrathin normally-off AlGaN/GaN MOSHEMT

A compact quantitative model based on oxide semiconductor interface density of states (DOS) is proposed for Al0.25Ga0.75N/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT). Mathematical expressions for surface potential, sheet charge concentration, gate capacitance and threshold voltage have been derived. The gate capacitance behaviour is studied in terms of capacitance–voltage (CV) characteristics. Similarly, the predicted threshold voltage (V T) is analysed by varying barrier thickness and oxide thickness. The positive V T obtained for a very thin 3 nm AlGaN barrier layer enables the enhancement mode operation of the MOSHEMT. These devices, along with depletion mode devices, are basic constituents of cascode configuration in power electronic circuits. The expressions developed are used in conventional long-channel HEMT drain current equation and evaluated to obtain different DC characteristics. The obtained results are compared with experimental data taken from literature which show good agreement and hence endorse the proposed model.

Normally-off AlGaN/AlN/GaN/Si oxide-passivated HEMTs and MOS-HEMTs by using CF4 plasma and ozone water oxidization treatment

The letter reports normally-off device characteristics of Al0.26Ga0.74N/AlN/GaN oxide-passivated high electron mobility transistors (HEMTs) and metal-oxide-semiconductor HEMTs (MOS-HEMTs) grown on a Si substrate. Al2O3 was formed as the surface passivation oxide or gate dielectric on a thin AlGaN barrier layer by using a cost-effective ozone water oxidization technique. CF4 plasma was used to enable normally-off operation. For the gate dimensions of 1×100µm2, the present oxide-passivated HEMT and MOS-HEMT (a control Schottky-gate HEMT) have demonstrated superior on/off-current ratio (Ion/Ioff) of 2.5×106 and 1×107 (3.9×103), maximum extrinsic transconductance (gm, max) of 154 and 175 (120) mS/mm, maximum drain-source current density (IDS, max) of 312 and 349 (300) mA/mm, two-terminal gate-drain breakdown voltage (BVGD) of −80 and −140 (−36) V, turn-on voltage (Von) of 1.2 and 1.3 (1) V, and three-terminal on-state breakdown voltage (BVDS) of 93 and 109 (48) V. Excellent BVGD and BVDS enhancements of 122% (288%) and 94% (127%) are achieved in the present oxide-passivated HEMT (MOS-HEMT) design.

Comprehensive characterization of AlGaN/GaN metal‐oxide‐semiconductor high‐electron mobility transistors with TiO2 gate dielectric

AlGaN/GaN metal‐oxide‐semiconductor high‐electron mobility transistors (MOS‐HEMTs) on Si substrates with TiO2 gate dielectrics are fabricated. The dc and power characteristics of AlGaN/GaN MOS‐HEMTs are compared with that of metal‐gate HEMTs fabricated on the same material. The gate leakage current for the MOS‐HFET is more than two orders of magnitude smaller than for the HEMT at 300 K. The high‐speed performance potential of the MOS‐HEMT with an fT = 10.44 GHz and an fmax = 13.8 GHz is confirmed. The MOS‐HEMT shows higher extrinsic transconductance, breakdown voltage, high‐frequency and power characteristics relative to the HEMT. Furthermore, experimental results reveal that this studied MOS‐HEMT is feasible for use at high temperatures.

Effect of thin gate dielectrics on DC, radio frequency and linearity characteristics of lattice‐matched AlInN/AlN/GaN metal–oxide–semiconductor high electron mobility transistor

In this paper, the authors present a polarisation dependent analytical model for DC, radio frequency (RF) and linearity characteristics of a proposed lattice-matched AlInN/AlN/GaN metal–oxide–semiconductor high electron mobility transistor (MOSHEMT). The developed model includes charge controlled analysis derived from triangular potential well approximation along with the spontaneous and piezoelectric polarisation effects. The model accurately predicts the threshold voltage, two-dimensional electron gas sheet charge density, drain current, transconductance and cut-off frequencies for different samples of gate dielectric materials such as SiO2, HfO2 and Al2O3 over a full range of gate and drain bias. A detailed analysis of the linearity characteristics by investigating the key figure-of-merit metrics such as second-order voltage intercept point, third-order voltage intercept point, third-order input intercept point and third-order intermodulation distortion are performed for different gate dielectric thicknesses of 5, 7 and 10 nm. The accuracy of the model results is verified against Silvaco Technology Computer Aided Design numerical simulation results and found to be satisfactory. It is observed that by careful tuning the device parameters such as dielectric constant and dielectric thickness, lattice-matched AlInN/AlN/GaN MOSHEMT can considerably improve the device performance and suitable for high performance low distortion RF applications.

Investigation of Post Oxidation Annealing Effect on H2O2-Grown-Al2O3/AlGaN/GaN MOSHEMTs

This paper investigates the Al2O3/AlGaN/GaN metal–oxide–semiconductor high electron mobility transistor (MOSHEMT) performance with post oxidation annealing (POA) process. First, the optimum annealing condition was found to be 400 °C for 20 min. The transmission electron microscopy, atomic force microscopy, and X-ray photoelectron spectroscopy were used for material analysis. The hysteresis capacitance–voltage ( ${C}$ – ${V}$ ) measurement was also used to characterize the amount of traps at the Al2O3/AlGaN interface. It was found that the amount of the traps reduced after POA process. In addition, the performance of the MOSHEMT like gate leakage current, output current, subthreshold swing, off-state breakdown voltage, frequency response, and power characteristics were improved after POA process.