Metal Oxide Semiconductor Gate Stacks Research Articles

Relaxation kinetics of interface states and bulk traps in atomic layer deposited ZrO2/β-Ga2O3 metal-oxide-semiconductor capacitors

The study of interface states and bulk traps and their connection to device instability is highly demanded to achieve reliable β-Ga2O3 metal-oxide-semiconductor (MOS) devices. However, a comprehensive analysis of the capture/emission behavior of interface states and bulk traps can be challenging due to widespread time constant distribution. In this study, using capacitance transient measurement tools, trap states of the ZrO2/β-Ga2O3 MOS gate stack were explicitly investigated, particularly its bias- and temperature-dependent relaxation kinetics. As forward bias is enlarged, it is observed that the interface state density (Dit) increases by 12.6%. Two bulk traps with discrete levels identified as 0.43 eV (E1) and 0.74 eV (E2) below the conduction band minimum were extracted by deep-level transient spectroscopy. It is further revealed that the emission processes of E1 and E2 are thermally enhanced, while the capture processes remain insensitive to temperature. The electric-field dependence of E1 indicates that the dominant mechanism follows the rule of Poole–Frenkel emission. The capacitance–voltage (C–V) hysteresis deteriorated at a higher forward bias due to the higher trap density and increased population of trapped charges. These findings provide an important framework for future device optimization to improve the reliability and performance of β-Ga2O3 MOS devices.

Fabrication and characterization of a self-aligned gate stack for electronics applications

A metal–oxide–semiconductor (MOS) gate stack that is self-aligned with the underlying silicon doping profile is demonstrated. We combine a new hybrid bottom-up patterning technique with atomic layer deposition (ALD) to selectively deposit a platinum-hafnium dioxide-silicon MOS gate stack. A poly(methyl methacrylate) (PMMA) brush is blanket grown from a Si(100) surface and selectively removed from the lightly doped (∼1018 cm−3) regions using a doping-selective KOH etch. The PMMA brush that remains on the heavily doped (∼1020 cm−3) regions effectively blocks the ALD of both HfO2 and platinum. MOS capacitors exhibit promising capacitance-voltage characteristics with a HfO2 dielectric constant of ∼25 and an average interface state density of 2.1 × 1011 eV−1 cm−2 following forming gas anneal.

InGaN/(GaN)/AlGaN/GaN normally-off metal-oxide-semiconductor high-electron mobility transistors with etched access region

The proposal and processing aspects of the prove-of-concept InGaN/GaN/AlGaN/GaN metal-oxide-semiconductor (MOS) high-electron mobility transistor with etched access regions are addressed. Full strain and decent quality of the epitaxial system comprising 4 nm In0.16Ga0.84N/3 nm GaN/5 nm Al0.27Ga0.73N are observed using a high-resolution transmission-electron microscopy and by deformation profile extractions. Large negative polarization charge in the MOS gate stack provides the HEMT normally-off operation, while free electrons are populated at access regions after etching. Consecutive passivation by 10 nm Al2O3 together with annealing at 300 °C improved the Al2O3/semiconductor interface, with the threshold voltage (VT) reaching 1 V. Improvements of the present concept in comparison to the previous one with a gate recess were proved by showing the decreased drain leakage current and increased breakdown voltage.

Analog reversible nonvolatile memcapacitance in metal-oxide-semiconductor memcapacitor with ITO/HfOx/Si structure

We demonstrate strong, analog, reversible, and nonvolatile memcapacitance in a Si-based MOS (metal-oxide-semiconductor) memcapacitor with an ITO (In-Sn-O)/HfOx/Si structure. Both accumulation and depletion capacitances change sequentially and reversibly upon repeating voltage application with respect to voltage polarity. This memcapacitance is thought to be induced by oxygen ions' migration between ITO and HfOx layers, which changes the HfOx permittivity and the depletion states in Si and ITO. The Si-based memcapacitor has potential to be applied to the gate stack of the MOS field-effect-transistor for nonvolatile memory and synaptic transistors through modulating drain current determined by the capacitance change of the MOS gate stack.

(Invited) Interface and Border Traps, Their Passivation and the Reliability of Alumina Dielectric / Indium Gallium Arsenide Gate Stacks

Both interface defects and border traps - charge traps in the gate oxide - influence the behavior of InGaAs metal-oxide-semiconductor (MOS) devices. This presentation will summarize the different effects of interface and border traps on the temperature- and bias-stress behavior of aluminum oxide/InGaAs MOS gate stacks, and will describe methods for passivating these defects both prior to and after gate dielectric deposition. The influence of local interface chemistry and the complex role of hydrogen as a defect passivant are highlighted. In one set of experiments, a temperature dependent border trap response for Al2O3 gate dielectrics is investigated.1 This behavior is unexpected for defects that have typically been reported to charge and discharge through direct tunneling of electrons from the n-type substrate. Temperature dependent border trap frequency dispersion of the accumulation capacitance and conductance is found to be correlated with the presence of a defective interfacial layer, which can be intentionally produced either by excessive exposure to hydrating or oxidizing species during atomic layer deposition of Al2O3 or by use of a previously-reported aqueous HCl wet clean of the InGaAs surface prior to ALD. These results point out the sensitivity of the temperature dependence of the border trap response in metal oxide/III-V MOS gate stacks to the presence of processing-induced interface oxide layers, which alter the dynamics of carrier trapping at defects that are not located at the semiconductor interface. I also report on the effects of pre- and post-atomic layer deposition (ALD) defect passivation with hydrogen on the trap density and reliability of Al2O3/InGaAs gate stacks.2, 3 Reliability is characterized by capacitance-voltage hysteresis measurements on samples prepared using different fabrication procedures and having different initial trap densities. Despite its beneficial ability to passivate both interface and border traps, a final forming gas (H2/N2) anneal (FGA) step is found to induce a significant hysteresis. This is caused by hydrogen depassivation of defects in the gate stack under bias stress, supported by the observed bias stress-induced increase of interface trap density, and strong hydrogen isotope effects on the measured hysteresis. Additional strategies, beyond hydrogen annealing, for more stable interface defect passivation on InGaAs will be discussed briefly. K. Tang, A.C. Meng, R. Droopad, and P.C. McIntyre, "Temperature Dependent Border Trap Response Produced by a Defective Interfacial Oxide Layer in Al2O3/InGaAs Gate Stacks,” ACS Appl. Mater. Interfaces 8, 30601-07 (2016). K. Tang, F.R. Palumbo, L. Zhang, R. Droopad, and P.C. McIntyre “Interface Defect Hydrogen Depassivation and Capacitance–Voltage Hysteresis of Al2O3/InGaAs Gate Stacks,” ACS Appl. Mater. Interfaces 9, 7819-25 (2017). K. Tang, R. Droopad, and P.C. McIntyre, “Bias Temperature Stress Induced Hydrogen Depassivation from Al2O3/InGaAs Interface Defects,” J. Appl. Phys. 123, 025708 (2018).

Physical and electrical characterizations of AlGaN/GaN MOS gate stacks with AlGaN surface oxidation treatment

The impacts of inserting ultrathin oxides into insulator/AlGaN interfaces on their electrical properties were investigated to develop advanced AlGaN/GaN metal–oxide–semiconductor (MOS) gate stacks. For this purpose, the initial thermal oxidation of AlGaN surfaces in oxygen ambient was systematically studied by synchrotron radiation X-ray photoelectron spectroscopy (SR-XPS) and atomic force microscopy (AFM). Our physical characterizations revealed that, when compared with GaN surfaces, aluminum addition promotes the initial oxidation of AlGaN surfaces at temperatures of around 400 °C, followed by smaller grain growth above 850 °C. Electrical measurements of AlGaN/GaN MOS capacitors also showed that, although excessive oxidation treatment of AlGaN surfaces over around 700 °C has an adverse effect, interface passivation with the initial oxidation of the AlGaN surfaces at temperatures ranging from 400 to 500 °C was proven to be beneficial for fabricating high-quality AlGaN/GaN MOS gate stacks.

(Invited) Charge Traps, Temperature- and Bias-Stress Stability of Alumina Dielectric / Indium Gallium Arsenide Gate Stacks

Both interface defects and border traps - charge traps in the gate oxide - influence the behavior of InGaAs metal-oxide-semiconductor (MOS) devices. This presentation will summarize the different effects of interface and border traps on the temperature- and bias-stress behavior of aluminum oxide/InGaAs MOS gate stacks, with particular emphasis on threshold voltage stability. The influence of local interface chemistry and the complex role of hydrogen as a defect passivant are highlighted. In one set of experiments, a temperature dependent border trap response for Al2O3 gate dielectrics is investigated. This behavior is unexpected for defects that have typically been reported to charge and discharge through direct tunneling of electrons from the n-type substrate. Temperature dependent border trap frequency dispersion of the accumulation capacitance and conductance is found to be correlated with the presence of a defective interfacial layer, which can be intentionally produced either by excessive exposure to hydrating or oxidizing species during atomic layer deposition of Al2O3 or by use of a previously-reported aqueous HCl wet clean of the InGaAs surface prior to ALD. These results point out the sensitivity of the temperature dependence of the border trap response in metal oxide/III-V MOS gate stacks to the presence of processing-induced interface oxide layers, which alter the dynamics of carrier trapping at defects that are not located at the semiconductor interface. We also report on the effects of pre- and post-atomic layer deposition (ALD) defect passivation with hydrogen on the trap density and reliability of Al2O3/InGaAs gate stacks. Reliability is characterized by capacitance-voltage hysteresis measurements on samples prepared using different fabrication procedures and having different initial trap densities. Despite its beneficial ability to passivate both interface and border traps, a final forming gas (H2/N2) anneal (FGA) step is found to induce a significant hysteresis. This is caused by hydrogen depassivation of defects in the gate stack under bias stress, supported by the observed bias stress-induced increase of interface trap density, and strong hydrogen isotope effects on the measured hysteresis. Additional strategies, beyond hydrogen annealing, for more stable interface defect passivation on InGaAs will be discussed briefly.

HfxAlyO ternary dielectrics for InGaAs based metal-oxide-semiconductor capacitors

The electrical properties of HfxAlyO compound dielectric films and the HfxAlyO/InGaAs interface are reported for various dielectric film compositions. Despite the same trimethylaluminum (TMA) pre-deposition treatment, dispersion in accumulation and capacitance-voltage (C-V) hysteresis increased with hafnium content. Different kinds of border traps were identified as being responsible for the phenomena. After anneal, the density of states in the HfxAlyO/InGaAs interface varied quite weakly with dielectric film composition. The optimal composition for obtaining high inversion charge density in metal oxide semiconductor gate stacks is determined by a tradeoff between leakage and dielectric constant, with the optimum atomic cation ratio ([Hf]/[Al]) of ∼1.

Temperature Dependent Border Trap Response Produced by a Defective Interfacial Oxide Layer in Al2O3/InGaAs Gate Stacks.

Intentional oxidation of an As2-decapped (100) In0.57Ga0.43As substrate by additional H2O dosing during initial Al2O3 gate dielectric atomic layer deposition (ALD) increases the interface trap density (Dit), lowers the band edge photoluminescence (PL) intensity, and generates Ga-oxide detected by X-ray photoelectron spectroscopy (XPS). Aberration-corrected high resolution transmission electron microscopy (TEM) reveals formation of an amorphous interfacial layer which is distinct from the Al2O3 dielectric and which is not present without the additional H2O dosing. Observation of a temperature dependent border trap response, associated with the frequency dispersion of the accumulation capacitance and conductance of metal-oxide-semiconductor (MOS) structures, is found to be correlated with the presence of this defective interfacial layer. MOS capacitors prepared with additional H2O dosing show a notable decrease (∼20%) of accumulation dispersion over 5 kHz to 500 kHz when the measurement temperature decreases from room temperature to 77 K, while capacitors prepared with an abrupt Al2O3/InGaAs interface display little change (<2%) with temperature. Similar temperature-dependent border trap response is also observed when the (100) InGaAs surface is treated with a previously reported HCl(aq) wet cleaning procedure prior to Al2O3 ALD. These results point out the sensitivity of the temperature dependence of the border trap response in metal oxide/III-V MOS gate stacks to the presence of processing-induced interface oxide layers, which alter the dynamics of carrier trapping at defects that are not located at the semiconductor interface.

Negative Capacitance in Organic/Ferroelectric Capacitor to Implement Steep Switching MOS Devices.

Because of the "Boltzmann tyranny" (i.e., the nonscalability of thermal voltage), a certain minimum gate voltage in metal-oxide-semiconductor (MOS) devices is required for a 10-fold increase in drain-to-source current. The subthreshold slope (SS) in MOS devices is, at best, 60 mV/decade at 300 K. Negative capacitance in organic/ferroelectric materials is proposed in order to address this physical limitation in MOS technology. Here, we experimentally demonstrate the steep switching behavior of a MOS device-that is, SS ∼ 18 mV/decade (much less than 60 mV/decade) at 300 K-by taking advantage of negative capacitance in a MOS gate stack. This negative capacitance, originating from the dynamics of the stored energy in a phase transition of a ferroelectric material, can achieve the step-up conversion of internal voltage (i.e., internal voltage amplification in a MOS device). With the aid of a series-connected negative capacitor as an assistive device, the surface potential in the MOS device becomes higher than the applied gate voltage, so that a SS of 18 mV/decade at 300 K is reliably observed.

The physical origin of dispersion in accumulation in InGaAs based metal oxide semiconductor gate stacks

Dispersion in accumulation is a widely observed phenomenon in technologically important InGaAs gate stacks. Two principal different interface defects were proposed as the physical origin of this phenomenon—disorder induced gap states and border traps. While the gap states are located at the semiconductor side of the interface, the border traps are related to the dielectric side. The study of Al2O3, HfO2, and an intermediate composition of HfxAlyO deposited on InGaAs enabled us to find a correlation between the dispersion and the dielectric/InGaAs band offset. At the same time, no change in the dispersion was observed after applying an effective pre-deposition treatment which results in significant reduction of the interface states. Both observations prove that border traps are the physical origin of the dispersion in accumulation in InGaAs based metal-oxide-semiconductor gate stacks.

Impact of metal gate electrodes on electrical properties of InGaAs MOS gate stacks

• Gate electrode metals have impacts on gate dielectrics and interface properties. • MOS capacitors with Pd gate electrode can provide thinnest CET. • Pd gate electrode provides better MOS interface properties in HfO 2 /InGaAs. Electrical properties of Al 2 O 3 and HfO 2 /InGaAs metal–oxide–semiconductor (MOS) capacitors with Al, Au and Pd gate electrodes have been evaluated in order to study the impact of metal gate electrodes on gate dielectrics and interface properties. It is found that MOS capacitors with Pd gate electrode can provide thinnest capacitance-equivalent-thickness (CET) and better HfO 2 /InGaAs MOS interfaces than those with Al and Au. However, the Al 2 O 3 /InGaAs interface properties are better in Au and Al gate electrodes than in Pd. Thus, the combination of high- k and gate metals must be carefully examined for realizing optimum gate stacks.

Gate stack dielectric degradation of rare-earth oxides grown on high mobility Ge substrates

We report on the reliability characteristics and their analysis, of rare-earth oxides (REOs) dielectric degradation, when used as interfacial buffer layers together with HfO2 high-k films (REOs/HfO2) on high mobility Ge substrates. Metal-oxide-semiconductor (MOS) devices with these stacks, show dissimilar charge trapping phenomena under varying levels of constant-voltage-stress (CVS) conditions, influencing the measured densities of the interface (Nit) and border (NBT) traps. In the present study, we report on C-Vg hysteresis curves related to both Nit and NBT. We propose a new model based on the Maxwell-Wagner mechanism, and this model explains the current decay transient observed under CVS bias from low to higher fields of MOS gate stack devices grown on Ge substrates. The proposed model is unlike to those used for other MOS devices. Finally, CVS measurements for very long times at moderate fields reveal an initial current decay due to relaxation, followed by charge trapping and generation of stress-induced leakage which eventually lead to hard breakdown.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

Second-harmonic generation reveals the oxidation steps in semiconductor processing

Monitoring oxidation steps is an important factor during the fabrication of semiconductor devices, because transistor performance can be greatly affected by defects in the passivation layer. As an example, we discuss the formation of a gate stack in metal oxide semiconductor (MOS) devices using Ge as an alternative channel material. Building an MOS gate stack on Ge requires passivation of the interface between the dielectric (typically a high-k material such as Al2O3 or HfO2, grown by means of atomic layer deposition (ALD)) and the Ge channel. Such passivation can be obtained from a very thin Si layer, epitaxially grown on Ge. The Si surface receives an oxidizing clean (O3 or wet chemical clean) before the ALD step. In this work, second-harmonic generation (SHG) data are presented for silicon layers with varying thickness, grown with either trisilane (Si3H8) or silane (SiH4) and with various cleaning steps. The trend in second-harmonic response upon azimuthal rotation of the samples was comparable for both silane and trisilane as a Si precursor. Our results show that upon oxidation, the SHG intensity reduces, most likely due to a reduction of the amount of crystalline Si, which is converted to SiO2.

Preparation of Native Oxide and Carbon-Minimized Ge Surface by NH4OH -Based Cleaning for High-k ∕ Ge MOS Gate Stacks

The native oxide and carbon-contaminant-minimized Ge surface with ammonium hydroxide -based cleaning for high- metal-oxide-semiconductor (MOS) gate stack application is reported. Furthermore, the carbon-free interfacial Ge-oxide layer preparation on the cleaned Ge surfaces was also studied. The thickness of on Ge surface before, during, and after different cleaning processes was evaluated by the spectroscopic ellipsometry measurements. The HF rinsing step in the cyclic HF∕deionized water cleaning was not effective for a removal of native because it cannot form the soluble species by a chemical reaction in the low pH HF solution. A cyclic -based cleaning results in a minimum residual at 3 and on Ge(111) and (100), respectively. The fast regrowth of on cleaned Ge surfaces under air exposure was observed, regardless of the cleaning methods. However, Auger electron spectroscopy spectra showed less amount of carbon on Ge surfaces with -based cleaning than HF-based cleaning. The small amount of residual carbon after -based wet cleaning was completely removed by plasma for a very thin surface oxidation in the remote plasma-enhanced chemical vapor deposition chamber.

Effective work function engineering by lanthanide ion implantation of metal-oxide semiconductor gate stacks

While the debate about the exact cause of Fermi level pinning in metal-high-k dielectric gate stacks is ongoing, several solutions for engineering the threshold voltage Vt of the gate stacks have been proposed. Engineering the flat-band voltage Vfb translates into an effective control of the threshold voltage. This study uses ion implantation as a tool to adjust Vfb by doping the gate stack. It is shown that lanthanide implantation can modulate the effective work function for n-type gate electrodes. Ion implantation of dysprosium (Dy) and lanthanum (La) into the gate stack achieves significant flat-band voltage shifts of about −1 and −3V, respectively, for a dose of 1×1014cm−2. By increasing the implantation dose and energy, larger shifts in the flat-band voltage are obtainable.

Maximizing performance for higher K gate dielectrics

Further scaling of complementary metal oxide semiconductor gate stacks will require gate dielectrics with a higher dielectric constant (K) than HfO2. We point out that this will require strategies to minimize the overall effective oxide thickness of the gate stack, and not just maximizing the dielectric constant, so that the channel mobility is not impaired and there is still control of the flatband voltages. This may require retention of a SiO2-based interfacial layer, and attention should be paid to the flatband voltages of lanthanide oxides. Phase control of HfO2 and ZrO2 by addition of group IV elements offers simpler advances.

High-K dielectrics for the gate stack

This article gives an overview of recent developments in the search for the next-generation dielectric for the complementary metal-oxide semiconductor gate stack. After introducing the main quantities of interest, the paper concentrates on a figure of merit that connects two main properties of the gate stack, namely, the leakage current and the capacitance. This is done for single layers as well as for bilayers consisting of interfacial SiOx and a high-K dielectric. In the case of the bilayers, the impact of the interfacial layer SiOx is enormous, reducing the leakage current by an order of magnitude per monolayer. This extreme dependance makes a good correlation between the leakage and the structural parameters nearly impossible. This is illustrated using numerical examples designed to help the reader evaluate the orders of magnitude involved. The origin of the interfacial layer is traced back by means of thermodynamic considerations. As the estimates put forward in the literature do not correspond to the results observed, a detailed review is made, and additional mechanisms are suggested. By using reasonable values for the Gibbs free energy of an interfacial solid silicon oxide phase it is demonstrated how the reaction equilibria shift. Such an interface phase may fundamentally change the stability criteria of oxides on Si. Furthermore, it can also provide a major source of electronic defects that will affect the device performance. Finally, a second figure of merit is introduced that connects the capacitance with a strongly reduced carrier mobility, which might also be related to the same electronic defects.

Nanoscopic versus macroscopic C– V characterization of high- κ metal-oxide chemical vapor deposition ZrO 2 thin films

In this paper we compare macroscopic C– V-measurements with (local) scanning capacitance (SCM) measurements to extract electrical parameters. In future microelectronic CMOS devices, high- κ dielectrics, primarily as gate oxides, will play an important role. The characterization of their electrical behaviour is one key issue to evaluate their suitability. We deposited zirconium dioxide (ZrO 2) thin films by metal–organic chemical vapor deposition (MOCVD) on (1 0 0)-silicon substrates to fabricate metal oxide semiconductor gate stacks. These devices were evaluated by conventional C( V) characterization using a probing station. Additionally, we applied a new C( V)-characterization method, allowing to determine electrical characteristics of nm-thick dielectric films on a nanoscopic scale. This method enabled us to directly compare the nanoscopic and macroscopic measurements. As a result, local and global measurements turned out to be consistent. A comparison of our ZrO 2high- κ layers with thermal SiO 2 films indicate a superior behaviour of MOCVD grown ZrsO 2 film.