Metal-oxide Semiconductor Field-effect Transistor Structure Research Articles

Innovations in thin‐film electronics for the new generation of displays

AbstractToday's display industry faces transistor‐level challenges similar to those of complementary metal‐oxide semiconductor (CMOS) metal‐oxide semiconductor field‐effect transistors (MOSFETs) in the mid‐1990s. Learnings from MOSFETs inform the display industry's response to the limitations of silicon‐based thin‐film transistors (TFTs). Improvements sustaining Moore's Law drove the need to rethink MOSFET materials and structures. The display industry needs fundamental innovation at the device level. New thin‐film devices enable an inflection point in the use of displays, just as fin field‐effect transistor (FinFET) defined the inflection point in CMOS in the 2000s. This paper outlines two innovations in thin‐film device technology that offers improvement in image quality and power consumption of flat panel displays: amorphous metal gate TFTs (AMeTFTs) and amorphous metal nonlinear resistors (AMNRs). Linked through a single core material set based on mass‐producible, thin‐film amorphous metals, these two innovations create near‐ and long‐term roadmaps simplifying the production of high‐image quality, low‐power consumption displays on glass (now) and plastic (future). In particular, the field‐effect mobility of indium gallium zinc oxide (IGZO) AMeTFTs (55–72 cm2/Vs) exceeds that of IGZO TFTs developed by existing display manufacturers without the need for atomic layer deposition or vertical stacking of heterostructure semiconductor films, making AMeTFTs a natural choice for the new G8.5–G8.7 fabs targeting IGZO backplanes.

Establishment of analytical model for electrostatic discharge gate-to-source capacitance of power metal-oxide-semiconductor field-effect transistor

In the actual human body model (HBM) test, it is found that the electrostatic discharge (ESD) test results of various power metal-oxide-semiconductor field-effect transistor (MOSFET) devices show asymmetry between forward withstand voltage and reverse withstand voltage, while the ESD process does not distinguish between positive direction and negative direction. Large differences between forward and reverse withstand voltages are unacceptable for power MOSFETs or as ESD protection devices. The problem of its causing device failure is particularly pronounced. In this work, by establishing the analytical model of gate-to-source capacitance of SGT-MOSFET, VUMOSFET and VDMOS under the forward and reverse voltages, we comparatively analyze the reasons for the asymmetry of the forward and reverse withstand voltages and their different ratios of the three kinds of power MOSFETs, which provides a theoretical basis for testing the device’s ESD and the analyzing their reliability. It is found that the ESD forward and reverse withstand voltage asymmetry phenomena of different power MOSFET structures are related to the variation of gate-to-source capacitance, caused by the reverse-type layer. When a forward voltage is applied across the gate and source, the device gate-to-source capacitance consists of the oxide layer capacitance around the gate in parallel; when a reverse voltage is applied, the gate-to-source capacitance consists of the virtual gate-to-drain capacitance in series with the inverse layer capacitance and then in parallel with the other oxide layer capacitance around the gate. This results in a decrease of the gate-to-source capacitance at the reverse voltage, making the device reverse withstand voltage greater than the forward withstand voltage. The difference in the ratio of ESD reverse withstand voltage to forward withstand voltage among different devices is related to the change of the capacitance of the inverse layer in the gate-to-source capacitor under reverse voltage caused by the difference in device structure.

Electrical properties of a low-temperature fabricated Ge-based top-gate MOSFET structure with epitaxial ferromagnetic Heusler-alloy Schottky-tunnel source and drain

We show electrical properties of a Ge-based top-gate metal-oxide-semiconductor field-effect transistor (MOSFET) structure with epitaxial ferromagnetic Heusler alloy/Ge Schottky-tunnel contacts, fabricated with a low-temperature gate-stack process. For shaping the Ge-MOSFET with the ferromagnetic source and drain (S/D) contacts, we use a combination process of Ar+ ion milling and reactive ion etching (RIE). As a consequence of the formation of a gate stack (SiO2/GeO2) using a process temperature of 240 °C, we demonstrate inversion channel MOSFETs with a low gate-voltage operation (VG ∼5 V). Furthermore, we achieve a relatively high field-effect mobility (μFE) of ∼300 cm2/Vs compared to those in a Si-based back-gate spin-MOSFET reported previously [Phys. Rev. B 102, 035305 (2020).]. This study will open a way for developing a Ge-based top-gate spin-MOSFET on the Si platform.

High Performance 3.3 kV SiC MOSFET Structure with Built-In MOS-Channel Diode

Built-in freewheeling diode metal–oxide–semiconductor field-effect transistors (MOSFETs) that ensure high performance and reliability at high voltages are crucial for chip integration. In this study, a 4H–SiC built-in MOS-channel diode MOSFET with a center P+ implanted structure (CIMCD–MOSFET) is proposed and simulated via technology computer-aided design (TCAD). The CIMCD–MOSFET contains a P+ center implant region, which protects the gate oxide edge from high electric field crowding. Moreover, the region also makes it possible to increase the junction FET (JFET) and N-drift doping concentration of the device by dispersing the high electric field. Consequently, the CIMCD–MOSFET is stable even at a high voltage of 3.3 kV without static degradation and gate oxide reliability issues. The CIMCD–MOSFET also has higher short-circuit withstanding capability owing to the low saturation current and improved switching characteristics due to the low gate-drain capacitance, compared to the conventional MOSFET (C–DMOSFET) and the built-in Schottky barrier diode MOSFET (SBD–MOSFET). The total switching time of a CIMCD–MOSFET is reduced by 52.2% and 42.2%, and the total switching loss is reduced by 67.8% and 41.8%, respectively, compared to the C–DMOSFET and SBD–MOSFET.

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET) structure with side-wall p-type pillar (p-pillar) and wrap n-type pillar (n-pillar) in the n-drain was investigated by utilizing Silvaco TCAD simulations. The optimized structure mainly includes a p+ buried region, a light n-type current spreading layer (CSL), a p-type pillar region, and a wrapping n-type pillar region at the right and bottom of the p-pillar. The improved structure is named as SNPPT-MOS. The side-wall p-pillar region could better relieve the high electric field around the p+ shielding region and the gate oxide in the off-state mode. The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance (R on,sp). As a result, the SNPPT-MOS structure exhibits that the figure of merit (FoM) related to the breakdown voltage (V BR) and R on,sp () of the SNPPT-MOS is improved by 44.5%, in comparison to that of the conventional trench gate SJ MOSFET (full-SJ-MOS). In addition, the SNPPT-MOS structure achieves a much faster-witching speed than the full-SJ-MOS, and the result indicates an appreciable reduction in the switching energy loss.

Thickness Modeling of Short-Channel Cylindrical Surrounding Double- Gate MOSFET at Strong Inversion Using Depletion Depth Analysis

Aims: The semiconductor technology has a great impact on consistent growth in the Very-Large- Scale Integrated (VLSI) devices. The transistor size has been scaled down from micron to submicron and towards the nanometer regime in the past 30 years due to technological advancements. The most reliable solid-state device is Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) but this rapid decrease in the device dimensions with the advent of Moore's law follows several problems, such as Short Channel Effects (SCE's) and Hot Carrier Effects. The channel becomes too small at short channel effects that necessitate the analysis of the optimum device designs, in particular in the operating conditions. The charge-sheet model that can quickly analyze a long-channel device, currently in the subthreshold to saturation regime without any discontinuity, turns out to be inappropriate at reduced channel size. Objectives: At the nano-scaling of the device, since the accumulation layer thickness is comparable to the device, the assumption of the channel as a thin sheet of charge vanishes. Though the depletion layers or zone are the regions of the absentia of charges mostly, the existence affects the device behavior and the channel thickness. Therefore, channel thickness modeling becomes essential at various bias conditions to define the specifics of device operation and the channel dependence of the structural parameters. In this work, the objective is to develop an analytical model and numerical analysis of the Cylindrical Surrounding Double-Gate (CSDG) MOSFET, including the thickness, derived based on the formation of depletion depth to analyze the device performance at reducing dimensions. Methods: The analysis is built upon the device's physical and electrical parameters, such as capacitance, electric field, thickness, threshold voltage, effective channel dimensions, drain current, are considered in this research. The depletion region in a MOSFET structure accounts for the inclusion of the source and drain depletion regions, divided primarily into three separate sub-regions as a junction between the diffused source/drain and the substrate depletion under the channel and by region induced by lateral source and drain diffusion. The condition of a planar MOSFET in channel formation, i.e., for strong inversion, and when VGS > VTH has been considered for this mathematical analysis. Results: The computed results of device thickness and depending parameters for a planar MOSFET and the CSDG MOSFET have been obtained. Based on this analysis, the silicon thickness of the typical CSDG MOSFET computed is 180 nm, 281 nm, and 327 nm at VDS 0.2 V, 0.8 V, and 1.2 V, respectively. The achieved results, through the thickness modeling proposed in this work, show that nanoscale CSDG MOSFET can be deployed for the improvements in the device performance and novel design modifications. Conclusion: The analysis presented in this work significantly contributes to understanding the dependence of semiconductor thickness in CSDG MOSFET and serves as a guide for future modifications in the structure for the device compactness.

Impact of source doping profile on the performance of CNT TFETs and MOSFETs: design aspects for fabrication tolerance

In this work, the effect of the source doping profile due to possible fabrication aspects has been investigated and discussed for both carbon nanotube tunneling field effect transistors (TFETs) and metal oxide semiconductor field effect transistors (MOSFETs). A quantum 2D simulator, which is based on self-consistent solution of non-equilibrium Green’s function and Poisson’s equation, is utilized. It has been found that the source doping gradient remarkably affects the drain current, especially in the case of TFET. This raises the need for fabrication precautions and design to retain higher ON-state current. Besides, the high frequency behavior of TFET and MOSFET structures is inspected in terms of cut-off frequency f T. It is found that the source doping profile has a more significant impact on TFETs than on MOSFETs. For better performance, source doping needs to be abrupt. However, with a small source-gate underlapping, degradations due to gradual doping can be reduced. It is also found that a TFET with source/drain low-k oxide spacer can achieve more immunity to these degradations than the single oxide structure.

Intrinsic switching in Si-doped HfO2: A study of Curie–Weiss law and its implications for negative capacitance field-effect transistor

HfO2-based ferroelectrics are considered a promising class of materials for logic and memory applications due to their CMOS compatibility and ferroelectric figures of merit. A steep-slope field-effect-transistor (FET) switch is a device for logic applications in which a ferroelectric gate stack exploits a stabilized negative capacitance regime capable to differentially amplify the surface potential in a metal–oxide–semiconductor FET structure, resulting in the improvement of the subthreshold swing and overdrive. In a number of relevant studies of negative capacitance, intrinsic (thermodynamic) switching is assumed, since alternative switching scenarios predict undesirable hysteretic responses in logic devices. However, there is little support from the experimental data showing that the polarization reversal in HfO2-based ferroelectrics is really driven by the intrinsic switching mechanism. In this work, polarization hysteresis loops are measured over wide temperature ranges on polycrystalline Si-doped HfO2 (Si:HfO2) capacitors. The analysis herein, which is based on the classic Landau–Ginzburg–Devonshire theory, yields the temperature-dependent dielectric susceptibility values, which fit the Curie–Weiss law. The extrapolated Curie temperature value is in line with the data obtained for other HfO2-based ferroelectrics using different techniques. The work also illustrates a method to evaluate the ferroelectric equivalent negative capacitance value and range of voltages, aiming at study and optimization of a stabilized negative capacitance FET. This study indicates that the intrinsic switching provides an adequate description of the polarization hysteresis in Si:HfO2 films. This confirms the usability of hafnia-based ferroelectrics for negative capacitance logic devices, and the important role that the intrinsic mechanism plays in the dielectric response of these materials.

An Overview on MOSFET Drivers and Converter Applications

—The metal oxide semiconductor field effect transistor (MOSFET) drivers are among the main components for most power electronic applications. Increasing the switching frequency from kHz to MHz levels, MOSFETs' current, power and efficiency expectations are increasing. So it needs to find new solutions to design fast drivers. Some of the outcomes and new applications are now silicon carbide MOSFET applications. The focus of this paper is the power MOSFET gate drive requirements in various switch-mode power conversion applications. So a detailed literature review about MOSFET drivers investigates in this study firstly. There are several different MOSFET structures, but the authors focused on the planar-gate counterparts. Primary system and the switching principle of MOSFET's given in this study. The MOSFET gate driver design principles are presented in more detail in this study. Different proposals and applications for power converters are provided with examples. The drivers evaluated and concluded in all ways.

Energy Storage and Reuse in Negative Capacitance

In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive. During transistor turn-on, the FE releases energy, while the whole system is absorbing energy, and during turn-off, the FE retrieves energy, while the whole system is releasing energy. Capacitor energy is analyzed using two different approaches: static material free energy integrals and transient circuit power integrals. The two results agree within 1%. Energy analysis is also performed for a metal–oxide–semiconductor field-effect transistor structure for two gate lengths, 20 nm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2~\mu \text{m}$ </tex-math></inline-formula> , in an inverter circuit. At 2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> gate length, the values of energy match under these two different approaches with less than a 6% difference. The difference is larger in the 20-nm gate length case due to larger parasitic capacitances, such as gate-to-drain and gate-to-source capacitance, affecting the transient circuit analysis. Even so, most of the energy storage and retrieval benefit is retained even in small size negative capacitance transistors.

Challenges to overcome breakdown limitations in lateral β-Ga2O3 MOSFET devices

In this work, the fabrication of high-performance metal-oxide-semiconductor field-effect transistors (MOSFETs) on Si-doped homoepitaxial layers on (100) Mg-doped semi-insulating β-Ga2O3 substrates is demonstrated. Furthermore, the influence of additional gate and source field-plates is analyzed in regards to the breakdown properties of the MOSFET devices. The comparative study reveals comparable transistor performances of devices with and without field-plates showing maximum drain currents, on/off-current ratios and ON-resistances of ~75 mA/mm, 109 and 110 Ω∙mm, respectively. Moreover, both MOSFET structures show comparable breakdown voltages at around 1200 V which equals an average breakdown field strength of 2 MV/cm emphasizing no influence of the field-plates on the breakdown properties. Analysis of the thin film composition by secondary ion mass spectrometry on the processed β-Ga2O3 wafers indicates an increased concentration of silicon dopants at the interface between epitaxial layer and substrate. Our findings suggest that this might be the current main limitation factor in reaching higher breakdown voltages using field-plated β-Ga2O3 MOSFET devices.

New Insight on Terahertz Rectification in a Metal–Oxide–Semiconductor Field-Effect Transistor Structure

The use of a metal–oxide–semiconductor field-effect transistor (MOS-FET) permits the rectification of electromagnetic radiation by employing integrated circuit technology. However, obtaining a high-efficiency rectification device requires the assessment of a physical model capable of providing a qualitative and quantitative explanation of the processes involved. For a long time, high-frequency detection based on MOS technology was explained using plasma wave detection theory. In this paper, we review the rectification mechanism in light of high-frequency numerical simulations, showing features never examined until now. The results achieved substantially change our understanding of terahertz (THz) rectification in semiconductors, and can be interpreted by the model based on the self-mixing process in the device substrate, providing a new and essential tool for designing this type of detector.

Diode-Less SiC Power Module With Countermeasures Against Bipolar Degradation to Achieve Ultrahigh Power Density

A 3.3-kV diode-less (D-less) SiC power module adopting a “next high power density dual package” (named nHPD2) was developed. Configuring the module with SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) only resulted in the ultrahigh power density. Its rated current of 800 A and power density of 37.7 kVA/cm2 are the highest value achieved among high power modules so far. As a countermeasure against bipolar degradation related to the body diode in the MOSFET structure, a high-throughput screening process was utilized for the first time. To clarify the advantageous features of this module, its characteristics an in comparison with those of a full-SiC module and a conventional silicon module in the same nHPD2 package. In addition, system-level impacts on actual traction inverter operations were simulated by using the evaluated characteristics. To accurately calculate the impacts, the temperature dependence of the SiC modules, which is a remarkable feature of high-voltage SiC devices, was taken into account. The superior performance of the developed D-less SiC power module, namely, low loss, low junction temperature, and high power density capability, was confirmed.

Reduction of the kink effect in a SELBOX tunnel FET and its RF/analog performance

The kink effect in a fully depleted silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) is studied and compared with the results for a SOI metal–oxide–semiconductor field-effect transistor (MOSFET) using a model that is calibrated against experimental results available in literature. A technique for eliminating the kink effect is proposed. The structure with a small gap in the buried oxide, known as the selective buried oxide (SELBOX) structure, is capable of reducing the kink effect. The impact of the kink effect on the device performance for different gap positions, thicknesses, and buried oxide thicknesses is examined. A better current–voltage characteristic is obtained for a position of the gap near the source. The effect of varying the temperature and the presence of a uniform trap charge on the kink effect for the SOI TFET, SOI MOSFET, and SELBOX structures is also studied. Various electrical parameters such as the subthreshold swing and ION/IOFF ratio are investigated for the TFET in the presence and absence of uniform trap charge. Although the SELBOX structure can minimize the kink effect, it is still present for such devices with narrow and wider gaps. Therefore, the gap thickness is optimized based on technology computer-aided design (TCAD) simulations. Furthermore, radio frequency (RF)/analog performance parameters such as the transconductance (gm), cutoff frequency (ft), transconductance generation factor (TGF = gm/ID), transconductance frequency product, gain transconductance frequency product, and 1-dB compression point are investigated using TCAD simulations and compared between the SELBOX MOSFET and SELBOX TFET devices.

Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects

The ITRS predicts that the scaling of planar CMOS (Complementary Metal Oxide Semiconductor) technology will continue till the 22 nm technology node [1] and a possible extension beyond is appealing [2]. In this work, we investigate the effect of electron confinement [3] in nanoscaled transistor channels of 25 nm surface channel Si and 32 nm SOI (Silicon on Insulator) and 15 nm IF (Implant Free) III-V MOSFETs using a self-consistent solution of 1 D Poisson - Schrödinger equation [4,5]. For simulat ion and development with accuracy of nano-scaled of 25 nm gate length Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor), 32 nm SOI Implant Free (IF) MOSFET, and 15nm Implant Free III-V MOSFET transistors, we investigated the bandstructure and quantum confinement effects occurring near the oxide-semiconductor interface inmetal-Oxide-Semiconductor (MOS) structure of Si MOSFET device. These investigation have been carried out using a selfconsistent solution of 1D Poisson-Schrödinger equation across the channel of conventional Si / SOI / III-V MOSFET Transistors. To solve self-consistently 1D Poisson-Schrödinger equations across the channel of a conventional Si, SOI, and an Implant Free III-V MOSFETs to determine the conduction and valence band profiles, electron density, electron sheet density, eigenstate and eigenfunctions in these structures. We present the simulat ion results of conduction band profile, electron density (classical and quantum mechanical), eigenstate and eigenfunctions for Si, SOI and III-V MOSFET structures at two different bias voltages of 0.5 V and 1.0 V. For comparison, we calculate the electron sheet density (quantum mechanically) as a function of the applied gate voltages.

Quasi-3D TCAD modeling of STI radiation-induced leakage currents in SOI MOSFET structure

Quasi-3D model for calculation of radiation leakage currents in modern submicron Silicon-on-Insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) structures is proposed. The solution of a complex 3-dimensional problem is reduced to solving two tasks: 2D modeling of the traditional MOSFET cross-section and 3D modeling of the side parasitic transistor. The radiation-induced leakage current simulation in the 0.35 μm SOI MOSFET structure with taking account ionizing radiation with a dose of up to 500 krad was simulated. The results of the simulation show that in comparison with the traditional fully 3D modeling, which requires 11 hours of computer time, the computer time for the IdVg characteristic was reduced to 71 minutes (i.e. the computer time decreased by 9 times).

The Performance of Operational Amplifiers Consisting of 4H-SiC CMOS After Gamma Irradiation

The operational amplifier was fabricated by 4H-SiC complementary MOS on the same die for sensors installed in nuclear power plants, and it showed over $100\times $ the radiation resistance compared with Si bipolar junction transistors. The closed-loop gain at 50 kGy was 11% lower than it of preirradiation because the allowable output voltage range became small by the threshold voltage degradation of p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs), and the offset voltage became unstable when the gamma integral dose was beyond 30 kGy. To reduce the influence of gamma irradiation, we propose a MOSFETs structure which features both thin gate oxide and field plate electrodes connected to an isolation layer. We evaluated the proposed isolation structure using the single device, and our experiments confirmed that the proposed isolation structure has potential of gamma irradiation resistance of 100 kGy.

Hole Trapping in the NBTI Characteristic of SiC MOSFETs

P-type implanted metal oxide semiconductor capacitors (MOSCAPs) and metal oxide semiconductor field effect transistors (MOSFETs) have been fabricated. The characteristics of hole trapping at the interface of SiO2/SiC are investigated through capacitance-voltage (CV) measurements with different starting voltages. The negative shift voltage ∆Vshift and the hysteresis voltages ∆VH which caused by the hole traps in the MOSCAPs and MOSFETs are extracted from CV results. The results show that the hole traps extracted from MOSCAPs are larger than the that extracted from the threshold voltage shift in the MOSFETs. It suggests holes trapping are the primary mechanism contributing to the NBTI, but not all the holes work. Part of the hole traps are compensation by sufficient electrons in the MOSFET structure.

Static power characteristics of selective buried oxide CMOS devices

AbstractSelective buried oxide (SELBOX) Metal‐Oxide‐Semiconductor Field‐Effect Transistor (MOSFET) structure can be used to reduce the kink effect and self‐heating problems associated with the silicon on insulator (SOI) MOSFET devices while maintaining the advantages of bulk MOSFET. In this paper, static power dissipation of SELBOX structure is investigated and compared with SOI and bulk structures. Various MOSFET structures are simulated and evaluated in terms of their static power dissipation. Only results from 90‐nm Complementary Metal Oxide Semiconductor (CMOS) technology devices are included in this paper. Simulation results using the Silvaco TCAD show that static power dissipation in SELBOX CMOS is similar to that of SOI devices but lower than that of bulk CMOS. Hence, SELBOX structure is found to produce relatively low‐static power dissipation while maintaining high operating speed and reducing self‐heating and kink effect. A mathematical model to describe the static power dissipation in the subthreshold region is also included. Statistical analysis show that the model and fabrication simulation results agree with P &lt; .05 and correlation coefficient of 0.95.

(Keynote) Gallium Oxide Electronics: Beyond SiC and GaN

Ultrawide bandgap (UWBG) semiconductors, which are defined in terms of a bandgap energy larger than those of SiC and GaN, are getting attention as emerging materials. Gallium oxide (Ga2O3) is one of the typical UWBG materials and has attractive material properties represented by an extremely large bandgap of about 4.5 eV [1]. Furthermore, availability of high-quality, large-area native wafers manufactured from bulk single crystals synthesized by melt growth methods is another important material feature of Ga2O3 [2]. In this talk, I will introduce our state-of-the-art Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) and Schottky barrier diode (SBD) technologies developed for applications to power and harsh environment electronics. The first single-crystal Ga2O3 transistors by means of metal-semiconductor FETs were demonstrated in 2011 [3]. As a result of continuous efforts, we developed lateral depletion-mode (D-mode) Ga2O3 MOSFETs with a gate-connected field plate (FP) [4]. The devices showed a large off-state breakdown voltage of 755 V, a large drain current on/off ratio of over nine orders of magnitude, stable device operation at temperatures up to 300°C, and negligible DC–RF dispersion. A high gamma-ray tolerance was also demonstrated for the bulk Ga2O3 channel by virtue of weak radiation effects on their output current and threshold voltage. Lateral enhancement-mode Ga2O3 MOSFETs enabling normally-off operation were fabricated by Si-ion implantation doping in an undoped Ga2O3 layer to form source/drain contacts and access regions [5]. The undoped Ga2O3 channel layer that was fully depleted at thermal equilibrium gave rise to positive threshold voltage. A decent on-state drain current of 1.4 mA/mm and a sufficiently large drain current on/off ratio of six orders of magnitude were also achieved. Recently, our FET development took a step forward to vertical D-mode Ga2O3 MOSFETs. In the device structure, the source was electrically isolated from the drain by a current blocking layer formed by Mg-ion implantation except at an aperture opening for drain current conduction. Despite a large source–drain leakage current due to an imperfect function of the current blocking layer, the drain current modulation by applied gate bias was successfully demonstrated. We have also been developing vertical Ga2O3 SBDs. Ga2O3 FP-SBDs were fabricated on n --Ga2O3 drift layers grown by halide vapor phase epitaxy on n +-Ga2O3 (001) substrates [6]. The illustrative device with a net donor concentration of 1.8×1016 cm-3 exhibited a specific on-resistance of 5.1 mΩ·cm2 and an ideality factor of 1.05 at room temperature. Successful FP engineering resulted in a high breakdown voltage of 1076 V. Note that at the breakdown condition, the peak electric field in the Ga2O3 drift layer was estimated to be over 5 MV/cm, which was much larger than theoretical limits for SiC and GaN. Steady and rapid progress has been made on developing building blocks such as bulk wafers, epitaxial films, and device process techniques for realization of Ga2O3 electronics. We fabricated and characterized relatively simple Ga2O3 MOSFET and SBD structures. Both types of developed devices revealed excellent characteristics and thus demonstrated great potential of Ga2O3. Research and development in the next decade is certainly crucial for the road to industrialization of Ga2O3 electronic devices. This work was partially supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics” (funding agency: NEDO). [1] T. Onuma, S. Saito, K. Sasaki, T. Masui, T. Yamaguchi, T. Honda, and M. Higashiwaki, Jpn. J. Appl. Phys. 54, 112601 (2015). [2] A. Kuramata, K. Koshi, S. Watanabe, Y. Yamaoka, T. Masui, and S. Yamakoshi, Jpn. J. Appl. Phys. 55, 1202A2 (2016). [3] M. Higashiwaki, K. Sasaki, A. Kuramata, T. Masui, and S. Yamakoshi, Appl. Phys. Lett. 100, 013504 (2012). [4] M. H. Wong, K. Sasaki, A. Kuramata, S. Yamakoshi, and M. Higashiwaki, IEEE Electron Device Lett. 37, 212 (2016). [5] M. H. Wong, Y. Nakata, A. Kuramata, S. Yamakoshi, and M. Higashiwaki, Appl. Phys. Express 10, 041101 (2017). [6] K. Konishi, K. Goto, H. Murakami, Y. Kumagai, A. Kuramata, S. Yamakoshi, and M. Higashiwaki, Appl. Phys. Lett. 110, 103506 (2017).