Metal Oxide Semiconductor Devices Research Articles

Temperature dependent growth of ytterbium oxide as gate dielectric on silicon substrate via combination of nitrogen and oxygen ambient

The ongoing trend towards downsizing silicon (Si)-based metal-oxide semiconductor (MOS) devices has led to constraints on the silicon dioxide (SiO2) gate dielectric due to increased leakage current through the thin SiO2. In this study, ytterbium oxide (Yb2O3) as a high dielectric constant (k) gate oxide material was deposited on a Si substrate and subjected to annealing at different temperatures ranging from 400 to 1000oC in a nitrogen-oxygen-nitrogen ambient atmosphere. The successful formation of Yb2O3 was verified using X-ray diffraction (XRD), Fourier transform infrared (FTIR), and ultraviolet–visible (UV–VIS) spectroscopy. The FTIR analysis indicated that Yb2O3 gate dielectrics post-annealing exhibited Yb-O bonding due to oxygen diffusion, as well as N-O bonding and NO3-bonding, demonstrating the formation of a nitrogen barrier at the interface to hinder oxygen diffusion. The optical band gap values of Yb2O3 gate dielectrics post-annealing ranged from 3.092 eV to 3.267 eV. Notably, the Yb2O3 gate dielectric annealed at 800 °C showed no breakdown within the 0–3 V range across all samples. The acquisition of a high k value of 19.40 and a low effective oxide charge (Qeff) of 5.32 x 1011 cm−2, along with the superior I-V characteristics, suggest that the Yb2O3 gate dielectric annealed at 800oC has the potential to be employed for next generation MOS applications.

Mechanisms and models of interface trap annealing in positively-biased MOS devices

Abstract We propose a hydrogen anion (H$^-$) passivation mechanism of the interface trap annealing (ITA) in positively-biased metal-oxide-semiconductor (MOS) devices. It is demonstrated that, the protons (H$^+$) released in SiO$_2$ due to H$_2$ cracking on oxide traps can migrate into Si at relatively high temperature, therefore passivating the interfacial $P_b$ centers by capturing two electrons provided by the positive bias. This new mechanism explains the elimination temperature of about 100$^\circ$C in experiments, which is much lower than temperature above 220$^\circ$C predicted by the traditional H$_2$ passivation mechanism. We also derive analytic models of the ITA, based on the coupling transformation dynamics of oxide and interface traps, as well as the concept of hierarchically constrained dynamics in glassy materials. These models can universally describe a generation-to-elimination transition of $P_b$, and predict the enhanced elimination of $E'_\gamma$ as the annealing temperature is elevated. Moreover, we demonstrate that, the defect annealing models can be applied to analysis the nonmonotonic temperature dependence of the annealing of threshold voltage shift in nMOS devices. Our findings provide a theoretical basis for achieving the low temperature elimination of interface traps, and for setting the high temperature stages of accelerated aging and damage evaluations of MOS devices.

Electron Irradiation on Metal Oxide Silicon Field Effect Transistors in Space Applications

The space environment is hostile to most semiconductor electronic devices and components used for space applications. The radiation generally encountered in space are α, β, γ, x-ray, energetic electrons, protons, neutrons and ions of various kinds. Especially the Van Allen Belts consist of high energy electrons which are in continuous motion. Satellites systems operating in Low Earth Orbits (LEO) are prone to get exposed to high energy electrons. This paper describes the effect of electron beam irradiation on MOSFETs planned for space applications. The devices selected for the study are 2N6768 n- channel MOSFETs (JANTXV) procured from ISAC, Bangalore. The decapped MOSFETS are exposed to a beam of electrons for various doses ranging from 50 Gy to 10 KGy in the electron energy range 7 – 10 MeV using the electron accelerator facility at RRCAT, Indore. Pre and post- irradiation measurements of the electrical characteristics are undertaken to investigate the electron induced device degradation and damage. The dominant mechanism of the interaction of the electrons with semiconductors is to produce atomic displacement which can have serious impact on electrical characteristics. MOS (Metal oxide semiconductor) devices are the most sensitive of all semiconductor devices to radiation showing considerable degradation even for a relatively low dose of exposure to high energy electrons. The energy dissipated by electrons in semiconductors is sufficient to displace silicon atoms and causes a shift in the threshold voltage and leakage current. The study indicates that the gate threshold voltage substantially decreases with the increase in electron dose. The leakage current increases with dose which could have an impact on the performance of the device. The transconductance of the MOS transistor is found to decrease with increase in electron dose. The observed changes in the electrical characteristics upon electron irradiation are analysed and interpreted as due to trapped charges in the SiO2 layer and at the interface. The present investigation reveals that there is a remarkable degradation in threshold voltage and the leakage current displays substantial increase when the devices are exposed to electrons. This increase in leakage current can have significant impact on device performance in a radiation environment.

Morphological Evolution of Atomic Layer Deposited Hafnium Oxide on Aligned Carbon Nanotube Arrays.

Microscopic study of the nucleation and growth of atomic layer deposition (ALD) dielectrics onto carbon nanotubes (CNTs) is an essential while challenging task toward high-performance devices. Here, we capture the morphological evolution and growth behaviors of ALD-HfO2 onto SiO2/Si-supported aligned CNT arrays (A-CNTs) under three ALD recipes via cross-sectional high-resolution scanning transmission electron microscopy. The HfO2 in ALD I (200 °C) preferentially nucleates on the SiO2 substrate in heterogeneous growth mode, resulting in films with considerable pinholes, while ALD II (90 °C) and III (90 °C and extra H2O presoak) exhibit homogeneous growth with nucleation on both SiO2 and CNTs, yielding uniform films. Arrangement defects in A-CNTs exacerbate nonuniformity of HfO2 and tube-tube separation plays deterministic roles affecting the HfO2-CNT interfacial morphology. Electrical measurements from A-CNTs metaloxide-semiconductor devices validate these findings. Our investigation contributes valuable insights for optimizing ALD processes for enhanced dielectric integration on A-CNTs in next-generation electronics.

Impact of Oxide Charges on The Minority Carrier Response in MOS(p) Devices With Al2O3/SiO2 Gate Stacks under Strong Inversion Condition

Admittance measurement, including capacitance and conductance, is very useful to analyze the electrical characteristics of metal-oxide-semiconductor (MOS) systems. These techniques offer insights into various device properties, including interface trap density and minority carrier lifetime in the substrate. It is essential to note that, apart from the gate area, the oxide region beyond the device could significantly influence measurement results [1]-[2]. In this work, a compact model proposed in [3] was used to clarify an unusual minority carrier response time observed in experimental data. The results proved the heightened sensitivity of device alternating current (AC) characteristics to oxide charges in the outer region. Additionally, the dependencies of oxide thickness and quality on the transition frequency (ωm) of devices were explored.The MOS (Al/AlOx/SiO2/p-Si) structure illustrated in Fig. 1 was employed in this study. Aluminum oxide region is under the gate electrode, while silicon oxide (SiO2) covers the entire wafer. Table 1 summarizes samples (S1 to S5) with consistent aluminum oxide thickness but diverse SiO2 thickness. Fig 2. shows the process flow and the anodic oxidation (ANO) system. By tilting the wafer at a specific angle during ANO, a high-quality SiO2 layer with different thicknesses on a single wafer could be obtained. Fig 3(a) to (d) illustrate the capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics of devices with varying SiO2 thicknesses. All devices exhibit low-frequency capacitance characteristics in strong inversion regions with thickness-dependent minority carrier response, particularly at 10kHz. Additionally, devices show different thicknesses depending on G-V characteristics at 1MHz and 10kHz. Fig 4(a) and (b) illustrate the Cinv/Cox ratio for varied oxide thicknesses and Gm/ω characteristics under strong inversion bias (VG = +3V). Gm means the measurement conductance. Following established research [3], peak Gm/ω magnitudes would occur at ωm. Table 2 reveals microsecond-range response times (τR) at ωm, considerably faster than conventional silicon minority carrier lifetimes (usually 1 ms to 100 ms). Moreover, decreasing oxide thickness shifts the ωm toward lower values.To explain this observed phenomenon, the environment outside the devices should be taken into consideration. Fig 5(a) and (b) show the schematic diagram and AC signal model proposed in [1] and [2]. Oxide charges in the outer region would deplete majority carriers and invert the p-type silicon surface to an n-type inversion layer. As a result, the lateral depletion region (Cd, out) and conductive channel (Rs) are formed outside the device, which are functions of substrate doping concentration and the effective oxide charges. The detailed model derivation is discussed in [2]. For this reason, an AC signal applied on the gate would extend outside the device for about a millimeter to a micrometer, affecting measuring results. Based on the model, the effective charges in the SiO2 could be extracted by measuring results. The thicker oxide has more oxide charges, as shown in Fig 6(a). Fig 6(b) and (c) show the modeling results of the Cinv/Cox ratio versus different oxide thicknesses and the Gm/ω-ω plot, which are very close to the experimental results. By simplifying the conductance formula (Gm), Gm reveals an inverse proportional to lateral effective conductance (GLeff) at low frequency (e.g., 10 kHz) and a direct proportional at high frequency (e.g., 1 MHz). Thicker SiO2 devices possess more oxide charges, leading to a greater lateral coupling effect, resulting in a greater GLeff compared to thinner devices. This elucidates the observed variations in Gm-V characteristics at 1 MHz and 10 kHz. Figures 7(a) and (b) display TCAD-simulated C-V and ωm for devices with varying oxide charge densities, confirming that minor changes in oxide charges result in noticeable differences in minority carrier responses in the strong inversion region. Fig 8(a) and (b) show the TCAD simulated results for devices with low doping substrate. For low doping substrates, oxide charges play a much more important role under AC operation.In summary, the study established a correlation between oxide charge densities and thicknesses. The origin of the faster minority carrier response and the peak shift in Gm/ω- ω plot were thoroughly explained and validated by TCAD simulation. Oxide charges were found to play a crucial role, especially in low-doping substrates, offering insights for advanced IC fabrication.[1] E. H. Nicollian and A. Goetzberger, IEEE Transactions on Electron Devices, vol. 12, no. 3, pp. 108-117, 1965.[2] K. C. Chen, K. W. Lin, S. W. Huang, J. Y. Lin, and J. G. Hwu, IEEE Journal of the Electron Devices Society, vol. 10, pp. 960-969, 2022.[3] S. Monaghan et al., IEEE Transactions on Electron Devices, vol. 61, no. 12, pp. 4176-4185, 2014. Figure 1

Research on single event effects and hardening design of LDMOS transistors

In this paper, an N-type Lateral Diffused Metal Oxide Semiconductor (LDMOS) device was designed using a heavily doped P+ well and drain N-type buffer layer structure in the BCD process. The hardened mechanism of heavily doped P+ well and drain N-type buffer layer structures was simulated and analyzed using a TCAD device simulator. To verify the anti-SEE performance of the LDMOS, the irradiation test was conducted using Ta ion (LET = 79.2 MeV·cm−2 mg−1). The results show that increasing P+ well doping concentration and using buffer layer structure can increase the single event burnout (SEB) voltage of high-voltage LDMOS devices. SEB did not occur within the full operation voltage range.

Programmable Optical Encryption Based on Electrical-Field-Controlled Exciton-Trion Transitions in Monolayer WS2.

Optical encryption is receiving much attention with the rapid growth of information technology. Conventional optical encryption usually relies on specific configurations, such as metasurface-based holograms and structure colors, not meeting the requirements of increasing dynamic and programmable encryption. Here, we report a programmable optical encryption approach using WS2/SiO2/Au metal-oxide-semiconductor (MOS) devices, which is based on the electrical-field-controlled exciton-trion transitions in monolayer WS2. The modulation depth of the MOS device reflection amplitude up to 25% related to the excitons ensures the fidelity of information, and the decryption based on the near excitonic resonance assures security. With such devices, we successfully demonstrate their applications in real-time encryption of ASCII codes and visual images. For the latter, it can be implemented at the pixel level. The strategy shows significant potential for low-cost, low-energy-consumption, easily integrated, and high-security programmable optical encryptions.

A review of emerging trends in photonic deep learning accelerators

Deep learning has revolutionized many sectors of industry and daily life, but as application scale increases, performing training and inference with large models on massive datasets is increasingly unsustainable on existing hardware. Highly parallelized hardware like Graphics Processing Units (GPUs) are now widely used to improve speed over conventional Central Processing Units (CPUs). However, Complementary Metal-oxide Semiconductor (CMOS) devices suffer from fundamental limitations relying on metallic interconnects which impose inherent constraints on bandwidth, latency, and energy efficiency. Indeed, by 2026, the projected global electricity consumption of data centers fueled by CMOS chips is expected to increase by an amount equivalent to the annual usage of an additional European country. Silicon Photonics (SiPh) devices are emerging as a promising energy-efficient CMOS-compatible alternative to electronic deep learning accelerators, using light to compute as well as communicate. In this review, we examine the prospects of photonic computing as an emerging solution for acceleration in deep learning applications. We present an overview of the photonic computing landscape, then focus in detail on SiPh integrated circuit (PIC) accelerators designed for different neural network models and applications deep learning. We categorize different devices based on their use cases and operating principles to assess relative strengths, present open challenges, and identify new directions for further research.

Interface States in Gate Stack of Carbon Nanotube Array Transistors.

A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high reliability. Although MOSFETs built on aligned semiconducting carbon nanotube (A-CNT) arrays have been considered ideal energy-efficient successors to commercial silicon (Si) transistors, research on the interface states of A-CNT MOS devices, let alone their optimization, is lacking. Here, we fabricate MOS capacitors based on an A-CNT array with a well-designed layout and accurately measure the capacitance-voltage and conductance-voltage (C-V and G-V) data. Then, the gate electrostatics and the physical origins of interface states are systematically analyzed and revealed. In particular, targeted improvement of gate dielectric growth in the A-CNT MOS device contributes to suppressing the interface state density (Dit) to 6.1 × 1011 cm-2 eV-1, which is a record for CNT- or low-dimensional semiconductors-based MOSFETs, boosting a record transconductance (gm) of 2.42 mS/μm and an on-off ratio of 105. Further decreasing Dit below 1 × 1011 cm-2 eV-1 is necessary for A-CNT MOSFETs to achieve the expected high energy efficiency.

Tuning of interface quality of Al/CeO2/Si device by post-annealing of sol-gel grown high-k CeO2 layers

A comprehensive study has been done on the influence of post-deposition annealing temperature on high-k cerium oxide (CeO2) layer grown on n-type silicon (Si) substrate and its resultant interface states have been studied for Al/CeO2/Si metal-oxide-semiconductor (MOS) devices. The high-k CeO2 thin films were deposited by spin-coating and sintered at different annealing temperatures (Ta) in the range of 400–900 °C. The parameters such as fixed charge density (Qeff), dielectric constant (k) of the layers, flat-band voltage (VFB), interface defect density (Dit), etc., of the MOS device were evaluated from CV and I-V measurements. A minimum value of flat band shift (∼0.05 V) with lower Qeff (−4.81 × 1011 C/cm2) have been achieved for the Ta of 600 °C. The k and Dit were evaluated to be 22 and 1.29 × 1012 cm−2, respectively at the Ta of 600 °C. In addition, the CV measurements showed a very small hysteresis and very low frequency dispersion for the Ta of 600 °C sample. Energy distribution of defect states was evaluated and it was maximum towards the bottom of the conduction band. This shows that the 600 °C is the optimum annealing temperature, which results in high quality interface, and the electron affinity of the corresponding CeO2 layers was found to be 3.29 eV as evaluated from ultraviolet photoelectron spectroscopy (UPS). Further, a maximum value of minority carrier lifetime (147 μs) has been achieved for the samples annealed at Ta of 400 °C, indicating that the post-annealing temperature plays a significant role on the properties of CeO2 films deposited by sol-gel process. Thus, the present study demonstrates the possibility of sol-gel grown high k-CeO2 layers suitable for MOS like devices.

Spin coating high‐k multicomponent (Al,Ti,V,Zr,Hf)Ox films with sub‐nm EOT for MOS‐based electronic devices

AbstractThe facile spin coating fabrication of high‐dielectric‐constant (high‐k) multicomponent (Al,Ti,V,Zr,Hf)Ox films with an equivalent oxide thickness of ≈0.95 nm and the investigation of their thermal stability and dielectric and electrical properties of the resulting advanced metal–oxide–semiconductor (MOS)‐based electronic devices are reported in this study. Various heating conditions, including drying following spin coating, annealing after drying, and forming gas annealing, were investigated to optimize the quality of the films and reduce film defects. The favorable film‐based MOS devices exhibited robust capacitance–voltage (C–V) and current–voltage (I–V) characteristics with a remarkable k value of approximately 62 at 1 kHz. The thermal stability of the films was affirmed through a rapid thermal annealing treatment at 900°C for 5 s and observation of nondegraded C–V and I–V curves. The electrical performance of the resulting MOS field‐effect transistors (MOSFETs), including a threshold voltage of 0.4 V, an on/off ratio of 106, a saturated mobility of 40.1 cm2 V−1 s−1, and a subthreshold swing of 66.7 mV dec−1, was obtained. Moreover, hole‐ and electron‐trapping measurements through negative and positive gate bias stress instabilities, respectively, indicate the reliable performance of our MOSFETs. Our results imply that solution‐based processes are promising for fabricating fundamental semiconductor devices.

Hydrogen-like impurities in Si and Ge quantum dots in connection with 5 nm and beyond metal-oxide-semiconductor technologies

The industrial drive towards smaller semiconductor devices is at less than 10 nano-meters. In the next few years a three-dimensional quantum confined device structure is expected. We have studied the electronic structure of hydrogen-like donor impurities in Si and Ge quantum dots with varied shape of the confinement potential. These calculations are carried out within the Density-Functional-Effective-Mass Theory (DF-EMT). We have paid particular attention to the electron-electron interaction energy in a negative charge state of the donor impurity. The effect of electron correlation on the binding energy has been explored. In addition to these, we show that the second order correction to the ground state energy obtained through perturbative approach agrees well with the DF-EMT based numerical results, down to very small sizes of the quantum dots when the depth of the confinement is moderate or small. A non-monotonic shallow-deep transition of the binding energy of neutral and charged donors of hydrogen-like impurities is expected to occur with the reduction in the size of the quantum dot. A similar effect is expected for hydrogen-like acceptor impurities as well. Furthermore, the optical gap also shows non-monotonic shallow-deep behaviour with the quantum dot size reduction. Deepening of shallow donor or acceptor level implies that the carriers will freeze out at small sizes of the dot. We believe this is quite important in the context of metal-oxide-semiconductor (MOS) devices beyond 5 nm technologies, based on Si, Ge or a combination (SiGe). We also point out possible variabilities in the binding energy of donors and acceptors if there are variations in the size of host quantum dots in a large assembly of devices in future integrated circuits. This will lead to the variabilities in the characteristics from device to device. These results should be incorporated in the Technology Computer Aided Design (TCAD) simulation of less than or equal to 5 nm MOS devices.

CMOS Compatible Hydrogen Sensor Using Platinum Gate and ALD-Aluminum Oxide.

In this study, a p-Si/ALD-Al2O3/Ti/Pt MOS (metal oxide semiconductor) device has been fabricated and used as a hydrogen sensor. The use of such a stack enables a reliable, industry-compatible CMOS fabrication process. ALD-Al2O3 has been chosen as it can be integrated into the back end of the line (BEOL) or in CMOS, post processing. The device response and recovery are demonstrated with good correlation between the capacitance variation and the hydrogen concentration. Detection down to 20 ppm at 140 °C was obtained and a response time of 56 s for 500 ppm was recorded.

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

Performance improvements in complementary metal oxide semiconductor devices and circuits based on fin field-effect transistors using 3-nm ferroelectric Hf0.5Zr0.5O2

In this work, a conventional HfO2 gate dielectric layer is replaced with a 3-nm ferroelectric (Fe) HZO layer in the gate stacks of advanced fin field-effect transistors (FinFETs). Fe-induced characteristics, e.g., negative drain induced barrier lowering (N-DIBL) and negative differential resistance (NDR), are clearly observed for both p- and n-type HZO-based FinFETs. These characteristics are attributed to the enhanced ferroelectricity of the 3-nm hafnium zirconium oxide (HZO) film, caused by Al doping from the TiAlC capping layer. This mechanism is verified for capacitors with structures similar to the FinFETs. Owing to the enhanced ferroelectricity and N-DIBL phenomenon, the drain current (IDS) of the HZO-FinFETs is greater than that of HfO2-FinFETs and obtained at a lower operating voltage. Accordingly, circuits based on HZO-FinFET achieve higher performance than those based on HfO2-FinFET at a low voltage drain (VDD), which indicates the application feasibility of the HZO-FinFETs in the ultra-low power integrated circuits.Graphical abstract

Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology

Designing a power efficient and high-speed static random-access memory (SRAM) cell with improved noise stability using traditional complementary metal oxide semiconductor (CMOS) devices is an arduous task. Owing to balanced electrical properties of graphene nanoribbon field-effect transistor (GNRFET), its capability to realize high performance SRAM cells need a keen exploration. This article proposes an 11-transistor GNRFET SRAM cell which deploys hybrid inverter scheme. The hybrid inverter scheme encompasses two distinct inverters, based on stacked transistors and Schmitt trigger (ST) techniques. The simulations conducted using 16 nm GNRFET model in HSPICE simulator show that proposed SRAM cell has write power, hold power, read power, write static noise margin, hold static noise margin, read static noise margin, write delay and read delay of 0.445 nW, 0.978 µW, 1.8 nW, 225 mV, 222.8 mV, 225.1 mV, 24 pS and 49.6 pS, respectively. The results obtained for proposed SRAM cell have been found to be encouraging in contrast to previously reported SRAM cells implemented using 16 nm GNRFET model. Besides this, the effect of variation in various parameters of GNRFET on performance of proposed SRAM cell has been investigated in this article. The outstanding performance results of SRAM makes its suitable for developing high performance memories devices for biomedical digital gadgets, internet of things (IoT), artificial intelligence (AI) and smart agricultural applications.

Optimizing interface properties of HfO2/Si0.73Ge0.27 gate stacks through sulfur passivation and post-deposition annealing

This paper presents a comprehensive exploration of low interface trap density (Dit) in HfO2/Si0.73Ge0.27 metal-oxide semiconductor (MOS) capacitors achieved through sulfur passivation and post-deposition annealing (PDA). Our investigation revealed that devices subjected to sulfur passivation and PDA exhibit noteworthy reductions in Dit and hysteresis. Specifically, a low Dit value of 1.2 × 1011 eV−1 cm−2 has been achieved at Ei–0.1 eV for the SiGe MOS device. The observed enhancement in interface properties can be attributed to two key factors: the reduction of the GeOx concentration in the interfacial layer (IL) by sulfur passivation on the SiGe surface and the IL densification with stoichiometric oxygen during PDA.

The impact of sputtering pressure on the TiO2/p-Si interface and its implications for hole-blocking and photodetection

One convenient approach to minimize the surface recombination loss in Si is to passivate the surface dangling bonds by depositing a thin TiO2 layer on the bulk Si. Besides, the p-Si/TiO2 interface can initiate hole-blocking and facilitate efficient electron transport through the TiO2 layer; thereby, promoting the extraction of electrons for efficient onward utilization. In this context, the current investigation involves studying how the Ti3+ donor states, produced by deliberately introducing O-vacancies controlled by changing the plasma pressure in the RF-magnetron sputtering chamber during the growth of the TiO2 thin films, can change the material's Fermi level and work function and modify the band bending and band offset as well as the fixed oxide charge density in the p-Si/TiO2 heterojunction interface. The TiO2/p-Si interface has been studied through capacitance-voltage (C-V) analysis to determine the interface parameters such as fixed oxide charge, the density of interface traps, and the dielectric constant of TiO2. The studied hole-blocking property of the interface has been correlated to the photoresponsivity of the metal-oxide-semiconductor (MOS) structure. The MOS device fabricated at a pressure of 30 mTorr displays a large saturation current (15.95 μA cm–2) when subjected to a positive gate bias, facilitated by the relatively low conduction band offset (ΔEC ∼0.20 eV), significant positive fixed oxide charge (+1.18 ×1011 cm–2) and the interface trap density (1.03 ×1012 cm–2), which enhanced the transport of minority carrier electrons from the p-Si to the metal, resulting in a good photo responsivity ∼0.158 AW–1 and photo gain of ∼37.5 under white light illumination. Optimum hole-blocking and surface passivation characteristics of the TiO2/p-Si interface together may facilitate fabricating improved heterojunction Si solar cells.

Investigation of dual work function metal (DWFM) gate stacks with ALD TaAlN and TaAlC for multi threshold voltages (VTHs) engineering in MOS device integration

This study investigates methods to modulate the effective work function (EWF) and control the multiple threshold voltages (VTHs) of metal-oxide-semiconductor (MOS) devices by applying metal electrodes with different work function materials (WFMs), including a single layer of n-type (TaAlC) and p-type (TaAlN) as well as their stacked structures, through atomic layer deposition (ALD). Dual-Work-Function-Metal (DWFM) gate is a crucial aspect of confirming the feasibility of metal gate stacks in MOS devices for a complementary metal-oxide-semiconductor (CMOS) integration scheme. The gate stack structure of p-Si/IL (Inter layer)/HfO2/DWFM (p/n-type compatible metal stack)/W exhibits good adhesion and even chemical composition distribution, as evidenced by transmission electron microscope (TEM) and energy dispersive spectrometer (EDS) analysis. By fabricating MOS capacitors using this WFM structure and extracting EWF from the measured capacitance-voltage (C–V) characteristics, EWF values of 4.62 eV and 4.99 eV were identified both before and after annealing using forming gas, indicating pWFM-like properties. These properties are attributed to the strengthened Al–O bonds and reduced CO peaks seen in x-ray photoelectron spectroscopy (XPS) analysis. The use of different Ta precursor from Tris(diethylamido)(tert-butylimido)tantalum(V) (TBTDET) as well as TaCl5 resulted in the increase of the EWF following the unique p-WFM like feature. As candidates for WFM electrode in metal-oxide-semiconductor field effect transistor (MOSFET) with the DWFMs (n/p stacks) were evaluated, resulting in a VTH of 0.84 V that places in the middle of the VTH shift range from 0.6 V (nWFM) to 1.16 V (pWFM), approximately. The DWFMs allow for modulation of the EWF, which in turn reduces ambiguity in addressing replacement metal gate (RMG) challenges and opens up new avenues for achieving multi-VTH solutions in CMOS integration schemes.

Characterization of nitrided SiC(1 [formula omitted] 00) MOS structures by means of electrical measurements and X-ray photoelectron spectroscopy

Interface nitridation in nitric oxide is a standard technique for improving the performance of silicon carbide (SiC) metal-oxide-semiconductor (MOS) devices. In this study, we focused on m-face SiC MOS structures and investigated the impact of nitridation by means of electrical measurements and X-ray photoelectron spectroscopy (XPS). Gate leakage characteristics were measured in a wide temperature range of about −150 – 100 °C, which clarified that nitridation leads to an unwanted increase in the Fowler-Nordheim leakage current. Scanning XPS measurements revealed that the amount of nitrogen incorporated at the m-face MOS interface could reach about 2.3 times higher than the Si-face MOS interface. The incorporation of nitrogen likely reduces the conduction band offset at the SiO2/SiC interface, thereby increasing the gate leakage. This conclusion was further corroborated in an analysis of band alignment based on synchrotron radiation XPS measurements. Therefore, while nitrided m-face SiC MOS devices exhibit superior on-state performances, they have a limitation in terms of reliability.