MOS Capacitors Research Articles

Effect of NO annealing on radiation detection performance of Ni/SiO2/4H-SiC MOS capacitors

In this study, Ni/SiO2/4H-SiC metal-oxide-semiconductor (MOS) devices were fabricated, achieving high-energy resolution for alpha particle radiation detection. The SiO2/4H-SiC interface was treated with two different methods: i) annealing in N2 environment, ii) annealing in NO environment. Devices manufactured using the former method show lower dark currents than the latter. This difference is due to a decrease in trap density at the SiO2/4H-SiC interface caused by NO annealing, resulting in a higher barrier height for the device. The NO-30 exhibited a much higher energy resolution of 0.46%@5486 keV compared to 0.95%@5486 keV observed in N2-30, despite both devices exhibiting good energy linearity in response to alpha particles. The SiO2/4H-SiC interface trap density revealed a significant decrease after NO treatment, indicating NO treatment can effectively improve the electrical performance of 4H-SiC MOS devices. CCE analysis showed the NO-30 had a lower surface recombination field (13000 V/cm) compared to N2-30 (35000 V/cm), which improves the charge collection efficiency and energy resolution. This study provides a practical approach for enhancing the energy resolution of 4H-SiC MOS detectors.

Silica conversion of polysilazanes by low-temperature plasma jet generated from Ar and water-vapor mixed gas

Perhydropolysilazane (PHPS), which contains no organic catalyst, chemically reacts with H2O in the atmosphere by heating it at 450 °C for more than 1 h to turn it into a SiO2 film. If silica conversion can be achieved at temperatures below 100 °C, which plastics can withstand, it may be applicable to a wide range of applications, such as flexible electronics. Here, we report a technique for forming SiO2 films with leakage current characteristics very close to those of thermally oxidized (THOX) films that works at a very low temperature of 52 °C with high speed. Using a 9-kV, 30-kHz power supply, a low-temperature plasma jet containing a gas mixture of Ar and water vapor irradiated an 8 nm thick PHPS thin film, inducing silica conversion at a maximum substrate temperature of 52 °C. The current density-electric field strength (J-E) characteristics of metal oxide semiconductor capacitors fabricated with this SiO2 film showed characteristics very close to those of THOX films. In addition, the mechanism of silica conversion of PHPS through low-temperature plasma jet irradiation using this gas mixture was clarified in real-time FT-IR measurements.

High-temperature time-dependent dielectric breakdown of 4H-SiC MOS capacitors

—With the rapid applications of silicon carbide metal–oxide–semiconductor field-effect transistor (SiC MOSFET) power devices, further improving the performance of SiC MOSFET device through enhancing its gate oxide reliability is one of the crucial directions. The density of interface states in a SiC MOSFET is a significant parameter that affects the reliability of the gate oxide layer. In this paper, the SiC MOS capacitors (MOSCAPs) were prepared by the 1250 °C dry oxidation and 1350 °C NO annealing process. Then, we analyzed the mechanisms of the breakdown by two group of ramped experiment. And we still evaluated the reliability of oxide layer via the high-temperature time-dependent dielectric breakdown (TDDB) tests on the prepared MOSCAPs, meanwhile, the temperature effect on the reliability was considered. Furthermore, the E, 1/E, and E models with Weibull plotting were used to calculate the tBD lifetimes and failure analysis was carried on the failed samples finally. The results indicate that: (1) the impact of the generation and accumulation of the traps in the oxide, which is the main mechanisms of device failure; (2) The prediction of lifetime was calculated with three models at different acceleration factors; (3) at high-temperature, although the lower the density of interface states is, the Si epitaxial growth and C cluster will manifest in the oxide surface and lead to the breakdown of SiC MOSCAPs.

Research on high dynamic pixel structure based on adaptive integral capacitor

Infrared image sensing technology has attracted wide attention due to its advantages such as being unaffected by the environment, good target recognition, and strong anti-interference ability. However, with the improvement of the integration of infrared focal planes, the constraints between the dynamic range, noise, and full-shade of the optoelectronic system are particularly prominent. Therefore, in order to solve the contradiction between noise in weak light and full-shade capacity in strong light, in a 5 T infrared pixel circuit, the relationship between the capacitance value and voltage of the inverted MOS capacitor in a specific voltage range is used to make the integral capacitance of the infrared image sensor automatically change from 6.5 fF to 37.5 fF. A high dynamic pixel structure based on adaptive integral capacitance is proposed. Based on 55 nm CMOS process technology, 12288 × 12288its performance parameters are studied in a pixel-scale infrared sensor. The research results show that 5.5m × 5.5mthe small-size pixel has a large full-shade capacity of 1.31 Me- and a variable conversion gain, a noise of less than 0.43 e, and a dynamic range of more than 130 dB.

Low-pressure oxidation for improving interface properties and voltage instability of SiO2/4H-SiC MOS capacitor

The impact of high-temperature sub-atmospheric oxidation pressure on the interface properties of n-type 4H-SiC metal–oxide–semiconductor capacitors has been systematically investigated in this report. The bias temperature instability measurement was used to calculate the mobile ions and near-interface trap density that led to device instability at high temperatures. The density of near interface traps decreased from 88.3 × 1011 cm−2 to 10.2 × 1011 cm−2 when the growth pressure of SiO2 was reduced from 1 atm to 0.1 atm, while the mobile ions density decreased from 83.5 × 1011 to 4.18 × 1011 cm−2. The results show that SiO2 growing under lower oxidation pressure has better interfacial quality. The underlying mechanism was explored by secondary ion mass spectrometry (SIMS) and x-ray photoelectron spectroscopy (XPS). It is speculated that the SiO2/SiC interface was reconstructed under low-pressure oxidation: the excess Si-related defects near the interface, such as SiOxCy, were released while O atoms were accumulated to promote a complete oxidation reaction, thereby effectively reducing the number of defects in the SiO2 film and improving device performance.

Enhancement of dielectric constant in Sm:Zr co-doped HfO2 films synthesized by cost-effective method

Sm, Zr co-doped HfO2 films were deposited on a p-type silicon wafer using a cost-effective spin coating method. The influence of Sm, Zr co-doping concentration variation on structural, compositional, morphological, and electrical properties was examined. The dominance of the orthorhombic phase (o-phase) in comparison to the monoclinic phase was noted to rise with the simultaneous increment of Sm doping concentration and decrement of Zr concentration. A decrease in oxygen vacancies was noted for all the Sm, Zr co-doped HfO2 films from XPS results. Nonporous and uniform distribution of grains was observed from Field Emission Scanning Electron Microscope (FESEM) and Atomic Force Microscopy (AFM) studies. Electrical studies of MOS capacitors based on Sm, Zr co-doped HfO2 films revealed a low leakage current. C-V studies exhibited an increment of dielectric constant and a decrement of interface trap densities. Further, to obtain insights into the microscopic features of Sm, Zr co-doped films, impedance and modulus studies have been performed. The obtained results imply the potential of tuning Sm, Zr co-doping concentrations in HfO2 towards stabilization of the orthorhombic phase and to enhance the dielectric constant of the films.

RF Characterization of Ferroelectric MOS Capacitors

RF Characterization of Ferroelectric MOS Capacitors

Degradation mechanism of SiC diodes under thermal and irradiation stress

Abstract Silicon carbide (SiC)-based diodes are widely used due to their high temperature resistance. In this paper, breakdown voltage of 4H-SiC JBS diodes and capacitance-voltage of 4H-SiC MOS capacitors with identical interfacial structure were both measured at high temperature to study their interfacial properties. By analyzing the variation of interfacial properties, the correlation between thermal stress and failure mode of 4H-SiC JBS diodes was further established to reveal their degradation mechanism. During initial high temperature storage, interfacial negative effective charge density of 4H-SiC JBS diodes may increase, leading to the decrease of breakdown voltage. As storage time increases, interfacial charge density began reducing, resulting in the increase of breakdown voltage. Avalanche luminescence verifies that the variation of interfacial charge density under thermal stress led to the degradation of 4H-SiC JBS diodes and further affected their breakdown voltage. Finally, degradation mechanism of SiC-JBS, SiC-SBD and SiC-PIN diodes under irradiation stress was investigated. After irradiation, forward current of some SiC diodes increased at a small forward voltage. However, the reverse characteristics deteriorated obviously and even failed.

Investigations into the Impact of Deposition or Growth Techniques on the Field Oxide TID Response for 4H-SiC Space Applications

The total ionising dose (TID) reliability of a phosphorous pentoxide (P2O5) treated SiO2 (silicon dioxide) layer is compared for the first time to other industrially relevant oxides formed on 4H-silicon carbide (SiC). Metal-oxide-semiconductor capacitors (MOSCAPs) are characterised before and after irradiation to ascertain changes in flat band voltage shift, leakage current, and dielectric breakdown (BV). Secondary ion mass spectrometry (SIMS) profiling reveals a significant phosphorus concentration near the SiO2/SiC interface, which led to improved TID resistance. The P2O5 treated oxide had the lowest leakage current at high voltage bias due to the high-temperature (1,000°C) anneal, though it had a significantly negative flat band voltage due to the high concentration of deposited phosphorus atoms. The thermal and P2O5 oxides demonstrated a TID resistance, suffering only minor shifts in flat band voltage, while the P2O5 oxide suffered the smallest decrease in its BV and the smallest leakage current rise, post-irradiation.

Electronic Properties of Atomic Layer Deposited HfO2 Thin Films on InGaAs Compared to HfO2/GaAs Semiconductors

This paper demonstrates how the treatment of III-V semiconductor surface affects the number of defects and ensures the conformal growth of the high-k dielectric thin film. We present the electrical properties of an HfO2/InGaAs-based MOS capacitor, in which growth temperatures and surface treatments of the substrate are two key factors that contribute to the uniformity and composition of the HfO2 thin films. A remarkable asymmetry observed in capacitance versus voltage measurements was linked to the interface defects and charge redistribution, as confirmed from X-ray photoelectron spectroscopy. The GaAs substrates that were etched with only NH4OH showed a large frequency dispersion and a higher surface roughness; however, the HfO2 thin films grown on GaAs pre-treated with both NH4OH etching and (NH4)2S passivation steps produced a desirable surface and superior electronic properties.

SiC MOSFET Gate Oxide Quality Improvement Method in Furnace Thermal Oxidation with Lower Pressure Control

We have investigated carbon behavior resulting from pressure control in furnace thermal oxidation process and evaluated the effect on gate oxide quality resulting from this pressure control. In order to investigate the potential reduction of carbon defects by reducing CO and CO2, an analysis of oxidized SiC wafers was conducted. To evaluate the effect of pressure control related carbon component change during thermal oxidation, QBD characteristic was evaluated in SiC MOS Capacitance. The analysis results revealed on observable decrease in carbon at the SiO2/SiC interface and the SiO2 layer. The QBD results shown that improved at lower pressure better than those obtained in the general pressure.

(Invited) Consideration on Gate Stack Formation Processes of Ultrawide Bandgap Ga2O3 with SiO2 Dielectric Layer

MOSFETs on β-Ga2O3 are expected to be a high-efficient and cost-effective alternative option of high-voltage power devices. Taking account of the reliability and the large conduction-band offset against β-Ga2O3, it would be reasonable to employ SiO2 as the gate dieletric. In this study we investigated the effects of post-deposition annealing (PDA) on SiO2/β-Ga2O3 MOS gate stacks, in terms of the MOS electrical characteristics and the band alignment.β-Ga2O3 (001) wafers with ~2×1016 cm-3 n-type doped epitaxial layers were cleaned in diluted HF solution, and SiO2 films were deposited by electron-beam (EB) evaporation of Si in O2 ambient of ~1×10-2 Pa, followed by PDA at various temperatures from 600 to 1000℃ in either O2 or N2 ambient. Au was evaporated as gate electrode to form MOS capacitors. X-ray photoelectron spectroscopy (XPS) was conducted on the stacks with ~3nm-thick SiO2 for the evaluation of band alignment. Ultraviolet photoelectron spectroscopy (UPS) was also employed to determine the band diagram of β-Ga2O3 (001).Nearly-ideal capacitance-voltage characteristics were obtained for the MOS capacitor fabricated with O2-PDA at 1000℃. The interface state density (Dit) determined by conductance method decreased down to ~1010 cm-3 at the energy level of EC−0.2 eV by PDA at higher temperature. The hysteresis width (ΔVhys) of C-V curves was smaller for the samples annealed at higher temperatures. The flatband voltage (VFB) shift after O2-PDA resulted in VFB close to the ideal value estimated from the physical properties of Au and Ga2O3, suggesting that fixed charge density at the interface would be minimized. However, PDA in N2 at 1000℃ resulted in a negative shift of VFB, which indicates the formation of positive fixed charges in the stack. The beneficial influences of O2-PDA on those characteristics suggest that an oxygen deficiency introduced near the interface is one of the origins of interface defect states. It is noteworthy that Ga3d XPS on the surface of Ga2O3 substrate always shows a tailing in lower binding energy side, which is indicating oxygen deficiency on the surface. The intensity of this lower-binding-energy component reduced significantly when a bare-Ga2O3 substate was annealed in O2, however, it did not decrease efficiently even after O2-PDA when the surface was covered with SiO2. This is probably due to the oxygen rearrangement at SiO2/Ga2O3 interface determined by the difference of material properties of those oxides. This fact suggests that the Ga2O3 surface easily forms oxygen vacancies when it is covered with SiO2. This would be the reason why the formation of interface defect states is not suppressed without O2-PDA.Next the band diagram of β-Ga2O3 (001) substrate was investigated by UPS analysis where the energy level of valence band edge referring to the vacuum level was evaluted from the energy difference between minimum (cut-off) and maximum edges of the obtained kinetic energy spectra of photoelectrons. As a result we found the valence band edge of of β-Ga2O3 (001) was ~8.2 eV below the vacuum level, where the influences of O2 annealing at 1000℃ on the valence band edge energy level was limited to the shift within ~0.1eV. This would tell us the valence band offset between SiO2 and Ga2O3 should be around ~1.1eV, and the conduction band offset between them is to be around 2.8-2.9eV, by taking account of the well-reported SiO2 band diagram and assuming the bandgap of β-Ga2O3 as 4.7eV. On the other hand, the valence band offset estimated from the deconvolution of the XPS valence band spectrum for a ~3nm-thick SiO2/β-Ga2O3 stack from the energy edge difference between the deconvoluted spectra corresponding to SiO2 and Ga2O3, was a few hundreds of mV smaller than the above expected value (~1.1eV). This discrepancy is indicating the formation of an interface dipole layer between SiO2 and Ga2O3 with a pair of nagative and positive charges aligned at the interface to cause a shift in the band alignment. The magnitude of such dipole was indicated to be more significant (~0.5eV) for the stack after PDA at 1000℃, whereas it was less (0.2~0.3eV) after PDA at 600℃.In conclusion, we demonstrated that SiO2/β-Ga2O3 (001) MOS capacitors showed nearly-ideal electrical characteristics with significantly reduced interface defect density and small fixed charge density by applying O2-PDA. The band alignment of SiO2/β-Ga2O3 (001) MOS stack was clarified by photoelectron spectroscopy to confirm a very large conduction band offset of the stack, but an influence of the formation of interface dipole layer between SiO2 and Ga2O3 on the band alighment was also indicated.

Morphological, Optical, and Electrical Properties of a MOS Capacitor Based on Rare Earth Oxide and p-Porous GaAs

Morphological, Optical, and Electrical Properties of a MOS Capacitor Based on Rare Earth Oxide and p-Porous GaAs

Interface States in Gate Stack of Carbon Nanotube Array Transistors.

A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high reliability. Although MOSFETs built on aligned semiconducting carbon nanotube (A-CNT) arrays have been considered ideal energy-efficient successors to commercial silicon (Si) transistors, research on the interface states of A-CNT MOS devices, let alone their optimization, is lacking. Here, we fabricate MOS capacitors based on an A-CNT array with a well-designed layout and accurately measure the capacitance-voltage and conductance-voltage (C-V and G-V) data. Then, the gate electrostatics and the physical origins of interface states are systematically analyzed and revealed. In particular, targeted improvement of gate dielectric growth in the A-CNT MOS device contributes to suppressing the interface state density (Dit) to 6.1 × 1011 cm-2 eV-1, which is a record for CNT- or low-dimensional semiconductors-based MOSFETs, boosting a record transconductance (gm) of 2.42 mS/μm and an on-off ratio of 105. Further decreasing Dit below 1 × 1011 cm-2 eV-1 is necessary for A-CNT MOSFETs to achieve the expected high energy efficiency.

Impact of NaOH solution surface treatment on Al2O3/β-Ga2O3 MOS capacitors

A suitable semiconductor surface treatment could improve the gate dielectric quality and reduce the interface states and traps to enhance the performance of metal–oxide semiconductor capacitors (MOSCAPs). In this paper, β-Ga2O3 surface treatment using NaOH solution prior to atomic layer deposition of Al2O3 was investigated. In comparison with piranha pretreatment, MOSCAPs with NaOH solution surface pretreatment show a larger maximum accumulation capacitance with less frequency dispersion, reduced charges/traps and interface state density D it. The improvement in MOSCAPs performance could be attributed to the NaOH solution pretreatment induced slight surface etching effect and relatively effective hydroxylation surface. These results suggest that the process optimization of NaOH solution surface pretreatment could lead to further improvement of β-Ga2O3 MOSCAPs and have a potential in application of β-Ga2O3 metal–oxide semiconductor field-effect transistors in the future.

SiO2‐GaN Interface Improvement by Wet Cleaning and In Situ Annealing for GaN MOS Transistors

Herein, ex situ wet cleaning and in situ high‐temperature annealing of GaN surfaces prior to low pressure chemical vapor deposition (LPCVD) of the SiO2 gate oxide, aiming at effective SiO2‐GaN interface engineering for channel improvement of metal–oxide semiconductor (MOS) transistors, are investigated. Additionally, the combination of in situ annealing and gate oxide deposition in an LPCVD tool provides the advantage of an industrially preferred batch process. A strong impact of the pretreatments on the interface state density and flatband voltage of the fabricated n‐type GaN MOS capacitors is demonstrated. Combined HF wet cleaning and NH annealing result in a low peak interface state density and a close to ideal C–V curve with a nearly ideal flatband voltage . Furthermore, the I–V characteristics exhibit a positive voltage shift of the current onset and substantially reduced I‐V hysteresis, i.e., negligible temporary charging. Physical root causes are assumed to be reduced contamination due to nondestructive yet efficient HF cleaning combined with subsequent high temperatures and the reduction of near‐interface, quasi‐permanent traps due to the saturation of dangling bonds by the annealing in hydrogen‐containing atmosphere.

Impact of Process on Gate Leakage Current and Time-Dependent Dielectric Breakdown Failure Mechanisms of 4H-SiC MOS Capacitors

Impact of Process on Gate Leakage Current and Time-Dependent Dielectric Breakdown Failure Mechanisms of 4H-SiC MOS Capacitors

Dependence of the incorporated boron concentration near SiO2/4H–SiC interface on trap passivation reduction

By systematically varying the boron concentration near the oxide/4H–SiC interface within a specifically designed boron-diffusion layer oxide structure, this paper explores the influence of boron concentration on interface state density and near-interface trap density in 4H–SiC MOS capacitors. Additionally, the effect of boron near the oxide/4H–SiC interface on device stability under elevated temperature conditions was examined. The boron species were introduced into the SiO2/4H–SiC interface by spin coating followed by annealing, whose temperature controls the amount of boron present in the near interface region. It is suggested that a higher concentration of boron leads to a better trap passivation effect while preserving the stability of flat band voltage.

Exploring the border traps near the valence band in the SiO2 - SiC system using above-band-gap optical excitation

Studying near-valence-band (EV) defects at the insulator–n-type 4H-SiC interface is challenging due to the low minority carrier concentration. Herein, we present a technique for characterizing the border traps near EV in an n-type 4H-SiC MOS capacitor by generating holes using above-band-gap optical excitation (OE). A rise in capacitance was observed under OE (due to hole capture by border traps), remaining stable long after the optical stimulus was removed, resulting in a persistent photocapacitance effect. We show the dynamics of the capture process and perform a quantification of the captured holes in samples with thermally grown oxide and different postoxidation annealing treatments. Published by the American Physical Society 2024

Simultaneous electric dipoles and flat-band voltage modulation in 4H-SiC MOS capacitors through HfO2/SiO2 interface engineering

We report an approach to simultaneously tune the electric dipoles and flat-band voltage (V FB) of 4H-silicon carbide (SiC) metal-oxide-semiconductor (MOS) capacitors through high-k oxide dielectric interface engineering. With an additional HfO2 thin layer on atomic layer deposition (ALD) of SiO2 film, a dipole layer was formed at the HfO2/SiO2 interface, leading to a small positive shift of the V FB of 0.3 V in 4H-SiC MOS capacitors. The Kelvin probe method was used to examine the dipole layers induced at the direct-contact oxide/4H-SiC interfaces. It was found that a minor difference of 0.3 V in the contact potential difference (V CPD) is observed between the SiO2/4H-SiC and HfO2/SiO2/4H-SiC stacks, which signifies the presence of a weak interface dipole layer at the interface of HfO2 and SiO2. Additionally, investigation of the interface state density reveals that ALD of the HfO2 process had a negligible impact on the quality of the SiO2/4H-SiC interface, suggesting that the observed small positive V FB shift originated from the HfO2/SiO2 interface rather than the SiO2/4H-SiC interface.